arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /*
   3  * Copyright 2021-2022 TQ-Systems GmbH
   4  * Author: Alexander Stein <alexander.stein@tq-group.com>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/leds/common.h>
  10 #include <dt-bindings/net/ti-dp83867.h>
  11 #include <dt-bindings/pwm/pwm.h>
  12 #include "imx8mp-tqma8mpql.dtsi"
  13
  14 / {
  15         model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL";
  16         compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
  17
  18         chosen {
  19                 stdout-path = &uart4;
  20         };
  21
  22         iio-hwmon {
  23                 compatible = "iio-hwmon";
  24                 io-channels = <&adc 0>, <&adc 1>;
  25         };
  26
  27         aliases {
  28                 mmc0 = &usdhc3;
  29                 mmc1 = &usdhc2;
  30                 mmc2 = &usdhc1;
  31                 rtc0 = &pcf85063;
  32                 rtc1 = &snvs_rtc;
  33                 spi0 = &flexspi;
  34                 spi1 = &ecspi1;
  35                 spi2 = &ecspi2;
  36                 spi3 = &ecspi3;
  37         };
  38
  39         backlight_lvds: backlight {
  40                 compatible = "pwm-backlight";
  41                 pinctrl-names = "default";
  42                 pinctrl-0 = <&pinctrl_backlight>;
  43                 pwms = <&pwm2 0 5000000 0>;
  44                 brightness-levels = <0 4 8 16 32 64 128 255>;
  45                 default-brightness-level = <7>;
  46                 power-supply = <&reg_vcc_12v0>;
  47                 enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
  48                 status = "disabled";
  49         };
  50
  51         gpio-keys {
  52                 compatible = "gpio-keys";
  53                 pinctrl-names = "default";
  54                 pinctrl-0 = <&pinctrl_gpiobutton>;
  55                 autorepeat;
  56
  57                 switch-1 {
  58                         label = "S12";
  59                         linux,code = <BTN_0>;
  60                         gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
  61                 };
  62
  63                 switch-2 {
  64                         label = "S13";
  65                         linux,code = <BTN_1>;
  66                         gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
  67                 };
  68         };
  69
  70         gpio-leds {
  71                 compatible = "gpio-leds";
  72                 pinctrl-names = "default";
  73                 pinctrl-0 = <&pinctrl_gpioled>;
  74
  75                 led-0 {
  76                         color = <LED_COLOR_ID_GREEN>;
  77                         function = LED_FUNCTION_STATUS;
  78                         function-enumerator = <0>;
  79                         gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
  80                         linux,default-trigger = "default-on";
  81                 };
  82
  83                 led-1 {
  84                         color = <LED_COLOR_ID_GREEN>;
  85                         function = LED_FUNCTION_HEARTBEAT;
  86                         gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
  87                         linux,default-trigger = "heartbeat";
  88                 };
  89
  90                 led-2 {
  91                         color = <LED_COLOR_ID_YELLOW>;
  92                         function = LED_FUNCTION_STATUS;
  93                         function-enumerator = <1>;
  94                         gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
  95                 };
  96         };
  97
  98         display: display {
  99                 /*
 100                  * Display is not fixed, so compatible has to be added from
 101                  * DT overlay
 102                  */
 103                 pinctrl-names = "default";
 104                 pinctrl-0 = <&pinctrl_lvdsdisplay>;
 105                 power-supply = <&reg_vcc_3v3>;
 106                 enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 107                 backlight = <&backlight_lvds>;
 108                 status = "disabled";
 109         };
 110
 111         reg_usdhc2_vmmc: regulator-usdhc2 {
 112                 compatible = "regulator-fixed";
 113                 pinctrl-names = "default";
 114                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
 115                 regulator-name = "VSD_3V3";
 116                 regulator-min-microvolt = <3300000>;
 117                 regulator-max-microvolt = <3300000>;
 118                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
 119                 enable-active-high;
 120                 startup-delay-us = <100>;
 121                 off-on-delay-us = <12000>;
 122         };
 123
 124         reg_vcc_12v0: regulator-12v0 {
 125                 compatible = "regulator-fixed";
 126                 pinctrl-names = "default";
 127                 pinctrl-0 = <&pinctrl_reg12v0>;
 128                 regulator-name = "VCC_12V0";
 129                 regulator-min-microvolt = <12000000>;
 130                 regulator-max-microvolt = <12000000>;
 131                 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
 132                 enable-active-high;
 133         };
 134
 135         reg_vcc_3v3: regulator-3v3 {
 136                 compatible = "regulator-fixed";
 137                 regulator-name = "VCC_3V3";
 138                 regulator-min-microvolt = <3300000>;
 139                 regulator-max-microvolt = <3300000>;
 140         };
 141
 142         reg_vcc_5v0: regulator-5v0 {
 143                 compatible = "regulator-fixed";
 144                 regulator-name = "VCC_5V0";
 145                 regulator-min-microvolt = <5000000>;
 146                 regulator-max-microvolt = <5000000>;
 147         };
 148
 149         reserved-memory {
 150                 #address-cells = <2>;
 151                 #size-cells = <2>;
 152                 ranges;
 153
 154                 ocram: ocram@900000 {
 155                         no-map;
 156                         reg = <0 0x900000 0 0x70000>;
 157                 };
 158
 159                 /* global autoconfigured region for contiguous allocations */
 160                 linux,cma {
 161                         compatible = "shared-dma-pool";
 162                         reusable;
 163                         size = <0 0x38000000>;
 164                         alloc-ranges = <0 0x40000000 0 0xB0000000>;
 165                         linux,cma-default;
 166                 };
 167         };
 168 };
 169
 170 &ecspi1 {
 171         pinctrl-names = "default";
 172         pinctrl-0 = <&pinctrl_ecspi1>;
 173         cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 174         status = "okay";
 175 };
 176
 177 &ecspi2 {
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_ecspi2>;
 180         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 181         status = "okay";
 182 };
 183
 184 &ecspi3 {
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&pinctrl_ecspi3>;
 187         cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
 188         status = "okay";
 189
 190         adc: adc@0 {
 191                 reg = <0>;
 192                 compatible = "microchip,mcp3202";
 193                 /* 100 ksps * 18 */
 194                 spi-max-frequency = <1800000>;
 195                 vref-supply = <&reg_vcc_3v3>;
 196                 #io-channel-cells = <1>;
 197         };
 198 };
 199
 200 &eqos {
 201         pinctrl-names = "default";
 202         pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>;
 203         phy-mode = "rgmii-id";
 204         phy-handle = <&ethphy3>;
 205         status = "okay";
 206
 207         mdio {
 208                 compatible = "snps,dwmac-mdio";
 209                 #address-cells = <1>;
 210                 #size-cells = <0>;
 211
 212                 ethphy3: ethernet-phy@3 {
 213                         compatible = "ethernet-phy-ieee802.3-c22";
 214                         reg = <3>;
 215                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
 216                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
 217                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 218                         ti,dp83867-rxctrl-strap-quirk;
 219                         ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
 220                         reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
 221                         reset-assert-us = <500000>;
 222                         reset-deassert-us = <50000>;
 223                         enet-phy-lane-no-swap;
 224                         interrupt-parent = <&gpio4>;
 225                         interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
 226                 };
 227         };
 228 };
 229
 230 &fec {
 231         pinctrl-names = "default";
 232         pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>;
 233         phy-mode = "rgmii-id";
 234         phy-handle = <&ethphy0>;
 235         fsl,magic-packet;
 236         status = "okay";
 237
 238         mdio {
 239                 #address-cells = <1>;
 240                 #size-cells = <0>;
 241
 242                 ethphy0: ethernet-phy@0 {
 243                         compatible = "ethernet-phy-ieee802.3-c22";
 244                         reg = <0>;
 245                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
 246                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
 247                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 248                         ti,dp83867-rxctrl-strap-quirk;
 249                         ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
 250                         reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
 251                         reset-assert-us = <500000>;
 252                         reset-deassert-us = <50000>;
 253                         enet-phy-lane-no-swap;
 254                         interrupt-parent = <&gpio4>;
 255                         interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
 256                 };
 257         };
 258 };
 259
 260 &flexcan1 {
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&pinctrl_flexcan1>;
 263         xceiver-supply = <&reg_vcc_3v3>;
 264         status = "okay";
 265 };
 266
 267 &flexcan2 {
 268         pinctrl-names = "default";
 269         pinctrl-0 = <&pinctrl_flexcan2>;
 270         xceiver-supply = <&reg_vcc_3v3>;
 271         status = "okay";
 272 };
 273
 274 &gpio1 {
 275         pinctrl-names = "default";
 276         pinctrl-0 = <&pinctrl_gpio1>;
 277
 278         gpio-line-names = "GPO1", "GPO0", "", "GPO3",
 279                           "", "", "GPO2", "GPI0",
 280                           "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#",
 281                           "OTG_PWR", "", "GPI2", "GPI3",
 282                           "", "", "", "",
 283                           "", "", "", "",
 284                           "", "", "", "",
 285                           "", "", "", "";
 286 };
 287
 288 &gpio2 {
 289         pinctrl-names = "default";
 290         pinctrl-0 = <&pinctrl_hoggpio2>;
 291
 292         gpio-line-names = "", "", "", "",
 293                           "", "", "VCC12V_EN", "PERST#",
 294                           "", "", "CLKREQ#", "PEWAKE#",
 295                           "USDHC2_CD", "", "", "",
 296                           "", "", "", "V_SD3V3_EN",
 297                           "", "", "", "",
 298                           "", "", "", "",
 299                           "", "", "", "";
 300
 301         perst-hog {
 302                 gpio-hog;
 303                 gpios = <7 0>;
 304                 output-high;
 305                 line-name = "PERST#";
 306         };
 307
 308         clkreq-hog {
 309                 gpio-hog;
 310                 gpios = <10 0>;
 311                 input;
 312                 line-name = "CLKREQ#";
 313         };
 314
 315         pewake-hog {
 316                 gpio-hog;
 317                 gpios = <11 0>;
 318                 input;
 319                 line-name = "PEWAKE#";
 320         };
 321 };
 322
 323 &gpio3 {
 324         gpio-line-names = "", "", "", "",
 325                           "", "", "", "",
 326                           "", "", "", "",
 327                           "", "", "LVDS0_RESET#", "",
 328                           "", "", "", "LVDS0_BLT_EN",
 329                           "LVDS0_PWR_EN", "", "", "",
 330                           "", "", "", "",
 331                           "", "", "", "";
 332 };
 333
 334 &gpio4 {
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&pinctrl_gpio4>;
 337
 338         gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#",
 339                           "", "", "", "",
 340                           "", "", "", "",
 341                           "", "", "", "",
 342                           "", "", "DP_IRQ", "DSI_EN",
 343                           "HDMI_OC#", "TEMP_EVENT#", "PCIE_CLK_OE#", "",
 344                           "", "", "", "FAN_PWR",
 345                           "RTC_EVENT#", "CODEC_RST#", "", "";
 346 };
 347
 348 &gpio5 {
 349         gpio-line-names = "", "", "", "LED2",
 350                           "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC",
 351                           "CSI0_TRIGGER", "CSI0_ENABLE", "", "",
 352                           "", "ECSPI2_SS0", "", "",
 353                           "", "", "", "",
 354                           "", "", "", "",
 355                           "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B",
 356                           "", "", "", "";
 357 };
 358
 359 &i2c2 {
 360         clock-frequency = <384000>;
 361         pinctrl-names = "default", "gpio";
 362         pinctrl-0 = <&pinctrl_i2c2>;
 363         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 364         scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 365         sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 366         status = "okay";
 367
 368         /* NXP SE97BTP with temperature sensor + eeprom */
 369         se97_1c: temperature-sensor-eeprom@1c {
 370                 compatible = "nxp,se97", "jedec,jc-42.4-temp";
 371                 reg = <0x1c>;
 372         };
 373
 374         at24c02_54: eeprom@54 {
 375                 compatible = "nxp,se97b", "atmel,24c02";
 376                 reg = <0x54>;
 377                 pagesize = <16>;
 378                 vcc-supply = <&reg_vcc_3v3>;
 379         };
 380 };
 381
 382 &i2c4 {
 383         clock-frequency = <384000>;
 384         pinctrl-names = "default", "gpio";
 385         pinctrl-0 = <&pinctrl_i2c4>;
 386         pinctrl-1 = <&pinctrl_i2c4_gpio>;
 387         scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 388         sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 389         status = "okay";
 390 };
 391
 392 &i2c6 {
 393         clock-frequency = <384000>;
 394         pinctrl-names = "default", "gpio";
 395         pinctrl-0 = <&pinctrl_i2c6>;
 396         pinctrl-1 = <&pinctrl_i2c6_gpio>;
 397         scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 398         sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 399         status = "okay";
 400 };
 401
 402 &pcf85063 {
 403         /* RTC_EVENT# is connected on MBa8MPxL */
 404         pinctrl-names = "default";
 405         pinctrl-0 = <&pinctrl_pcf85063>;
 406         interrupt-parent = <&gpio4>;
 407         interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
 408 };
 409
 410 &pwm2 {
 411         pinctrl-names = "default";
 412         pinctrl-0 = <&pinctrl_pwm2>;
 413         status = "disabled";
 414 };
 415
 416 &pwm3 {
 417         pinctrl-names = "default";
 418         pinctrl-0 = <&pinctrl_pwm3>;
 419         status = "okay";
 420 };
 421
 422 &snvs_pwrkey {
 423         status = "okay";
 424 };
 425
 426 &uart1 {
 427         pinctrl-names = "default";
 428         pinctrl-0 = <&pinctrl_uart1>;
 429         assigned-clocks = <&clk IMX8MP_CLK_UART1>;
 430         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
 431         status = "okay";
 432 };
 433
 434 &uart2 {
 435         pinctrl-names = "default";
 436         pinctrl-0 = <&pinctrl_uart2>;
 437         assigned-clocks = <&clk IMX8MP_CLK_UART2>;
 438         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
 439         status = "okay";
 440 };
 441
 442 &uart3 {
 443         pinctrl-names = "default";
 444         pinctrl-0 = <&pinctrl_uart3>;
 445         assigned-clocks = <&clk IMX8MP_CLK_UART3>;
 446         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
 447         status = "okay";
 448 };
 449
 450 &uart4 {
 451         /* console */
 452         pinctrl-names = "default";
 453         pinctrl-0 = <&pinctrl_uart4>;
 454         status = "okay";
 455 };
 456
 457 &usb3_0 {
 458         pinctrl-names = "default";
 459         pinctrl-0 = <&pinctrl_usb0>;
 460         fsl,over-current-active-low;
 461         status = "okay";
 462 };
 463
 464 &usb3_phy0 {
 465         vbus-supply = <&reg_vcc_5v0>;
 466         status = "okay";
 467 };
 468
 469 &usb_dwc3_0 {
 470         /* dual role is implemented, but not a full featured OTG */
 471         hnp-disable;
 472         srp-disable;
 473         adp-disable;
 474         dr_mode = "otg";
 475         usb-role-switch;
 476         role-switch-default-mode = "peripheral";
 477         status = "okay";
 478
 479         connector {
 480                 compatible = "gpio-usb-b-connector", "usb-b-connector";
 481                 type = "micro";
 482                 label = "X29";
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&pinctrl_usbcon0>;
 485                 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
 486         };
 487 };
 488
 489 &usdhc2 {
 490         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 491         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 492         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 493         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 494         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 495         vmmc-supply = <&reg_usdhc2_vmmc>;
 496         no-mmc;
 497         no-sdio;
 498         disable-wp;
 499         bus-width = <4>;
 500         status = "okay";
 501 };
 502
 503 &iomuxc {
 504         pinctrl_backlight: backlightgrp {
 505                 fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19          0x14>;
 506         };
 507
 508         pinctrl_flexcan1: flexcan1grp {
 509                 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX             0x150>,
 510                            <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX             0x150>;
 511         };
 512
 513         pinctrl_flexcan2: flexcan2grp {
 514                 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX             0x150>,
 515                            <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX             0x150>;
 516         };
 517
 518         /* only on X57, primary used as CSI0 control signals */
 519         pinctrl_ecspi1: ecspi1grp {
 520                 fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO       0x1c0>,
 521                            <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI       0x1c0>,
 522                            <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK       0x1c0>,
 523                            <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09         0x1c0>;
 524         };
 525
 526         /* on X63 and optionally on X57, can also be used as CSI1 control signals */
 527         pinctrl_ecspi2: ecspi2grp {
 528                 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO       0x1c0>,
 529                            <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI       0x1c0>,
 530                            <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK       0x1c0>,
 531                            <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13         0x1c0>;
 532         };
 533
 534         pinctrl_ecspi3: ecspi3grp {
 535                 fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI         0x1c0>,
 536                            <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK         0x1c0>,
 537                            <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO         0x1c0>,
 538                            <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25          0x1c0>;
 539         };
 540
 541         pinctrl_eqos: eqosgrp {
 542                 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                         0x40000044>,
 543                            <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                       0x40000044>,
 544                            <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0                   0x90>,
 545                            <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1                   0x90>,
 546                            <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2                   0x90>,
 547                            <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3                   0x90>,
 548                            <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK   0x90>,
 549                            <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL             0x90>,
 550                            <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0                   0x12>,
 551                            <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1                   0x12>,
 552                            <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2                   0x12>,
 553                            <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3                   0x12>,
 554                            <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL             0x12>,
 555                            <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK   0x14>;
 556         };
 557
 558         pinctrl_eqos_event: eqosevtgrp {
 559                 fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT            0x100>,
 560                            <MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN             0x1c0>;
 561         };
 562
 563         pinctrl_eqos_phy: eqosphygrp {
 564                 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02                          0x100>,
 565                            <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03                          0x1c0>;
 566         };
 567
 568         pinctrl_fec: fecgrp {
 569                 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC           0x40000044>,
 570                            <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO          0x40000044>,
 571                            <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0     0x90>,
 572                            <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1     0x90>,
 573                            <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2     0x90>,
 574                            <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3     0x90>,
 575                            <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC      0x90>,
 576                            <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL  0x90>,
 577                            <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0     0x12>,
 578                            <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1     0x12>,
 579                            <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2     0x12>,
 580                            <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3     0x12>,
 581                            <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL  0x12>,
 582                            <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC     0x14>;
 583         };
 584
 585         pinctrl_fec_event: fecevtgrp {
 586                 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN        0x100>,
 587                            <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT        0x1c0>;
 588         };
 589
 590         pinctrl_fec_phy: fecphygrp {
 591                 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00          0x100>,
 592                            <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01           0x1c0>;
 593         };
 594
 595         pinctrl_fec_phyalt: fecphyaltgrp {
 596                 fsl,pins = <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24          0x180>,
 597                            <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25           0x180>;
 598         };
 599
 600         pinctrl_gpiobutton: gpiobuttongrp {
 601                 fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26          0x10>,
 602                            <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27          0x10>;
 603         };
 604
 605         pinctrl_gpioled: gpioledgrp {
 606                 fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05      0x14>,
 607                            <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04           0x14>,
 608                            <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03           0x14>;
 609         };
 610
 611         pinctrl_gpio1: gpio1grp {
 612                 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00         0x10>,
 613                            <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01         0x10>,
 614                            <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03         0x10>,
 615                            <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06         0x10>,
 616                            <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07         0x80>,
 617                            <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09         0x80>,
 618                            <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14         0x80>,
 619                            <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15         0x80>;
 620         };
 621
 622         pinctrl_gpio4: gpio4grp {
 623                 fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20          0x180>,
 624                            <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22           0x180>;
 625         };
 626
 627         pinctrl_hdmi: hdmigrp {
 628                 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>,
 629                            <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>,
 630                            <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD     0x40000010>,
 631                            <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC     0x40000010>;
 632         };
 633
 634         pinctrl_hoggpio2: hoggpio2grp {
 635                 fsl,pins = <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07          0x140>,
 636                            <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10        0x140>,
 637                            <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11         0x140>;
 638         };
 639
 640         pinctrl_i2c2: i2c2grp {
 641                 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL             0x400001e2>,
 642                            <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA             0x400001e2>;
 643         };
 644
 645         pinctrl_i2c2_gpio: i2c2-gpiogrp {
 646                 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16           0x400001e2>,
 647                            <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17           0x400001e2>;
 648         };
 649
 650         pinctrl_i2c4: i2c4grp {
 651                 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL             0x400001e2>,
 652                            <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA             0x400001e2>;
 653         };
 654
 655         pinctrl_i2c4_gpio: i2c4-gpiogrp {
 656                 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20           0x400001e2>,
 657                            <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21           0x400001e2>;
 658         };
 659
 660         pinctrl_i2c6: i2c6grp {
 661                 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL            0x400001e2>,
 662                            <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA            0x400001e2>;
 663         };
 664
 665         pinctrl_i2c6_gpio: i2c6-gpiogrp {
 666                 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02          0x400001e2>,
 667                            <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03          0x400001e2>;
 668         };
 669
 670         pinctrl_lvdsdisplay: lvdsdisplaygrp {
 671                 fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20           0x10>; /* Power enable */
 672         };
 673
 674         pinctrl_pcf85063: pcf85063grp {
 675                 fsl,pins = <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28          0x80>;
 676         };
 677
 678         /* LVDS Backlight */
 679         pinctrl_pwm2: pwm2grp {
 680                 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT            0x14>;
 681         };
 682
 683         /* FAN */
 684         pinctrl_pwm3: pwm3grp {
 685                 fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT             0x14>;
 686         };
 687
 688         pinctrl_reg12v0: reg12v0grp {
 689                 fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06          0x140>; /* VCC12V enable */
 690         };
 691
 692         /* X61 */
 693         pinctrl_uart1: uart1grp {
 694                 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX          0x140>,
 695                            <MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX          0x140>;
 696         };
 697
 698         /* X61 */
 699         pinctrl_uart2: uart2grp {
 700                 fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX        0x140>,
 701                            <MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX        0x140>;
 702         };
 703
 704         pinctrl_uart3: uart3grp {
 705                 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX        0x140>,
 706                            <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX        0x140>;
 707         };
 708
 709         pinctrl_uart4: uart4grp {
 710                 fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX        0x140>,
 711                            <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX        0x140>;
 712         };
 713
 714         pinctrl_usb0: usb0grp {
 715                 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC        0x1c0>,
 716                            <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR       0x1c0>;
 717         };
 718
 719         pinctrl_usbcon0: usb0congrp {
 720                 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10         0x1c0>;
 721         };
 722
 723         pinctrl_usdhc2: usdhc2grp {
 724                 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK            0x192>,
 725                            <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD            0x1d2>,
 726                            <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0        0x1d2>,
 727                            <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1        0x1d2>,
 728                            <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2        0x1d2>,
 729                            <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d2>,
 730                            <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT     0xc0>;
 731         };
 732
 733         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 734                 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK            0x194>,
 735                            <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD            0x1d4>,
 736                            <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0        0x1d4>,
 737                            <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1        0x1d4>,
 738                            <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2        0x1d4>,
 739                            <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d4>,
 740                            <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT     0xc0>;
 741         };
 742
 743         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 744                 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK            0x194>,
 745                            <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD            0x1d4>,
 746                            <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0        0x1d4>,
 747                            <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1        0x1d4>,
 748                            <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2        0x1d4>,
 749                            <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d4>,
 750                            <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT     0xc0>;
 751         };
 752
 753         pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
 754                 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12           0x1c0>;
 755         };
 756 };