1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
7 #include <dt-bindings/net/ti-dp83867.h>
11 model = "PHYTEC phyCORE-i.MX8MP";
12 compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
20 device_type = "memory";
21 reg = <0x0 0x40000000 0 0x80000000>;
26 cpu-supply = <&buck2>;
30 cpu-supply = <&buck2>;
34 cpu-supply = <&buck2>;
38 cpu-supply = <&buck2>;
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_fec>;
45 phy-mode = "rgmii-id";
46 phy-handle = <ðphy1>;
54 ethphy1: ethernet-phy@0 {
55 compatible = "ethernet-phy-ieee802.3-c22";
57 interrupt-parent = <&gpio1>;
58 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
59 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
60 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
61 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
62 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
63 ti,min-output-impedance;
64 enet-phy-lane-no-swap;
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_flexspi0>;
75 compatible = "jedec,spi-nor";
77 spi-max-frequency = <80000000>;
78 spi-tx-bus-width = <1>;
79 spi-rx-bus-width = <4>;
84 clock-frequency = <400000>;
85 pinctrl-names = "default", "gpio";
86 pinctrl-0 = <&pinctrl_i2c1>;
87 pinctrl-1 = <&pinctrl_i2c1_gpio>;
88 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
89 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
94 compatible = "nxp,pca9450c";
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_pmic>;
97 interrupt-parent = <&gpio4>;
98 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
102 regulator-min-microvolt = <600000>;
103 regulator-max-microvolt = <2187500>;
106 regulator-ramp-delay = <3125>;
110 regulator-min-microvolt = <600000>;
111 regulator-max-microvolt = <2187500>;
114 regulator-ramp-delay = <3125>;
115 nxp,dvs-run-voltage = <950000>;
116 nxp,dvs-standby-voltage = <850000>;
120 regulator-min-microvolt = <600000>;
121 regulator-max-microvolt = <3400000>;
127 regulator-min-microvolt = <600000>;
128 regulator-max-microvolt = <3400000>;
134 regulator-min-microvolt = <600000>;
135 regulator-max-microvolt = <3400000>;
141 regulator-min-microvolt = <1600000>;
142 regulator-max-microvolt = <3300000>;
148 regulator-min-microvolt = <800000>;
149 regulator-max-microvolt = <1150000>;
155 regulator-min-microvolt = <800000>;
156 regulator-max-microvolt = <3300000>;
162 regulator-min-microvolt = <800000>;
163 regulator-max-microvolt = <3300000>;
167 regulator-min-microvolt = <1800000>;
168 regulator-max-microvolt = <3300000>;
176 compatible = "atmel,24c32";
182 compatible = "microcrystal,rv3028";
184 trickle-resistor-ohms = <3000>;
190 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
191 assigned-clock-rates = <400000000>;
192 pinctrl-names = "default", "state_100mhz", "state_200mhz";
193 pinctrl-0 = <&pinctrl_usdhc3>;
194 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
195 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_wdog>;
204 fsl,ext-reset-output;
209 pinctrl_fec: fecgrp {
211 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
212 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
213 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
214 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
215 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
216 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
217 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
218 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
219 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12
220 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12
221 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14
222 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14
223 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14
224 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14
225 MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11
229 pinctrl_flexspi0: flexspi0grp {
231 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
232 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
233 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
234 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
235 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
236 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
240 pinctrl_i2c1: i2c1grp {
242 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
243 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
247 pinctrl_i2c1_gpio: i2c1gpiogrp {
249 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3
250 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3
254 pinctrl_pmic: pmicirqgrp {
256 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141
260 pinctrl_usdhc3: usdhc3grp {
262 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
263 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
264 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
265 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
266 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
267 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
268 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
269 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
270 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
271 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
272 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
276 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
278 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
279 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
280 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
281 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
282 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
283 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
284 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
285 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
286 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
287 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
288 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
292 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
294 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
295 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
296 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2
297 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2
298 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2
299 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2
300 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2
301 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
302 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
303 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
304 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
308 pinctrl_wdog: wdoggrp {
310 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6