arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2020 PHYTEC Messtechnik GmbH
   4  * Author: Teresa Remmet <t.remmet@phytec.de>
   5  */
   6
   7 #include <dt-bindings/net/ti-dp83867.h>
   8 #include "imx8mp.dtsi"
   9
  10 / {
  11         model = "PHYTEC phyCORE-i.MX8MP";
  12         compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
  13
  14         aliases {
  15                 rtc0 = &rv3028;
  16                 rtc1 = &snvs_rtc;
  17         };
  18
  19         memory@40000000 {
  20                 device_type = "memory";
  21                 reg = <0x0 0x40000000 0 0x80000000>;
  22         };
  23 };
  24
  25 &A53_0 {
  26         cpu-supply = <&buck2>;
  27 };
  28
  29 &A53_1 {
  30         cpu-supply = <&buck2>;
  31 };
  32
  33 &A53_2 {
  34         cpu-supply = <&buck2>;
  35 };
  36
  37 &A53_3 {
  38         cpu-supply = <&buck2>;
  39 };
  40
  41 /* ethernet 1 */
  42 &fec {
  43         pinctrl-names = "default";
  44         pinctrl-0 = <&pinctrl_fec>;
  45         phy-handle = <&ethphy1>;
  46         phy-mode = "rgmii-id";
  47         fsl,magic-packet;
  48         status = "okay";
  49
  50         mdio {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53
  54                 ethphy1: ethernet-phy@0 {
  55                         compatible = "ethernet-phy-ieee802.3-c22";
  56                         reg = <0>;
  57                         enet-phy-lane-no-swap;
  58                         ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
  59                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  60                         ti,min-output-impedance;
  61                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  62                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  63                 };
  64         };
  65 };
  66
  67 &flexspi {
  68         pinctrl-names = "default";
  69         pinctrl-0 = <&pinctrl_flexspi0>;
  70         status = "okay";
  71
  72         som_flash: flash@0 {
  73                 compatible = "jedec,spi-nor";
  74                 reg = <0>;
  75                 spi-max-frequency = <80000000>;
  76                 spi-rx-bus-width = <4>;
  77                 spi-tx-bus-width = <1>;
  78         };
  79 };
  80
  81 &i2c1 {
  82         clock-frequency = <400000>;
  83         pinctrl-names = "default", "gpio";
  84         pinctrl-0 = <&pinctrl_i2c1>;
  85         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  86         scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  87         sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  88         status = "okay";
  89
  90         pmic: pmic@25 {
  91                 compatible = "nxp,pca9450c";
  92                 reg = <0x25>;
  93                 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
  94                 interrupt-parent = <&gpio4>;
  95                 pinctrl-names = "default";
  96                 pinctrl-0 = <&pinctrl_pmic>;
  97
  98                 regulators {
  99                         buck1: BUCK1 {
 100                                 regulator-always-on;
 101                                 regulator-boot-on;
 102                                 regulator-max-microvolt = <1000000>;
 103                                 regulator-min-microvolt = <805000>;
 104                                 regulator-name = "VDD_SOC (BUCK1)";
 105                                 regulator-ramp-delay = <3125>;
 106                         };
 107
 108                         buck2: BUCK2 {
 109                                 nxp,dvs-run-voltage = <950000>;
 110                                 nxp,dvs-standby-voltage = <850000>;
 111                                 regulator-always-on;
 112                                 regulator-boot-on;
 113                                 regulator-max-microvolt = <1050000>;
 114                                 regulator-min-microvolt = <805000>;
 115                                 regulator-name = "VDD_ARM (BUCK2)";
 116                                 regulator-ramp-delay = <3125>;
 117                         };
 118
 119                         buck4: BUCK4 {
 120                                 regulator-always-on;
 121                                 regulator-boot-on;
 122                                 regulator-max-microvolt = <3300000>;
 123                                 regulator-min-microvolt = <3300000>;
 124                                 regulator-name = "VDD_3V3 (BUCK4)";
 125                         };
 126
 127                         buck5: BUCK5 {
 128                                 regulator-always-on;
 129                                 regulator-boot-on;
 130                                 regulator-max-microvolt = <1800000>;
 131                                 regulator-min-microvolt = <1800000>;
 132                                 regulator-name = "VDD_1V8 (BUCK5)";
 133                         };
 134
 135                         buck6: BUCK6 {
 136                                 regulator-always-on;
 137                                 regulator-boot-on;
 138                                 regulator-max-microvolt = <1155000>;
 139                                 regulator-min-microvolt = <1045000>;
 140                                 regulator-name = "NVCC_DRAM_1V1 (BUCK6)";
 141                         };
 142
 143                         ldo1: LDO1 {
 144                                 regulator-always-on;
 145                                 regulator-boot-on;
 146                                 regulator-max-microvolt = <1950000>;
 147                                 regulator-min-microvolt = <1710000>;
 148                                 regulator-name = "NVCC_SNVS_1V8 (LDO1)";
 149                         };
 150
 151                         ldo3: LDO3 {
 152                                 regulator-always-on;
 153                                 regulator-boot-on;
 154                                 regulator-max-microvolt = <1800000>;
 155                                 regulator-min-microvolt = <1800000>;
 156                                 regulator-name = "VDDA_1V8 (LDO3)";
 157                         };
 158
 159                         ldo5: LDO5 {
 160                                 regulator-always-on;
 161                                 regulator-boot-on;
 162                                 regulator-max-microvolt = <3300000>;
 163                                 regulator-min-microvolt = <1800000>;
 164                                 regulator-name = "NVCC_SD2 (LDO5)";
 165                         };
 166                 };
 167         };
 168
 169         eeprom@51 {
 170                 compatible = "atmel,24c32";
 171                 reg = <0x51>;
 172                 pagesize = <32>;
 173         };
 174
 175         rv3028: rtc@52 {
 176                 compatible = "microcrystal,rv3028";
 177                 reg = <0x52>;
 178                 trickle-resistor-ohms = <3000>;
 179         };
 180 };
 181
 182 /* eMMC */
 183 &usdhc3 {
 184         assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
 185         assigned-clock-rates = <400000000>;
 186         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 187         pinctrl-0 = <&pinctrl_usdhc3>;
 188         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 189         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 190         bus-width = <8>;
 191         non-removable;
 192         status = "okay";
 193 };
 194
 195 &wdog1 {
 196         pinctrl-names = "default";
 197         pinctrl-0 = <&pinctrl_wdog>;
 198         fsl,ext-reset-output;
 199         status = "okay";
 200 };
 201
 202 &gpio1 {
 203         gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
 204                 "", "", "", "", "", "",
 205                 "", "", "", "", "", "X_nETHPHY_INT";
 206 };
 207
 208 &gpio4 {
 209         gpio-line-names = "", "", "", "",
 210                 "", "", "", "", "", "",
 211                 "", "", "", "", "", "",
 212                 "", "", "X_PMIC_IRQ_B";
 213 };
 214
 215 &iomuxc {
 216         pinctrl_fec: fecgrp {
 217                 fsl,pins = <
 218                         MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x2
 219                         MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x2
 220                         MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x90
 221                         MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x90
 222                         MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2         0x90
 223                         MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3         0x90
 224                         MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC          0x90
 225                         MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x12
 226                         MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x12
 227                         MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2         0x14
 228                         MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3         0x14
 229                         MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x14
 230                         MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC         0x14
 231                         MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x90
 232                 >;
 233         };
 234
 235         pinctrl_flexspi0: flexspi0grp {
 236                 fsl,pins = <
 237                         MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK           0x1c2
 238                         MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B        0x82
 239                         MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00      0x82
 240                         MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01      0x82
 241                         MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02      0x82
 242                         MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03      0x82
 243                 >;
 244         };
 245
 246         pinctrl_i2c1: i2c1grp {
 247                 fsl,pins = <
 248                         MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA         0x400001c2
 249                         MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL         0x400001c2
 250                 >;
 251         };
 252
 253         pinctrl_i2c1_gpio: i2c1gpiogrp {
 254                 fsl,pins = <
 255                         MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14       0x1e2
 256                         MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15       0x1e2
 257                 >;
 258         };
 259
 260         pinctrl_pmic: pmicirqgrp {
 261                 fsl,pins = <
 262                         MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18      0x140
 263                 >;
 264         };
 265
 266         pinctrl_usdhc3: usdhc3grp {
 267                 fsl,pins = <
 268                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x190
 269                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d0
 270                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d0
 271                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d0
 272                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d0
 273                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d0
 274                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d0
 275                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d0
 276                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d0
 277                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x190
 278                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d0
 279                 >;
 280         };
 281
 282         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 283                 fsl,pins = <
 284                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x194
 285                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d4
 286                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d4
 287                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d4
 288                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d4
 289                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d4
 290                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d4
 291                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d4
 292                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d4
 293                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x194
 294                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d4
 295                 >;
 296         };
 297
 298         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 299                 fsl,pins = <
 300                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x196
 301                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d2
 302                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d2
 303                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d2
 304                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d2
 305                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d2
 306                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d2
 307                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d2
 308                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d2
 309                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x196
 310                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d6
 311                 >;
 312         };
 313
 314         pinctrl_wdog: wdoggrp {
 315                 fsl,pins = <
 316                         MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B   0xe6
 317                 >;
 318         };
 319 };