1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
9 #include <dt-bindings/leds/leds-pca9532.h>
10 #include <dt-bindings/pwm/pwm.h>
11 #include "imx8mp-phycore-som.dtsi"
14 model = "PHYTEC phyBOARD-Pollux i.MX8MP";
15 compatible = "phytec,imx8mp-phyboard-pollux-rdk",
16 "phytec,imx8mp-phycore-som", "fsl,imx8mp";
22 reg_can1_stby: regulator-can1-stby {
23 compatible = "regulator-fixed";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_flexcan1_reg>;
26 gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
27 regulator-max-microvolt = <3300000>;
28 regulator-min-microvolt = <3300000>;
29 regulator-name = "can1-stby";
32 reg_can2_stby: regulator-can2-stby {
33 compatible = "regulator-fixed";
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_flexcan2_reg>;
36 gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
37 regulator-max-microvolt = <3300000>;
38 regulator-min-microvolt = <3300000>;
39 regulator-name = "can2-stby";
42 reg_usb1_vbus: regulator-usb1-vbus {
43 compatible = "regulator-fixed";
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_usb1_vbus>;
46 gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
47 regulator-max-microvolt = <5000000>;
48 regulator-min-microvolt = <5000000>;
49 regulator-name = "usb1_host_vbus";
52 reg_usdhc2_vmmc: regulator-usdhc2 {
53 compatible = "regulator-fixed";
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
56 regulator-name = "VSD_3V3";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
61 startup-delay-us = <100>;
62 off-on-delay-us = <12000>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_eqos>;
69 phy-mode = "rgmii-id";
70 phy-handle = <ðphy0>;
74 compatible = "snps,dwmac-mdio";
78 ethphy0: ethernet-phy@1 {
79 compatible = "ethernet-phy-ieee802.3-c22";
81 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
82 ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
83 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
84 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
85 enet-phy-lane-no-swap;
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_flexcan1>;
94 xceiver-supply = <®_can1_stby>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_flexcan2>;
101 xceiver-supply = <®_can2_stby>;
106 clock-frequency = <400000>;
107 pinctrl-names = "default", "gpio";
108 pinctrl-0 = <&pinctrl_i2c2>;
109 pinctrl-1 = <&pinctrl_i2c2_gpio>;
110 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
111 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
115 compatible = "atmel,24c02";
121 compatible = "nxp,pca9533";
125 type = <PCA9532_TYPE_LED>;
129 type = <PCA9532_TYPE_LED>;
133 type = <PCA9532_TYPE_LED>;
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_uart1>;
149 /* USB1 Host mode Type-A */
151 vbus-supply = <®_usb1_vbus>;
164 /* USB2 4-port USB3.0 HUB */
170 fsl,permanently-attached;
171 fsl,disable-port-power-control;
182 assigned-clocks = <&clk IMX8MP_CLK_UART2>;
183 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_uart2>;
192 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
193 assigned-clock-rates = <200000000>;
194 pinctrl-names = "default", "state_100mhz", "state_200mhz";
195 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
196 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
197 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
198 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
199 vmmc-supply = <®_usdhc2_vmmc>;
205 gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
206 "PMIC_SD_VSEL", "", "", "", "", "",
207 "", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT";
211 gpio-line-names = "", "", "", "",
212 "", "", "", "", "", "",
213 "", "", "X_SD2_CD_B", "", "", "",
214 "", "", "", "SD2_RESET_B";
218 gpio-line-names = "", "", "", "",
219 "", "", "", "", "", "",
220 "", "", "", "", "", "",
221 "", "", "", "", "nCAN1_EN", "nCAN2_EN";
225 gpio-line-names = "", "", "", "",
226 "", "", "", "", "", "",
227 "", "", "", "", "", "",
228 "", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN";
232 pinctrl_eqos: eqosgrp {
234 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
235 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
236 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
237 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
238 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
239 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
240 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
241 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
242 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
243 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
244 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
245 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
246 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
247 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
248 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
252 pinctrl_flexcan1: flexcan1grp {
254 MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
255 MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
259 pinctrl_flexcan2: flexcan2grp {
261 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
262 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
266 pinctrl_flexcan1_reg: flexcan1reggrp {
268 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154
272 pinctrl_flexcan2_reg: flexcan2reggrp {
274 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154
278 pinctrl_i2c2: i2c2grp {
280 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
281 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
285 pinctrl_i2c2_gpio: i2c2gpiogrp {
287 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
288 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
292 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
294 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
298 pinctrl_uart1: uart1grp {
300 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
301 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
305 pinctrl_usb1_vbus: usb1vbusgrp {
307 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10
311 pinctrl_uart2: uart2grp {
313 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
314 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
315 MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140
316 MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140
320 pinctrl_usdhc2_pins: usdhc2-gpiogrp {
322 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
326 pinctrl_usdhc2: usdhc2grp {
328 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
329 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
330 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
331 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
332 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
333 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
334 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
338 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
340 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
341 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
342 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
343 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
344 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
345 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
346 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
350 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
352 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
353 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
354 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
355 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
356 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
357 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
358 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0