arch/arm64/boot/dts/freescale/imx8mp-evk.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/phy/phy-imx8-pcie.h>
   9 #include "imx8mp.dtsi"
  10
  11 / {
  12         model = "NXP i.MX8MPlus EVK board";
  13         compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
  14
  15         chosen {
  16                 stdout-path = &uart2;
  17         };
  18
  19         hdmi-connector {
  20                 compatible = "hdmi-connector";
  21                 label = "hdmi";
  22                 type = "a";
  23
  24                 port {
  25                         hdmi_connector_in: endpoint {
  26                                 remote-endpoint = <&adv7533_out>;
  27                         };
  28                 };
  29         };
  30
  31         gpio-leds {
  32                 compatible = "gpio-leds";
  33                 pinctrl-names = "default";
  34                 pinctrl-0 = <&pinctrl_gpio_led>;
  35
  36                 status {
  37                         label = "yellow:status";
  38                         gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  39                         default-state = "on";
  40                 };
  41         };
  42
  43         memory@40000000 {
  44                 device_type = "memory";
  45                 reg = <0x0 0x40000000 0 0xc0000000>,
  46                       <0x1 0x00000000 0 0xc0000000>;
  47         };
  48
  49         pcie0_refclk: pcie0-refclk {
  50                 compatible = "fixed-clock";
  51                 #clock-cells = <0>;
  52                 clock-frequency = <100000000>;
  53         };
  54
  55         reg_audio_pwr: regulator-audio-pwr {
  56                 compatible = "regulator-fixed";
  57                 pinctrl-names = "default";
  58                 pinctrl-0 = <&pinctrl_audio_pwr_reg>;
  59                 regulator-name = "audio-pwr";
  60                 regulator-min-microvolt = <3300000>;
  61                 regulator-max-microvolt = <3300000>;
  62                 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
  63                 enable-active-high;
  64         };
  65
  66         reg_can1_stby: regulator-can1-stby {
  67                 compatible = "regulator-fixed";
  68                 regulator-name = "can1-stby";
  69                 pinctrl-names = "default";
  70                 pinctrl-0 = <&pinctrl_flexcan1_reg>;
  71                 regulator-min-microvolt = <3300000>;
  72                 regulator-max-microvolt = <3300000>;
  73                 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
  74                 enable-active-high;
  75         };
  76
  77         reg_can2_stby: regulator-can2-stby {
  78                 compatible = "regulator-fixed";
  79                 regulator-name = "can2-stby";
  80                 pinctrl-names = "default";
  81                 pinctrl-0 = <&pinctrl_flexcan2_reg>;
  82                 regulator-min-microvolt = <3300000>;
  83                 regulator-max-microvolt = <3300000>;
  84                 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
  85                 enable-active-high;
  86         };
  87
  88         reg_pcie0: regulator-pcie {
  89                 compatible = "regulator-fixed";
  90                 pinctrl-names = "default";
  91                 pinctrl-0 = <&pinctrl_pcie0_reg>;
  92                 regulator-name = "MPCIE_3V3";
  93                 regulator-min-microvolt = <3300000>;
  94                 regulator-max-microvolt = <3300000>;
  95                 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
  96                 enable-active-high;
  97         };
  98
  99         reg_usdhc2_vmmc: regulator-usdhc2 {
 100                 compatible = "regulator-fixed";
 101                 pinctrl-names = "default";
 102                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
 103                 regulator-name = "VSD_3V3";
 104                 regulator-min-microvolt = <3300000>;
 105                 regulator-max-microvolt = <3300000>;
 106                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
 107                 enable-active-high;
 108         };
 109
 110         sound {
 111                 compatible = "simple-audio-card";
 112                 simple-audio-card,name = "wm8960-audio";
 113                 simple-audio-card,format = "i2s";
 114                 simple-audio-card,frame-master = <&cpudai>;
 115                 simple-audio-card,bitclock-master = <&cpudai>;
 116                 simple-audio-card,widgets =
 117                         "Headphone", "Headphone Jack",
 118                         "Speaker", "External Speaker",
 119                         "Microphone", "Mic Jack";
 120                 simple-audio-card,routing =
 121                         "Headphone Jack", "HP_L",
 122                         "Headphone Jack", "HP_R",
 123                         "External Speaker", "SPK_LP",
 124                         "External Speaker", "SPK_LN",
 125                         "External Speaker", "SPK_RP",
 126                         "External Speaker", "SPK_RN",
 127                         "LINPUT1", "Mic Jack",
 128                         "LINPUT3", "Mic Jack",
 129                         "Mic Jack", "MICB";
 130
 131                 cpudai: simple-audio-card,cpu {
 132                         sound-dai = <&sai3>;
 133                 };
 134
 135                 simple-audio-card,codec {
 136                         sound-dai = <&wm8960>;
 137                 };
 138
 139         };
 140 };
 141
 142 &flexspi {
 143         pinctrl-names = "default";
 144         pinctrl-0 = <&pinctrl_flexspi0>;
 145         status = "okay";
 146
 147         flash@0 {
 148                 compatible = "jedec,spi-nor";
 149                 reg = <0>;
 150                 spi-max-frequency = <80000000>;
 151                 spi-tx-bus-width = <1>;
 152                 spi-rx-bus-width = <4>;
 153         };
 154 };
 155
 156 &A53_0 {
 157         cpu-supply = <&reg_arm>;
 158 };
 159
 160 &A53_1 {
 161         cpu-supply = <&reg_arm>;
 162 };
 163
 164 &A53_2 {
 165         cpu-supply = <&reg_arm>;
 166 };
 167
 168 &A53_3 {
 169         cpu-supply = <&reg_arm>;
 170 };
 171
 172 &eqos {
 173         pinctrl-names = "default";
 174         pinctrl-0 = <&pinctrl_eqos>;
 175         phy-mode = "rgmii-id";
 176         phy-handle = <&ethphy0>;
 177         snps,force_thresh_dma_mode;
 178         snps,mtl-tx-config = <&mtl_tx_setup>;
 179         snps,mtl-rx-config = <&mtl_rx_setup>;
 180         status = "okay";
 181
 182         mdio {
 183                 compatible = "snps,dwmac-mdio";
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186
 187                 ethphy0: ethernet-phy@1 {
 188                         compatible = "ethernet-phy-ieee802.3-c22";
 189                         reg = <1>;
 190                         eee-broken-1000t;
 191                         reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 192                         reset-assert-us = <10000>;
 193                         reset-deassert-us = <80000>;
 194                         realtek,clkout-disable;
 195                 };
 196         };
 197
 198         mtl_tx_setup: tx-queues-config {
 199                 snps,tx-queues-to-use = <5>;
 200                 snps,tx-sched-sp;
 201
 202                 queue0 {
 203                         snps,dcb-algorithm;
 204                         snps,priority = <0x1>;
 205                 };
 206
 207                 queue1 {
 208                         snps,dcb-algorithm;
 209                         snps,priority = <0x2>;
 210                 };
 211
 212                 queue2 {
 213                         snps,dcb-algorithm;
 214                         snps,priority = <0x4>;
 215                 };
 216
 217                 queue3 {
 218                         snps,dcb-algorithm;
 219                         snps,priority = <0x8>;
 220                 };
 221
 222                 queue4 {
 223                         snps,dcb-algorithm;
 224                         snps,priority = <0xf0>;
 225                 };
 226         };
 227
 228         mtl_rx_setup: rx-queues-config {
 229                 snps,rx-queues-to-use = <5>;
 230                 snps,rx-sched-sp;
 231
 232                 queue0 {
 233                         snps,dcb-algorithm;
 234                         snps,priority = <0x1>;
 235                         snps,map-to-dma-channel = <0>;
 236                 };
 237
 238                 queue1 {
 239                         snps,dcb-algorithm;
 240                         snps,priority = <0x2>;
 241                         snps,map-to-dma-channel = <1>;
 242                 };
 243
 244                 queue2 {
 245                         snps,dcb-algorithm;
 246                         snps,priority = <0x4>;
 247                         snps,map-to-dma-channel = <2>;
 248                 };
 249
 250                 queue3 {
 251                         snps,dcb-algorithm;
 252                         snps,priority = <0x8>;
 253                         snps,map-to-dma-channel = <3>;
 254                 };
 255
 256                 queue4 {
 257                         snps,dcb-algorithm;
 258                         snps,priority = <0xf0>;
 259                         snps,map-to-dma-channel = <4>;
 260                 };
 261         };
 262 };
 263
 264 &fec {
 265         pinctrl-names = "default";
 266         pinctrl-0 = <&pinctrl_fec>;
 267         phy-mode = "rgmii-id";
 268         phy-handle = <&ethphy1>;
 269         fsl,magic-packet;
 270         status = "okay";
 271
 272         mdio {
 273                 #address-cells = <1>;
 274                 #size-cells = <0>;
 275
 276                 ethphy1: ethernet-phy@1 {
 277                         compatible = "ethernet-phy-ieee802.3-c22";
 278                         reg = <1>;
 279                         eee-broken-1000t;
 280                         reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
 281                         reset-assert-us = <10000>;
 282                         reset-deassert-us = <80000>;
 283                         realtek,clkout-disable;
 284                 };
 285         };
 286 };
 287
 288 &flexcan1 {
 289         pinctrl-names = "default";
 290         pinctrl-0 = <&pinctrl_flexcan1>;
 291         xceiver-supply = <&reg_can1_stby>;
 292         status = "okay";
 293 };
 294
 295 &flexcan2 {
 296         pinctrl-names = "default";
 297         pinctrl-0 = <&pinctrl_flexcan2>;
 298         xceiver-supply = <&reg_can2_stby>;
 299         status = "disabled";/* can2 pin conflict with pdm */
 300 };
 301
 302 &i2c1 {
 303         clock-frequency = <400000>;
 304         pinctrl-names = "default";
 305         pinctrl-0 = <&pinctrl_i2c1>;
 306         status = "okay";
 307
 308         pmic@25 {
 309                 compatible = "nxp,pca9450c";
 310                 reg = <0x25>;
 311                 pinctrl-names = "default";
 312                 pinctrl-0 = <&pinctrl_pmic>;
 313                 interrupt-parent = <&gpio1>;
 314                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 315
 316                 regulators {
 317                         BUCK1 {
 318                                 regulator-name = "BUCK1";
 319                                 regulator-min-microvolt = <720000>;
 320                                 regulator-max-microvolt = <1000000>;
 321                                 regulator-boot-on;
 322                                 regulator-always-on;
 323                                 regulator-ramp-delay = <3125>;
 324                         };
 325
 326                         reg_arm: BUCK2 {
 327                                 regulator-name = "BUCK2";
 328                                 regulator-min-microvolt = <720000>;
 329                                 regulator-max-microvolt = <1025000>;
 330                                 regulator-boot-on;
 331                                 regulator-always-on;
 332                                 regulator-ramp-delay = <3125>;
 333                                 nxp,dvs-run-voltage = <950000>;
 334                                 nxp,dvs-standby-voltage = <850000>;
 335                         };
 336
 337                         BUCK4 {
 338                                 regulator-name = "BUCK4";
 339                                 regulator-min-microvolt = <3000000>;
 340                                 regulator-max-microvolt = <3600000>;
 341                                 regulator-boot-on;
 342                                 regulator-always-on;
 343                         };
 344
 345                         BUCK5 {
 346                                 regulator-name = "BUCK5";
 347                                 regulator-min-microvolt = <1650000>;
 348                                 regulator-max-microvolt = <1950000>;
 349                                 regulator-boot-on;
 350                                 regulator-always-on;
 351                         };
 352
 353                         BUCK6 {
 354                                 regulator-name = "BUCK6";
 355                                 regulator-min-microvolt = <1045000>;
 356                                 regulator-max-microvolt = <1155000>;
 357                                 regulator-boot-on;
 358                                 regulator-always-on;
 359                         };
 360
 361                         LDO1 {
 362                                 regulator-name = "LDO1";
 363                                 regulator-min-microvolt = <1650000>;
 364                                 regulator-max-microvolt = <1950000>;
 365                                 regulator-boot-on;
 366                                 regulator-always-on;
 367                         };
 368
 369                         LDO3 {
 370                                 regulator-name = "LDO3";
 371                                 regulator-min-microvolt = <1710000>;
 372                                 regulator-max-microvolt = <1890000>;
 373                                 regulator-boot-on;
 374                                 regulator-always-on;
 375                         };
 376
 377                         LDO5 {
 378                                 regulator-name = "LDO5";
 379                                 regulator-min-microvolt = <1800000>;
 380                                 regulator-max-microvolt = <3300000>;
 381                                 regulator-boot-on;
 382                                 regulator-always-on;
 383                         };
 384                 };
 385         };
 386 };
 387
 388 &i2c2 {
 389         clock-frequency = <400000>;
 390         pinctrl-names = "default";
 391         pinctrl-0 = <&pinctrl_i2c2>;
 392         status = "okay";
 393
 394         hdmi@3d {
 395                 compatible = "adi,adv7535";
 396                 reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
 397                 reg-names = "main", "cec", "edid", "packet";
 398                 adi,dsi-lanes = <4>;
 399                 adi,input-depth = <8>;
 400                 adi,input-colorspace = "rgb";
 401                 adi,input-clock = "1x";
 402                 adi,input-style = <1>;
 403                 adi,input-justification = "evenly";
 404
 405                 ports {
 406                         #address-cells = <1>;
 407                         #size-cells = <0>;
 408
 409                         port@0 {
 410                                 reg = <0>;
 411
 412                                 adv7533_in: endpoint {
 413                                         remote-endpoint = <&dsi_out>;
 414                                 };
 415                         };
 416
 417                         port@1 {
 418                                 reg = <1>;
 419
 420                                 adv7533_out: endpoint {
 421                                         remote-endpoint = <&hdmi_connector_in>;
 422                                 };
 423                         };
 424
 425                 };
 426         };
 427 };
 428
 429 &i2c3 {
 430         clock-frequency = <400000>;
 431         pinctrl-names = "default";
 432         pinctrl-0 = <&pinctrl_i2c3>;
 433         status = "okay";
 434
 435         wm8960: codec@1a {
 436                 compatible = "wlf,wm8960";
 437                 reg = <0x1a>;
 438                 #sound-dai-cells = <0>;
 439                 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
 440                 clock-names = "mclk";
 441                 wlf,shared-lrclk;
 442                 wlf,hp-cfg = <3 2 3>;
 443                 wlf,gpio-cfg = <1 3>;
 444                 SPKVDD1-supply = <&reg_audio_pwr>;
 445         };
 446
 447         pca6416: gpio@20 {
 448                 compatible = "ti,tca6416";
 449                 reg = <0x20>;
 450                 gpio-controller;
 451                 #gpio-cells = <2>;
 452                 interrupt-controller;
 453                 #interrupt-cells = <2>;
 454                 pinctrl-names = "default";
 455                 pinctrl-0 = <&pinctrl_pca6416_int>;
 456                 interrupt-parent = <&gpio1>;
 457                 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
 458                 gpio-line-names = "EXT_PWREN1",
 459                         "EXT_PWREN2",
 460                         "CAN1/I2C5_SEL",
 461                         "PDM/CAN2_SEL",
 462                         "FAN_EN",
 463                         "PWR_MEAS_IO1",
 464                         "PWR_MEAS_IO2",
 465                         "EXP_P0_7",
 466                         "EXP_P1_0",
 467                         "EXP_P1_1",
 468                         "EXP_P1_2",
 469                         "EXP_P1_3",
 470                         "EXP_P1_4",
 471                         "EXP_P1_5",
 472                         "EXP_P1_6",
 473                         "EXP_P1_7";
 474         };
 475 };
 476
 477 /* I2C on expansion connector J22. */
 478 &i2c5 {
 479         clock-frequency = <100000>; /* Lower clock speed for external bus. */
 480         pinctrl-names = "default";
 481         pinctrl-0 = <&pinctrl_i2c5>;
 482         status = "disabled"; /* can1 pins conflict with i2c5 */
 483
 484         /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
 485          *     LOW:  CAN1 (default, pull-down)
 486          *     HIGH: I2C5
 487          * You need to set it to high to enable I2C5 (for example, add gpio-hog
 488          * in pca6416 node).
 489          */
 490 };
 491
 492 &lcdif1 {
 493         status = "okay";
 494 };
 495
 496 &mipi_dsi {
 497         samsung,esc-clock-frequency = <10000000>;
 498         status = "okay";
 499
 500         ports {
 501                 port@1 {
 502                         reg = <1>;
 503
 504                         dsi_out: endpoint {
 505                                 remote-endpoint = <&adv7533_in>;
 506                                 data-lanes = <1 2 3 4>;
 507                         };
 508                 };
 509         };
 510 };
 511
 512 &pcie_phy {
 513         fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
 514         clocks = <&pcie0_refclk>;
 515         clock-names = "ref";
 516         status = "okay";
 517 };
 518
 519 &pcie {
 520         pinctrl-names = "default";
 521         pinctrl-0 = <&pinctrl_pcie0>;
 522         reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
 523         vpcie-supply = <&reg_pcie0>;
 524         status = "okay";
 525 };
 526
 527 &pwm1 {
 528         pinctrl-names = "default";
 529         pinctrl-0 = <&pinctrl_pwm1>;
 530         status = "okay";
 531 };
 532
 533 &pwm2 {
 534         pinctrl-names = "default";
 535         pinctrl-0 = <&pinctrl_pwm2>;
 536         status = "okay";
 537 };
 538
 539 &pwm4 {
 540         pinctrl-names = "default";
 541         pinctrl-0 = <&pinctrl_pwm4>;
 542         status = "okay";
 543 };
 544
 545 &sai3 {
 546         pinctrl-names = "default";
 547         pinctrl-0 = <&pinctrl_sai3>;
 548         assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
 549         assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
 550         assigned-clock-rates = <12288000>;
 551         fsl,sai-mclk-direction-output;
 552         status = "okay";
 553 };
 554
 555 &snvs_pwrkey {
 556         status = "okay";
 557 };
 558
 559 &uart1 { /* BT */
 560         pinctrl-names = "default";
 561         pinctrl-0 = <&pinctrl_uart1>;
 562         assigned-clocks = <&clk IMX8MP_CLK_UART1>;
 563         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
 564         uart-has-rtscts;
 565         status = "okay";
 566 };
 567
 568 &uart2 {
 569         /* console */
 570         pinctrl-names = "default";
 571         pinctrl-0 = <&pinctrl_uart2>;
 572         status = "okay";
 573 };
 574
 575 &usb3_phy1 {
 576         status = "okay";
 577 };
 578
 579 &usb3_1 {
 580         status = "okay";
 581 };
 582
 583 &usb_dwc3_1 {
 584         pinctrl-names = "default";
 585         pinctrl-0 = <&pinctrl_usb1_vbus>;
 586         dr_mode = "host";
 587         status = "okay";
 588 };
 589
 590 &uart3 {
 591         pinctrl-names = "default";
 592         pinctrl-0 = <&pinctrl_uart3>;
 593         assigned-clocks = <&clk IMX8MP_CLK_UART3>;
 594         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
 595         uart-has-rtscts;
 596         status = "okay";
 597 };
 598
 599 &usdhc2 {
 600         assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
 601         assigned-clock-rates = <400000000>;
 602         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 603         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 604         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 605         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 606         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 607         vmmc-supply = <&reg_usdhc2_vmmc>;
 608         bus-width = <4>;
 609         status = "okay";
 610 };
 611
 612 &usdhc3 {
 613         assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
 614         assigned-clock-rates = <400000000>;
 615         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 616         pinctrl-0 = <&pinctrl_usdhc3>;
 617         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 618         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 619         bus-width = <8>;
 620         non-removable;
 621         status = "okay";
 622 };
 623
 624 &wdog1 {
 625         pinctrl-names = "default";
 626         pinctrl-0 = <&pinctrl_wdog>;
 627         fsl,ext-reset-output;
 628         status = "okay";
 629 };
 630
 631 &iomuxc {
 632         pinctrl_audio_pwr_reg: audiopwrreggrp {
 633                 fsl,pins = <
 634                         MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29               0xd6
 635                 >;
 636         };
 637
 638         pinctrl_eqos: eqosgrp {
 639                 fsl,pins = <
 640                         MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                             0x2
 641                         MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                           0x2
 642                         MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0                       0x90
 643                         MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1                       0x90
 644                         MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2                       0x90
 645                         MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3                       0x90
 646                         MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK       0x90
 647                         MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL                 0x90
 648                         MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0                       0x16
 649                         MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1                       0x16
 650                         MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2                       0x16
 651                         MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3                       0x16
 652                         MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL                 0x16
 653                         MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK       0x16
 654                         MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22                               0x10
 655                 >;
 656         };
 657
 658         pinctrl_fec: fecgrp {
 659                 fsl,pins = <
 660                         MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x2
 661                         MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x2
 662                         MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x90
 663                         MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x90
 664                         MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2         0x90
 665                         MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3         0x90
 666                         MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC          0x90
 667                         MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x90
 668                         MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x16
 669                         MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x16
 670                         MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2         0x16
 671                         MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3         0x16
 672                         MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x16
 673                         MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC         0x16
 674                         MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02              0x10
 675                 >;
 676         };
 677
 678         pinctrl_flexcan1: flexcan1grp {
 679                 fsl,pins = <
 680                         MX8MP_IOMUXC_SPDIF_RX__CAN1_RX          0x154
 681                         MX8MP_IOMUXC_SPDIF_TX__CAN1_TX          0x154
 682                 >;
 683         };
 684
 685         pinctrl_flexcan2: flexcan2grp {
 686                 fsl,pins = <
 687                         MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX         0x154
 688                         MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX         0x154
 689                 >;
 690         };
 691
 692         pinctrl_flexcan1_reg: flexcan1reggrp {
 693                 fsl,pins = <
 694                         MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05  0x154   /* CAN1_STBY */
 695                 >;
 696         };
 697
 698         pinctrl_flexcan2_reg: flexcan2reggrp {
 699                 fsl,pins = <
 700                         MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154   /* CAN2_STBY */
 701                 >;
 702         };
 703
 704         pinctrl_flexspi0: flexspi0grp {
 705                 fsl,pins = <
 706                         MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK           0x1c2
 707                         MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B        0x82
 708                         MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00      0x82
 709                         MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01      0x82
 710                         MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02      0x82
 711                         MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03      0x82
 712                 >;
 713         };
 714
 715         pinctrl_gpio_led: gpioledgrp {
 716                 fsl,pins = <
 717                         MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16   0x140
 718                 >;
 719         };
 720
 721         pinctrl_i2c1: i2c1grp {
 722                 fsl,pins = <
 723                         MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL         0x400001c2
 724                         MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA         0x400001c2
 725                 >;
 726         };
 727
 728         pinctrl_i2c2: i2c2grp {
 729                 fsl,pins = <
 730                         MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL         0x400001c2
 731                         MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA         0x400001c2
 732                 >;
 733         };
 734
 735         pinctrl_i2c3: i2c3grp {
 736                 fsl,pins = <
 737                         MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL         0x400001c2
 738                         MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA         0x400001c2
 739                 >;
 740         };
 741
 742         pinctrl_i2c5: i2c5grp {
 743                 fsl,pins = <
 744                         MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA         0x400001c2
 745                         MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL         0x400001c2
 746                 >;
 747         };
 748
 749         pinctrl_pcie0: pcie0grp {
 750                 fsl,pins = <
 751                         MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B    0x60 /* open drain, pull up */
 752                         MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07      0x40
 753                 >;
 754         };
 755
 756         pinctrl_pcie0_reg: pcie0reggrp {
 757                 fsl,pins = <
 758                         MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06      0x40
 759                 >;
 760         };
 761
 762         pinctrl_pmic: pmicgrp {
 763                 fsl,pins = <
 764                         MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03     0x000001c0
 765                 >;
 766         };
 767
 768         pinctrl_pca6416_int: pca6416_int_grp {
 769                 fsl,pins = <
 770                         MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12     0x146 /* Input pull-up. */
 771                 >;
 772         };
 773
 774         pinctrl_pwm1: pwm1grp {
 775                 fsl,pins = <
 776                         MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT       0x116
 777                 >;
 778         };
 779
 780         pinctrl_pwm2: pwm2grp {
 781                 fsl,pins = <
 782                         MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT       0x116
 783                 >;
 784         };
 785
 786         pinctrl_pwm4: pwm4grp {
 787                 fsl,pins = <
 788                         MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT        0x116
 789                 >;
 790         };
 791
 792         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 793                 fsl,pins = <
 794                         MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19    0x40
 795                 >;
 796         };
 797
 798         pinctrl_uart1: uart1grp {
 799                 fsl,pins = <
 800                         MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX    0x140
 801                         MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX    0x140
 802                         MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS   0x140
 803                         MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS   0x140
 804                 >;
 805         };
 806
 807         pinctrl_sai3: sai3grp {
 808                 fsl,pins = <
 809                         MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC   0xd6
 810                         MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK    0xd6
 811                         MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00  0xd6
 812                         MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00  0xd6
 813                         MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK      0xd6
 814                 >;
 815         };
 816
 817         pinctrl_uart2: uart2grp {
 818                 fsl,pins = <
 819                         MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX    0x140
 820                         MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX    0x140
 821                 >;
 822         };
 823
 824         pinctrl_usb1_vbus: usb1grp {
 825                 fsl,pins = <
 826                         MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR   0x10
 827                 >;
 828         };
 829
 830         pinctrl_uart3: uart3grp {
 831                 fsl,pins = <
 832                         MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX          0x140
 833                         MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX          0x140
 834                         MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS          0x140
 835                         MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS         0x140
 836                 >;
 837         };
 838
 839         pinctrl_usdhc2: usdhc2grp {
 840                 fsl,pins = <
 841                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x190
 842                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d0
 843                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d0
 844                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d0
 845                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d0
 846                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d0
 847                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
 848                 >;
 849         };
 850
 851         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 852                 fsl,pins = <
 853                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x194
 854                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d4
 855                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d4
 856                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d4
 857                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d4
 858                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d4
 859                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
 860                 >;
 861         };
 862
 863         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 864                 fsl,pins = <
 865                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x196
 866                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d6
 867                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d6
 868                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d6
 869                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d6
 870                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d6
 871                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
 872                 >;
 873         };
 874
 875         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 876                 fsl,pins = <
 877                         MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12       0x1c4
 878                 >;
 879         };
 880
 881         pinctrl_usdhc3: usdhc3grp {
 882                 fsl,pins = <
 883                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x190
 884                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d0
 885                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d0
 886                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d0
 887                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d0
 888                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d0
 889                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d0
 890                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d0
 891                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d0
 892                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d0
 893                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x190
 894                 >;
 895         };
 896
 897         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 898                 fsl,pins = <
 899                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x194
 900                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d4
 901                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d4
 902                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d4
 903                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d4
 904                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d4
 905                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d4
 906                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d4
 907                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d4
 908                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d4
 909                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x194
 910                 >;
 911         };
 912
 913         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 914                 fsl,pins = <
 915                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x196
 916                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d6
 917                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d6
 918                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d6
 919                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d6
 920                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d6
 921                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d6
 922                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d6
 923                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d6
 924                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d6
 925                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x196
 926                 >;
 927         };
 928
 929         pinctrl_wdog: wdoggrp {
 930                 fsl,pins = <
 931                         MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B   0x166
 932                 >;
 933         };
 934 };