1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
9 model = "DH electronics i.MX8M Plus DHCOM SoM";
10 compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
21 device_type = "memory";
22 /* Memory size 512 MiB..8 GiB will be filled by U-Boot */
23 reg = <0x0 0x40000000 0 0x08000000>;
26 reg_eth_vio: regulator-eth-vio {
27 compatible = "regulator-fixed";
28 gpio = <&ioexp 2 GPIO_ACTIVE_LOW>;
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
33 regulator-name = "eth_vio";
34 vin-supply = <&buck4>;
37 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
38 compatible = "regulator-fixed";
40 gpio = <&gpio2 19 0>; /* SD2_RESET */
41 off-on-delay-us = <12000>;
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
44 regulator-max-microvolt = <3300000>;
45 regulator-min-microvolt = <3300000>;
46 regulator-name = "VDD_3V3_SD";
47 startup-delay-us = <100>;
48 vin-supply = <&buck4>;
51 reg_vdd_3p3v_awo: regulator-vdd-3p3v-awo { /* VDD_3V3_AWO */
52 compatible = "regulator-fixed";
54 regulator-min-microvolt = <3300000>;
55 regulator-max-microvolt = <3300000>;
56 regulator-name = "VDD_3P3V_AWO";
59 wlan_pwrseq: wifi-pwrseq {
60 compatible = "mmc-pwrseq-simple";
61 reset-gpios = <&ioexp 1 GPIO_ACTIVE_LOW>;
66 cpu-supply = <&buck2>;
70 cpu-supply = <&buck2>;
74 cpu-supply = <&buck2>;
78 cpu-supply = <&buck2>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_ecspi1>;
84 cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_ecspi2>;
91 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
95 &eqos { /* First ethernet */
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_eqos_rgmii>;
98 phy-handle = <ðphy0g>;
99 phy-mode = "rgmii-id";
103 compatible = "snps,dwmac-mdio";
104 #address-cells = <1>;
107 /* Up to one of these two PHYs may be populated. */
108 ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */
109 compatible = "ethernet-phy-id0007.c110",
110 "ethernet-phy-ieee802.3-c22";
111 interrupt-parent = <&gpio3>;
112 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
113 pinctrl-0 = <&pinctrl_ethphy0>;
114 pinctrl-names = "default";
116 reset-assert-us = <1000>;
117 reset-deassert-us = <1000>;
118 reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;
119 /* Non-default PHY population option. */
123 ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */
124 compatible = "ethernet-phy-id0022.1642",
125 "ethernet-phy-ieee802.3-c22";
126 interrupt-parent = <&gpio3>;
127 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
128 micrel,led-mode = <0>;
129 pinctrl-0 = <&pinctrl_ethphy0>;
130 pinctrl-names = "default";
132 reset-assert-us = <1000>;
133 reset-deassert-us = <1000>;
134 reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;
135 /* Default PHY population option. */
141 &fec { /* Second ethernet */
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_fec_rmii>;
144 phy-handle = <ðphy1f>;
150 #address-cells = <1>;
153 /* Up to one PHY may be populated. */
154 ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
155 compatible = "ethernet-phy-id0007.c110",
156 "ethernet-phy-ieee802.3-c22";
157 interrupt-parent = <&gpio4>;
158 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
159 pinctrl-0 = <&pinctrl_ethphy1>;
160 pinctrl-names = "default";
162 reset-assert-us = <1000>;
163 reset-deassert-us = <1000>;
164 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
165 /* Non-default PHY population option. */
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_flexcan1>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_flexcan2>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_flexspi>;
188 flash@0 { /* W25Q128JWPIM */
189 compatible = "jedec,spi-nor";
191 spi-max-frequency = <80000000>;
192 spi-tx-bus-width = <4>;
193 spi-rx-bus-width = <4>;
199 "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",
200 "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
201 "", "", "", "", "", "", "", "",
202 "", "", "", "", "", "", "", "";
207 "", "", "", "", "", "", "", "",
208 "", "", "", "DHCOM-K", "", "", "", "",
209 "", "", "", "", "DHCOM-INT", "", "", "",
210 "", "", "", "", "", "", "", "";
215 "", "", "", "", "", "", "", "",
216 "", "", "", "", "", "", "SOM-HW0", "",
217 "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
218 "SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
223 "", "", "", "", "", "", "", "",
224 "", "", "", "", "", "", "", "",
225 "", "", "", "SOM-HW1", "", "", "", "",
226 "", "", "", "DHCOM-D", "", "", "", "";
231 "", "", "DHCOM-C", "", "", "", "", "",
232 "", "", "", "", "", "", "", "",
233 "", "", "", "", "", "", "DHCOM-E", "DHCOM-F",
234 "", "", "", "", "", "", "", "";
238 clock-frequency = <100000>;
239 pinctrl-names = "default", "gpio";
240 pinctrl-0 = <&pinctrl_i2c3>;
241 pinctrl-1 = <&pinctrl_i2c3_gpio>;
242 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
243 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
246 tc_bridge: bridge@f {
247 compatible = "toshiba,tc9595", "toshiba,tc358767";
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_tc9595>;
252 clocks = <&clk IMX8MP_CLK_CLKOUT2>;
253 assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>,
254 <&clk IMX8MP_CLK_CLKOUT2>,
255 <&clk IMX8MP_AUDIO_PLL2_OUT>;
256 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
257 assigned-clock-rates = <13000000>, <13000000>, <156000000>;
258 reset-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
262 #address-cells = <1>;
268 tc_bridge_in: endpoint {
269 data-lanes = <1 2 3 4>;
270 remote-endpoint = <&dsi_out>;
277 compatible = "nxp,pca9450c";
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_pmic>;
281 interrupt-parent = <&gpio1>;
282 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
285 * i.MX 8M Plus Data Sheet for Consumer Products
286 * 3.1.4 Operating ranges
290 buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */
291 regulator-min-microvolt = <850000>;
292 regulator-max-microvolt = <1000000>;
293 regulator-ramp-delay = <3125>;
298 buck2: BUCK2 { /* VDD_ARM */
299 nxp,dvs-run-voltage = <950000>;
300 nxp,dvs-standby-voltage = <850000>;
301 regulator-min-microvolt = <850000>;
302 regulator-max-microvolt = <1000000>;
303 regulator-ramp-delay = <3125>;
308 buck4: BUCK4 { /* VDD_3V3 */
309 regulator-min-microvolt = <3300000>;
310 regulator-max-microvolt = <3300000>;
315 buck5: BUCK5 { /* VDD_1V8 */
316 regulator-min-microvolt = <1800000>;
317 regulator-max-microvolt = <1800000>;
322 buck6: BUCK6 { /* NVCC_DRAM_1V1 */
323 regulator-min-microvolt = <1100000>;
324 regulator-max-microvolt = <1100000>;
329 ldo1: LDO1 { /* NVCC_SNVS_1V8 */
330 regulator-min-microvolt = <1800000>;
331 regulator-max-microvolt = <1800000>;
336 ldo3: LDO3 { /* VDDA_1V8 */
337 regulator-min-microvolt = <1800000>;
338 regulator-max-microvolt = <1800000>;
343 ldo4: LDO4 { /* PMIC_LDO4 */
344 regulator-min-microvolt = <3300000>;
345 regulator-max-microvolt = <3300000>;
348 ldo5: LDO5 { /* NVCC_SD2 */
349 regulator-min-microvolt = <1800000>;
350 regulator-max-microvolt = <3300000>;
356 compatible = "ti,ads1015";
358 interrupts-extended = <&ioexp 7 IRQ_TYPE_EDGE_FALLING>;
359 #address-cells = <1>;
362 channel@0 { /* Voltage over AIN0 and AIN1. */
366 channel@1 { /* Voltage over AIN0 and AIN3. */
370 channel@2 { /* Voltage over AIN1 and AIN3. */
374 channel@3 { /* Voltage over AIN2 and AIN3. */
378 channel@4 { /* Voltage over AIN0 and GND. */
382 channel@5 { /* Voltage over AIN1 and GND. */
386 channel@6 { /* Voltage over AIN2 and GND. */
390 channel@7 { /* Voltage over AIN3 and GND. */
396 compatible = "ti,tsc2004";
398 interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_touch>;
401 vio-supply = <&buck4>;
404 eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */
405 compatible = "atmel,24c32"; /* M24C32-D */
411 compatible = "microcrystal,rv3032";
413 interrupts-extended = <&ioexp 3 IRQ_TYPE_EDGE_FALLING>;
417 eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */
418 compatible = "atmel,24c32"; /* M24C32-D */
424 compatible = "nxp,pca9539";
428 interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
429 interrupt-controller;
430 #interrupt-cells = <2>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_ioexp>;
436 "BT_REG_EN", "WL_REG_EN", "VIO_SWITCHED_#EN", "RTC_#INT",
437 "ENET_QOS_#RST", "RGB_OSZ_ENABLE", "USB1_ID", "ADC_ALTER_RDY",
438 "DHCOM-W", "DHCOM-V", "DHCOM-U", "DHCOM-T",
439 "BT_HOST_WAKE", "BT_DEV_WAKE", "", "";
444 clock-frequency = <100000>;
445 pinctrl-names = "default", "gpio";
446 pinctrl-0 = <&pinctrl_i2c4>;
447 pinctrl-1 = <&pinctrl_i2c4_gpio>;
448 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
449 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
453 &i2c5 { /* HDMI EDID bus */
454 clock-frequency = <100000>;
455 pinctrl-names = "default", "gpio";
456 pinctrl-0 = <&pinctrl_i2c5>;
457 pinctrl-1 = <&pinctrl_i2c5_gpio>;
458 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
459 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
464 samsung,burst-clock-frequency = <160000000>;
465 samsung,esc-clock-frequency = <10000000>;
472 data-lanes = <1 2 3 4>;
473 remote-endpoint = <&tc_bridge_in>;
480 pinctrl-0 = <&pinctrl_pwm1>;
481 pinctrl-names = "default";
487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_uart1>;
495 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_uart2>;
501 * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock,
502 * which with 16x oversampling yields 5 Mbdps baud base,
503 * which can be well divided by 5/4 to achieve 4 Mbdps,
504 * which is exactly the maximum rate supported by muRata
505 * 2AE bluetooth UART.
507 assigned-clocks = <&clk IMX8MP_CLK_UART2>;
508 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
509 assigned-clock-rates = <80000000>;
512 compatible = "cypress,cyw4373a0-bt";
513 shutdown-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>;
514 max-speed = <4000000>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&pinctrl_uart3>;
526 pinctrl-names = "default";
527 pinctrl-0 = <&pinctrl_uart4>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&pinctrl_usb1_vbus>;
561 pinctrl-names = "default", "state_100mhz", "state_200mhz";
562 pinctrl-0 = <&pinctrl_usdhc1>;
563 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
564 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
565 mmc-pwrseq = <&wlan_pwrseq>;
566 vmmc-supply = <&buck4>;
570 keep-power-in-suspend;
573 #address-cells = <1>;
576 brcmf: bcrmf@1 { /* muRata 2AE */
578 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
580 * The "host-wake" interrupt output is by default not
581 * connected to the SoC, but can be connected on to
582 * SoC pin on the carrier board.
589 pinctrl-names = "default", "state_100mhz", "state_200mhz";
590 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
591 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
592 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
593 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
594 vmmc-supply = <®_usdhc2_vmmc>;
601 pinctrl-names = "default", "state_100mhz", "state_200mhz";
602 pinctrl-0 = <&pinctrl_usdhc3>;
603 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
604 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
605 vmmc-supply = <&buck4>;
606 vqmmc-supply = <&buck5>;
613 pinctrl-names = "default";
614 pinctrl-0 = <&pinctrl_wdog>;
615 fsl,ext-reset-output;
620 pinctrl-0 = <&pinctrl_hog_base
621 &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
622 &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
623 &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
624 &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
625 &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
626 &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
627 &pinctrl_dhcom_s &pinctrl_dhcom_int>;
628 pinctrl-names = "default";
630 pinctrl_dhcom_a: dhcom-a-grp {
632 /* ENET_QOS_EVENT0-OUT */
633 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x2
637 pinctrl_dhcom_b: dhcom-b-grp {
639 /* ENET_QOS_EVENT0-IN */
640 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x2
644 pinctrl_dhcom_c: dhcom-c-grp {
647 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x2
651 pinctrl_dhcom_d: dhcom-d-grp {
654 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x2
658 pinctrl_dhcom_e: dhcom-e-grp {
661 MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x2
665 pinctrl_dhcom_f: dhcom-f-grp {
668 MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x2
672 pinctrl_dhcom_g: dhcom-g-grp {
675 MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2
679 pinctrl_dhcom_h: dhcom-h-grp {
682 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x2
686 pinctrl_dhcom_i: dhcom-i-grp {
689 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2
693 pinctrl_dhcom_j: dhcom-j-grp {
696 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x2
700 pinctrl_dhcom_k: dhcom-k-grp {
703 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x2
707 pinctrl_dhcom_l: dhcom-l-grp {
710 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x2
714 pinctrl_dhcom_m: dhcom-m-grp {
717 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x2
721 pinctrl_dhcom_n: dhcom-n-grp {
724 MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x2
728 pinctrl_dhcom_o: dhcom-o-grp {
731 MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x2
735 pinctrl_dhcom_p: dhcom-p-grp {
738 MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x2
742 pinctrl_dhcom_q: dhcom-q-grp {
745 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x2
749 pinctrl_dhcom_r: dhcom-r-grp {
752 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x2
756 pinctrl_dhcom_s: dhcom-s-grp {
759 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x2
763 pinctrl_dhcom_int: dhcom-int-grp {
765 /* INT_HIGHEST_PRIO */
766 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x2
770 pinctrl_hog_base: dhcom-hog-base-grp {
772 /* GPIOs for memory coding */
773 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x40000080
774 MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40000080
775 MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000080
776 /* GPIOs for hardware coding */
777 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000080
778 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000080
779 MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x40000080
783 pinctrl_ecspi1: dhcom-ecspi1-grp {
785 MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x44
786 MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x44
787 MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x44
788 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x40
792 pinctrl_ecspi2: dhcom-ecspi2-grp {
794 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44
795 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44
796 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44
797 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40
801 pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp { /* RGMII */
803 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
804 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
805 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
806 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
807 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
808 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
809 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
810 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
811 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
812 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
813 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
814 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
815 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
816 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
820 pinctrl_eqos_rmii: dhcom-eqos-rmii-grp { /* RMII */
822 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
823 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
824 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
825 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
826 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
827 MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x1f
828 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
829 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
830 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
832 MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000001f
836 pinctrl_ethphy0: dhcom-ethphy0-grp {
838 /* ENET_QOS_#INT Interrupt */
839 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22
843 pinctrl_ethphy1: dhcom-ethphy1-grp {
845 /* ENET1_#RST Reset */
846 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x11
847 /* ENET1_#INT Interrupt */
848 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x11
852 pinctrl_fec_rgmii: dhcom-fec-rgmii-grp { /* RGMII */
854 MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f
855 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
856 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
857 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
858 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
859 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
860 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
861 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
862 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
863 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
864 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
865 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
866 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
867 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
868 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
869 MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x1f
873 pinctrl_fec_rmii: dhcom-fec-rmii-grp { /* RMII */
875 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
876 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
877 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
878 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
879 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
880 MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x91
881 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
882 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
883 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
885 MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x4000001f
889 pinctrl_flexcan1: dhcom-flexcan1-grp {
891 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
892 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
896 pinctrl_flexcan2: dhcom-flexcan2-grp {
898 MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154
899 MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154
903 pinctrl_flexspi: dhcom-flexspi-grp {
905 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
906 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
907 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
908 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
909 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
910 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
914 pinctrl_hdmi: dhcom-hdmi-grp {
916 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154
917 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154
921 pinctrl_i2c3: dhcom-i2c3-grp {
923 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084
924 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084
928 pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {
930 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84
931 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84
935 pinctrl_i2c4: dhcom-i2c4-grp {
937 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084
938 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084
942 pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {
944 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84
945 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84
949 pinctrl_i2c5: dhcom-i2c5-grp {
951 MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084
952 MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084
956 pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {
958 MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84
959 MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84
963 pinctrl_ioexp: dhcom-ioexp-grp {
966 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22
970 pinctrl_pmic: dhcom-pmic-grp {
973 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
977 pinctrl_pwm1: dhcom-pwm1-grp {
979 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x6
983 pinctrl_tc9595: dhcom-tc9595-grp {
985 /* RESET_DSIBRIDGE */
986 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000146
987 /* DSI-CONV_INT Interrupt */
988 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x141
992 pinctrl_sai3: dhcom-sai3-grp {
994 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
995 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
996 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
997 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
1001 pinctrl_touch: dhcom-touch-grp {
1004 MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x40000080
1008 pinctrl_uart1: dhcom-uart1-grp {
1011 MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x49
1012 MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x49
1013 MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49
1014 MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x49
1018 pinctrl_uart2: dhcom-uart2-grp {
1020 /* Bluetooth UART */
1021 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
1022 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
1023 MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49
1024 MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49
1028 pinctrl_uart3: dhcom-uart3-grp {
1030 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49
1031 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x49
1032 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x49
1033 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x49
1037 pinctrl_uart4: dhcom-uart4-grp {
1039 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
1040 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
1044 pinctrl_usb1_vbus: dhcom-usb1-grp {
1046 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6
1047 MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x80
1051 pinctrl_usdhc1: dhcom-usdhc1-grp {
1053 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
1054 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
1055 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
1056 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
1057 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
1058 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
1062 pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
1064 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
1065 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
1066 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
1067 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
1068 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
1069 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
1073 pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
1075 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
1076 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
1077 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
1078 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
1079 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
1080 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
1084 pinctrl_usdhc2: dhcom-usdhc2-grp {
1086 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
1087 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
1088 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
1089 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
1090 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
1091 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
1092 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
1096 pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
1098 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
1099 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
1100 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
1101 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
1102 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
1103 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
1104 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
1108 pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {
1110 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
1111 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
1112 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
1113 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
1114 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
1115 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
1116 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
1120 pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {
1122 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20
1126 pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {
1128 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080
1132 pinctrl_usdhc3: dhcom-usdhc3-grp {
1134 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
1135 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
1136 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
1137 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
1138 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
1139 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
1140 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
1141 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
1142 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
1143 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
1144 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
1145 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
1149 pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {
1151 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
1152 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
1153 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
1154 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
1155 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
1156 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
1157 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
1158 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
1159 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
1160 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
1161 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
1162 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
1166 pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {
1168 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
1169 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
1170 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
1171 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
1172 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
1173 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
1174 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
1175 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
1176 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
1177 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
1178 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
1179 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
1183 pinctrl_wdog: dhcom-wdog-grp {
1185 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6