arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
   4  */
   5
   6 #include "imx8mp.dtsi"
   7
   8 / {
   9         model = "DH electronics i.MX8M Plus DHCOM SoM";
  10         compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
  11
  12         aliases {
  13                 ethernet0 = &eqos;
  14                 ethernet1 = &fec;
  15                 rtc0 = &rv3032;
  16                 rtc1 = &snvs_rtc;
  17                 spi0 = &flexspi;
  18         };
  19
  20         memory@40000000 {
  21                 device_type = "memory";
  22                 /* Memory size 512 MiB..8 GiB will be filled by U-Boot */
  23                 reg = <0x0 0x40000000 0 0x08000000>;
  24         };
  25
  26         reg_eth_vio: regulator-eth-vio {
  27                 compatible = "regulator-fixed";
  28                 gpio = <&ioexp 2 GPIO_ACTIVE_LOW>;
  29                 regulator-always-on;
  30                 regulator-boot-on;
  31                 regulator-min-microvolt = <3300000>;
  32                 regulator-max-microvolt = <3300000>;
  33                 regulator-name = "eth_vio";
  34                 vin-supply = <&buck4>;
  35         };
  36
  37         reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
  38                 compatible = "regulator-fixed";
  39                 enable-active-high;
  40                 gpio = <&gpio2 19 0>; /* SD2_RESET */
  41                 off-on-delay-us = <12000>;
  42                 pinctrl-names = "default";
  43                 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
  44                 regulator-max-microvolt = <3300000>;
  45                 regulator-min-microvolt = <3300000>;
  46                 regulator-name = "VDD_3V3_SD";
  47                 startup-delay-us = <100>;
  48                 vin-supply = <&buck4>;
  49         };
  50
  51         reg_vdd_3p3v_awo: regulator-vdd-3p3v-awo {      /* VDD_3V3_AWO */
  52                 compatible = "regulator-fixed";
  53                 regulator-always-on;
  54                 regulator-min-microvolt = <3300000>;
  55                 regulator-max-microvolt = <3300000>;
  56                 regulator-name = "VDD_3P3V_AWO";
  57         };
  58
  59         wlan_pwrseq: wifi-pwrseq {
  60                 compatible = "mmc-pwrseq-simple";
  61                 reset-gpios = <&ioexp 1 GPIO_ACTIVE_LOW>;
  62         };
  63 };
  64
  65 &A53_0 {
  66         cpu-supply = <&buck2>;
  67 };
  68
  69 &A53_1 {
  70         cpu-supply = <&buck2>;
  71 };
  72
  73 &A53_2 {
  74         cpu-supply = <&buck2>;
  75 };
  76
  77 &A53_3 {
  78         cpu-supply = <&buck2>;
  79 };
  80
  81 &ecspi1 {
  82         pinctrl-names = "default";
  83         pinctrl-0 = <&pinctrl_ecspi1>;
  84         cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
  85         status = "disabled";
  86 };
  87
  88 &ecspi2 {
  89         pinctrl-names = "default";
  90         pinctrl-0 = <&pinctrl_ecspi2>;
  91         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
  92         status = "disabled";
  93 };
  94
  95 &eqos { /* First ethernet */
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&pinctrl_eqos_rgmii>;
  98         phy-handle = <&ethphy0g>;
  99         phy-mode = "rgmii-id";
 100         status = "okay";
 101
 102         mdio {
 103                 compatible = "snps,dwmac-mdio";
 104                 #address-cells = <1>;
 105                 #size-cells = <0>;
 106
 107                 /* Up to one of these two PHYs may be populated. */
 108                 ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */
 109                         compatible = "ethernet-phy-id0007.c110",
 110                                      "ethernet-phy-ieee802.3-c22";
 111                         interrupt-parent = <&gpio3>;
 112                         interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 113                         pinctrl-0 = <&pinctrl_ethphy0>;
 114                         pinctrl-names = "default";
 115                         reg = <0>;
 116                         reset-assert-us = <1000>;
 117                         reset-deassert-us = <1000>;
 118                         reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;
 119                         /* Non-default PHY population option. */
 120                         status = "disabled";
 121                 };
 122
 123                 ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */
 124                         compatible = "ethernet-phy-id0022.1642",
 125                                      "ethernet-phy-ieee802.3-c22";
 126                         interrupt-parent = <&gpio3>;
 127                         interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 128                         micrel,led-mode = <0>;
 129                         pinctrl-0 = <&pinctrl_ethphy0>;
 130                         pinctrl-names = "default";
 131                         reg = <5>;
 132                         reset-assert-us = <1000>;
 133                         reset-deassert-us = <1000>;
 134                         reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;
 135                         /* Default PHY population option. */
 136                         status = "okay";
 137                 };
 138         };
 139 };
 140
 141 &fec {  /* Second ethernet */
 142         pinctrl-names = "default";
 143         pinctrl-0 = <&pinctrl_fec_rmii>;
 144         phy-handle = <&ethphy1f>;
 145         phy-mode = "rmii";
 146         fsl,magic-packet;
 147         status = "okay";
 148
 149         mdio {
 150                 #address-cells = <1>;
 151                 #size-cells = <0>;
 152
 153                 /* Up to one PHY may be populated. */
 154                 ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
 155                         compatible = "ethernet-phy-id0007.c110",
 156                                      "ethernet-phy-ieee802.3-c22";
 157                         interrupt-parent = <&gpio4>;
 158                         interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 159                         pinctrl-0 = <&pinctrl_ethphy1>;
 160                         pinctrl-names = "default";
 161                         reg = <1>;
 162                         reset-assert-us = <1000>;
 163                         reset-deassert-us = <1000>;
 164                         reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
 165                         /* Non-default PHY population option. */
 166                         status = "disabled";
 167                 };
 168         };
 169 };
 170
 171 &flexcan1 {
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&pinctrl_flexcan1>;
 174         status = "disabled";
 175 };
 176
 177 &flexcan2 {
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_flexcan2>;
 180         status = "disabled";
 181 };
 182
 183 &flexspi {
 184         pinctrl-names = "default";
 185         pinctrl-0 = <&pinctrl_flexspi>;
 186         status = "okay";
 187
 188         flash@0 {       /* W25Q128JWPIM */
 189                 compatible = "jedec,spi-nor";
 190                 reg = <0>;
 191                 spi-max-frequency = <80000000>;
 192                 spi-tx-bus-width = <4>;
 193                 spi-rx-bus-width = <4>;
 194         };
 195 };
 196
 197 &gpio1 {
 198         gpio-line-names =
 199                 "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",
 200                 "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
 201                 "", "", "", "", "", "", "", "",
 202                 "", "", "", "", "", "", "", "";
 203 };
 204
 205 &gpio2 {
 206         gpio-line-names =
 207                 "", "", "", "", "", "", "", "",
 208                 "", "", "", "DHCOM-K", "", "", "", "",
 209                 "", "", "", "", "DHCOM-INT", "", "", "",
 210                 "", "", "", "", "", "", "", "";
 211 };
 212
 213 &gpio3 {
 214         gpio-line-names =
 215                 "", "", "", "", "", "", "", "",
 216                 "", "", "", "", "", "", "SOM-HW0", "",
 217                 "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
 218                 "SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
 219 };
 220
 221 &gpio4 {
 222         gpio-line-names =
 223                 "", "", "", "", "", "", "", "",
 224                 "", "", "", "", "", "", "", "",
 225                 "", "", "", "SOM-HW1", "", "", "", "",
 226                 "", "", "", "DHCOM-D", "", "", "", "";
 227 };
 228
 229 &gpio5 {
 230         gpio-line-names =
 231                 "", "", "DHCOM-C", "", "", "", "", "",
 232                 "", "", "", "", "", "", "", "",
 233                 "", "", "", "", "", "", "DHCOM-E", "DHCOM-F",
 234                 "", "", "", "", "", "", "", "";
 235 };
 236
 237 &i2c3 {
 238         clock-frequency = <100000>;
 239         pinctrl-names = "default", "gpio";
 240         pinctrl-0 = <&pinctrl_i2c3>;
 241         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 242         scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 243         sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 244         status = "okay";
 245
 246         tc_bridge: bridge@f {
 247                 compatible = "toshiba,tc9595", "toshiba,tc358767";
 248                 pinctrl-names = "default";
 249                 pinctrl-0 = <&pinctrl_tc9595>;
 250                 reg = <0xf>;
 251                 clock-names = "ref";
 252                 clocks = <&clk IMX8MP_CLK_CLKOUT2>;
 253                 assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>,
 254                                   <&clk IMX8MP_CLK_CLKOUT2>,
 255                                   <&clk IMX8MP_AUDIO_PLL2_OUT>;
 256                 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
 257                 assigned-clock-rates = <13000000>, <13000000>, <156000000>;
 258                 reset-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
 259                 status = "disabled";
 260
 261                 ports {
 262                         #address-cells = <1>;
 263                         #size-cells = <0>;
 264
 265                         port@0 {
 266                                 reg = <0>;
 267
 268                                 tc_bridge_in: endpoint {
 269                                         data-lanes = <1 2 3 4>;
 270                                         remote-endpoint = <&dsi_out>;
 271                                 };
 272                         };
 273                 };
 274         };
 275
 276         pmic: pmic@25 {
 277                 compatible = "nxp,pca9450c";
 278                 reg = <0x25>;
 279                 pinctrl-names = "default";
 280                 pinctrl-0 = <&pinctrl_pmic>;
 281                 interrupt-parent = <&gpio1>;
 282                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 283
 284                 /*
 285                  * i.MX 8M Plus Data Sheet for Consumer Products
 286                  * 3.1.4 Operating ranges
 287                  * MIMX8ML8CVNKZAB
 288                  */
 289                 regulators {
 290                         buck1: BUCK1 {  /* VDD_SOC (dual-phase with BUCK3) */
 291                                 regulator-min-microvolt = <850000>;
 292                                 regulator-max-microvolt = <1000000>;
 293                                 regulator-ramp-delay = <3125>;
 294                                 regulator-always-on;
 295                                 regulator-boot-on;
 296                         };
 297
 298                         buck2: BUCK2 {  /* VDD_ARM */
 299                                 nxp,dvs-run-voltage = <950000>;
 300                                 nxp,dvs-standby-voltage = <850000>;
 301                                 regulator-min-microvolt = <850000>;
 302                                 regulator-max-microvolt = <1000000>;
 303                                 regulator-ramp-delay = <3125>;
 304                                 regulator-always-on;
 305                                 regulator-boot-on;
 306                         };
 307
 308                         buck4: BUCK4 {  /* VDD_3V3 */
 309                                 regulator-min-microvolt = <3300000>;
 310                                 regulator-max-microvolt = <3300000>;
 311                                 regulator-always-on;
 312                                 regulator-boot-on;
 313                         };
 314
 315                         buck5: BUCK5 {  /* VDD_1V8 */
 316                                 regulator-min-microvolt = <1800000>;
 317                                 regulator-max-microvolt = <1800000>;
 318                                 regulator-always-on;
 319                                 regulator-boot-on;
 320                         };
 321
 322                         buck6: BUCK6 {  /* NVCC_DRAM_1V1 */
 323                                 regulator-min-microvolt = <1100000>;
 324                                 regulator-max-microvolt = <1100000>;
 325                                 regulator-always-on;
 326                                 regulator-boot-on;
 327                         };
 328
 329                         ldo1: LDO1 {    /* NVCC_SNVS_1V8 */
 330                                 regulator-min-microvolt = <1800000>;
 331                                 regulator-max-microvolt = <1800000>;
 332                                 regulator-always-on;
 333                                 regulator-boot-on;
 334                         };
 335
 336                         ldo3: LDO3 {    /* VDDA_1V8 */
 337                                 regulator-min-microvolt = <1800000>;
 338                                 regulator-max-microvolt = <1800000>;
 339                                 regulator-always-on;
 340                                 regulator-boot-on;
 341                         };
 342
 343                         ldo4: LDO4 {    /* PMIC_LDO4 */
 344                                 regulator-min-microvolt = <3300000>;
 345                                 regulator-max-microvolt = <3300000>;
 346                         };
 347
 348                         ldo5: LDO5 {    /* NVCC_SD2 */
 349                                 regulator-min-microvolt = <1800000>;
 350                                 regulator-max-microvolt = <3300000>;
 351                         };
 352                 };
 353         };
 354
 355         adc@48 {
 356                 compatible = "ti,ads1015";
 357                 reg = <0x48>;
 358                 interrupts-extended = <&ioexp 7 IRQ_TYPE_EDGE_FALLING>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361
 362                 channel@0 {     /* Voltage over AIN0 and AIN1. */
 363                         reg = <0>;
 364                 };
 365
 366                 channel@1 {     /* Voltage over AIN0 and AIN3. */
 367                         reg = <1>;
 368                 };
 369
 370                 channel@2 {     /* Voltage over AIN1 and AIN3. */
 371                         reg = <2>;
 372                 };
 373
 374                 channel@3 {     /* Voltage over AIN2 and AIN3. */
 375                         reg = <3>;
 376                 };
 377
 378                 channel@4 {     /* Voltage over AIN0 and GND. */
 379                         reg = <4>;
 380                 };
 381
 382                 channel@5 {     /* Voltage over AIN1 and GND. */
 383                         reg = <5>;
 384                 };
 385
 386                 channel@6 {     /* Voltage over AIN2 and GND. */
 387                         reg = <6>;
 388                 };
 389
 390                 channel@7 {     /* Voltage over AIN3 and GND. */
 391                         reg = <7>;
 392                 };
 393         };
 394
 395         touchscreen@49 {
 396                 compatible = "ti,tsc2004";
 397                 reg = <0x49>;
 398                 interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&pinctrl_touch>;
 401                 vio-supply = <&buck4>;
 402         };
 403
 404         eeprom0: eeprom@50 {    /* EEPROM with EQoS MAC address */
 405                 compatible = "atmel,24c32";     /* M24C32-D */
 406                 pagesize = <32>;
 407                 reg = <0x50>;
 408         };
 409
 410         rv3032: rtc@51 {
 411                 compatible = "microcrystal,rv3032";
 412                 reg = <0x51>;
 413                 interrupts-extended = <&ioexp 3 IRQ_TYPE_EDGE_FALLING>;
 414                 wakeup-source;
 415         };
 416
 417         eeprom1: eeprom@53 {    /* EEPROM with FEC MAC address */
 418                 compatible = "atmel,24c32";     /* M24C32-D */
 419                 pagesize = <32>;
 420                 reg = <0x53>;
 421         };
 422
 423         ioexp: gpio@74 {
 424                 compatible = "nxp,pca9539";
 425                 reg = <0x74>;
 426                 gpio-controller;
 427                 #gpio-cells = <2>;
 428                 interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
 429                 interrupt-controller;
 430                 #interrupt-cells = <2>;
 431                 pinctrl-names = "default";
 432                 pinctrl-0 = <&pinctrl_ioexp>;
 433                 wakeup-source;
 434
 435                 gpio-line-names =
 436                         "BT_REG_EN", "WL_REG_EN", "VIO_SWITCHED_#EN", "RTC_#INT",
 437                         "ENET_QOS_#RST", "RGB_OSZ_ENABLE", "USB1_ID", "ADC_ALTER_RDY",
 438                         "DHCOM-W", "DHCOM-V", "DHCOM-U", "DHCOM-T",
 439                         "BT_HOST_WAKE", "BT_DEV_WAKE", "", "";
 440         };
 441 };
 442
 443 &i2c4 {
 444         clock-frequency = <100000>;
 445         pinctrl-names = "default", "gpio";
 446         pinctrl-0 = <&pinctrl_i2c4>;
 447         pinctrl-1 = <&pinctrl_i2c4_gpio>;
 448         scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 449         sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 450         status = "okay";
 451 };
 452
 453 &i2c5 { /* HDMI EDID bus */
 454         clock-frequency = <100000>;
 455         pinctrl-names = "default", "gpio";
 456         pinctrl-0 = <&pinctrl_i2c5>;
 457         pinctrl-1 = <&pinctrl_i2c5_gpio>;
 458         scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 459         sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 460         status = "okay";
 461 };
 462
 463 &mipi_dsi {
 464         samsung,burst-clock-frequency = <160000000>;
 465         samsung,esc-clock-frequency = <10000000>;
 466
 467         ports {
 468                 port@1 {
 469                         reg = <1>;
 470
 471                         dsi_out: endpoint {
 472                                 data-lanes = <1 2 3 4>;
 473                                 remote-endpoint = <&tc_bridge_in>;
 474                         };
 475                 };
 476         };
 477 };
 478
 479 &pwm1 {
 480         pinctrl-0 = <&pinctrl_pwm1>;
 481         pinctrl-names = "default";
 482         status = "disabled";
 483 };
 484
 485 &uart1 {
 486         /* CA53 console */
 487         pinctrl-names = "default";
 488         pinctrl-0 = <&pinctrl_uart1>;
 489         status = "okay";
 490         wakeup-source;
 491 };
 492
 493 &uart2 {
 494         /* Bluetooth */
 495         pinctrl-names = "default";
 496         pinctrl-0 = <&pinctrl_uart2>;
 497         uart-has-rtscts;
 498         status = "okay";
 499
 500         /*
 501          * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock,
 502          * which with 16x oversampling yields 5 Mbdps baud base,
 503          * which can be well divided by 5/4 to achieve 4 Mbdps,
 504          * which is exactly the maximum rate supported by muRata
 505          * 2AE bluetooth UART.
 506          */
 507         assigned-clocks = <&clk IMX8MP_CLK_UART2>;
 508         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
 509         assigned-clock-rates = <80000000>;
 510
 511         bluetooth {
 512                 compatible = "cypress,cyw4373a0-bt";
 513                 shutdown-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>;
 514                 max-speed = <4000000>;
 515         };
 516 };
 517
 518 &uart3 {
 519         pinctrl-names = "default";
 520         pinctrl-0 = <&pinctrl_uart3>;
 521         uart-has-rtscts;
 522         status = "okay";
 523 };
 524
 525 &uart4 {
 526         pinctrl-names = "default";
 527         pinctrl-0 = <&pinctrl_uart4>;
 528         status = "okay";
 529 };
 530
 531 &usb3_phy0 {
 532         status = "okay";
 533 };
 534
 535 &usb3_0 {
 536         status = "okay";
 537 };
 538
 539 &usb_dwc3_0 {
 540         dr_mode = "otg";
 541         status = "okay";
 542 };
 543
 544 &usb3_phy1 {
 545         status = "okay";
 546 };
 547
 548 &usb3_1 {
 549         status = "okay";
 550 };
 551
 552 &usb_dwc3_1 {
 553         pinctrl-names = "default";
 554         pinctrl-0 = <&pinctrl_usb1_vbus>;
 555         dr_mode = "host";
 556         status = "okay";
 557 };
 558
 559 /* SDIO WiFi */
 560 &usdhc1 {
 561         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 562         pinctrl-0 = <&pinctrl_usdhc1>;
 563         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 564         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 565         mmc-pwrseq = <&wlan_pwrseq>;
 566         vmmc-supply = <&buck4>;
 567         bus-width = <4>;
 568         non-removable;
 569         cap-power-off-card;
 570         keep-power-in-suspend;
 571         status = "okay";
 572
 573         #address-cells = <1>;
 574         #size-cells = <0>;
 575
 576         brcmf: bcrmf@1 {        /* muRata 2AE */
 577                 reg = <1>;
 578                 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
 579                 /*
 580                  * The "host-wake" interrupt output is by default not
 581                  * connected to the SoC, but can be connected on to
 582                  * SoC pin on the carrier board.
 583                  */
 584         };
 585 };
 586
 587 /* SD slot */
 588 &usdhc2 {
 589         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 590         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 591         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 592         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 593         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 594         vmmc-supply = <&reg_usdhc2_vmmc>;
 595         bus-width = <4>;
 596         status = "okay";
 597 };
 598
 599 /* eMMC */
 600 &usdhc3 {
 601         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 602         pinctrl-0 = <&pinctrl_usdhc3>;
 603         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 604         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 605         vmmc-supply = <&buck4>;
 606         vqmmc-supply = <&buck5>;
 607         bus-width = <8>;
 608         non-removable;
 609         status = "okay";
 610 };
 611
 612 &wdog1 {
 613         pinctrl-names = "default";
 614         pinctrl-0 = <&pinctrl_wdog>;
 615         fsl,ext-reset-output;
 616         status = "okay";
 617 };
 618
 619 &iomuxc {
 620         pinctrl-0 = <&pinctrl_hog_base
 621                      &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
 622                      &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
 623                      &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
 624                      &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
 625                      &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
 626                      &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
 627                      &pinctrl_dhcom_s &pinctrl_dhcom_int>;
 628         pinctrl-names = "default";
 629
 630         pinctrl_dhcom_a: dhcom-a-grp {
 631                 fsl,pins = <
 632                         /* ENET_QOS_EVENT0-OUT */
 633                         MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09             0x2
 634                 >;
 635         };
 636
 637         pinctrl_dhcom_b: dhcom-b-grp {
 638                 fsl,pins = <
 639                         /* ENET_QOS_EVENT0-IN */
 640                         MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08             0x2
 641                 >;
 642         };
 643
 644         pinctrl_dhcom_c: dhcom-c-grp {
 645                 fsl,pins = <
 646                         /* GPIO_C */
 647                         MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02              0x2
 648                 >;
 649         };
 650
 651         pinctrl_dhcom_d: dhcom-d-grp {
 652                 fsl,pins = <
 653                         /* GPIO_D */
 654                         MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27              0x2
 655                 >;
 656         };
 657
 658         pinctrl_dhcom_e: dhcom-e-grp {
 659                 fsl,pins = <
 660                         /* GPIO_E */
 661                         MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22              0x2
 662                 >;
 663         };
 664
 665         pinctrl_dhcom_f: dhcom-f-grp {
 666                 fsl,pins = <
 667                         /* GPIO_F */
 668                         MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23              0x2
 669                 >;
 670         };
 671
 672         pinctrl_dhcom_g: dhcom-g-grp {
 673                 fsl,pins = <
 674                         /* GPIO_G */
 675                         MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00             0x2
 676                 >;
 677         };
 678
 679         pinctrl_dhcom_h: dhcom-h-grp {
 680                 fsl,pins = <
 681                         /* GPIO_H */
 682                         MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11             0x2
 683                 >;
 684         };
 685
 686         pinctrl_dhcom_i: dhcom-i-grp {
 687                 fsl,pins = <
 688                         /* CSI1_SYNC */
 689                         MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05             0x2
 690                 >;
 691         };
 692
 693         pinctrl_dhcom_j: dhcom-j-grp {
 694                 fsl,pins = <
 695                         /* CSIx_#RST */
 696                         MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06             0x2
 697                 >;
 698         };
 699
 700         pinctrl_dhcom_k: dhcom-k-grp {
 701                 fsl,pins = <
 702                         /* CSIx_PWDN */
 703                         MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11             0x2
 704                 >;
 705         };
 706
 707         pinctrl_dhcom_l: dhcom-l-grp {
 708                 fsl,pins = <
 709                         /* CSI2_SYNC */
 710                         MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07             0x2
 711                 >;
 712         };
 713
 714         pinctrl_dhcom_m: dhcom-m-grp {
 715                 fsl,pins = <
 716                         /* CSIx_MCLK */
 717                         MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05          0x2
 718                 >;
 719         };
 720
 721         pinctrl_dhcom_n: dhcom-n-grp {
 722                 fsl,pins = <
 723                         /* CSI2_D3- */
 724                         MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09              0x2
 725                 >;
 726         };
 727
 728         pinctrl_dhcom_o: dhcom-o-grp {
 729                 fsl,pins = <
 730                         /* CSI2_D3+ */
 731                         MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08              0x2
 732                 >;
 733         };
 734
 735         pinctrl_dhcom_p: dhcom-p-grp {
 736                 fsl,pins = <
 737                         /* CSI2_D2- */
 738                         MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10            0x2
 739                 >;
 740         };
 741
 742         pinctrl_dhcom_q: dhcom-q-grp {
 743                 fsl,pins = <
 744                         /* CSI2_D2+ */
 745                         MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13             0x2
 746                 >;
 747         };
 748
 749         pinctrl_dhcom_r: dhcom-r-grp {
 750                 fsl,pins = <
 751                         /* CSI2_D1- */
 752                         MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12             0x2
 753                 >;
 754         };
 755
 756         pinctrl_dhcom_s: dhcom-s-grp {
 757                 fsl,pins = <
 758                         /* CSI2_D1+ */
 759                         MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10             0x2
 760                 >;
 761         };
 762
 763         pinctrl_dhcom_int: dhcom-int-grp {
 764                 fsl,pins = <
 765                         /* INT_HIGHEST_PRIO */
 766                         MX8MP_IOMUXC_SD2_WP__GPIO2_IO20                 0x2
 767                 >;
 768         };
 769
 770         pinctrl_hog_base: dhcom-hog-base-grp {
 771                 fsl,pins = <
 772                         /* GPIOs for memory coding */
 773                         MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22              0x40000080
 774                         MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23              0x40000080
 775                         MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24              0x40000080
 776                         /* GPIOs for hardware coding */
 777                         MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14               0x40000080
 778                         MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19              0x40000080
 779                         MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25              0x40000080
 780                 >;
 781         };
 782
 783         pinctrl_ecspi1: dhcom-ecspi1-grp {
 784                 fsl,pins = <
 785                         MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK              0x44
 786                         MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI              0x44
 787                         MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO              0x44
 788                         MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17               0x40
 789                 >;
 790         };
 791
 792         pinctrl_ecspi2: dhcom-ecspi2-grp {
 793                 fsl,pins = <
 794                         MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK           0x44
 795                         MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI           0x44
 796                         MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO           0x44
 797                         MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13             0x40
 798                 >;
 799         };
 800
 801         pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp {      /* RGMII */
 802                 fsl,pins = <
 803                         MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC             0x3
 804                         MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO           0x3
 805                         MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
 806                         MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK       0x1f
 807                         MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0       0x1f
 808                         MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1       0x1f
 809                         MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2       0x1f
 810                         MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3       0x1f
 811                         MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK       0x91
 812                         MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
 813                         MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0       0x91
 814                         MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1       0x91
 815                         MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2       0x91
 816                         MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3       0x91
 817                 >;
 818         };
 819
 820         pinctrl_eqos_rmii: dhcom-eqos-rmii-grp {        /* RMII */
 821                 fsl,pins = <
 822                         MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC             0x3
 823                         MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO           0x3
 824                         MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
 825                         MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0       0x1f
 826                         MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1       0x1f
 827                         MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER           0x1f
 828                         MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
 829                         MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0       0x91
 830                         MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1       0x91
 831                         /* Clock */
 832                         MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK      0x4000001f
 833                 >;
 834         };
 835
 836         pinctrl_ethphy0: dhcom-ethphy0-grp {
 837                 fsl,pins = <
 838                         /* ENET_QOS_#INT Interrupt */
 839                         MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19              0x22
 840                 >;
 841         };
 842
 843         pinctrl_ethphy1: dhcom-ethphy1-grp {
 844                 fsl,pins = <
 845                         /* ENET1_#RST Reset */
 846                         MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02              0x11
 847                         /* ENET1_#INT Interrupt */
 848                         MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03              0x11
 849                 >;
 850         };
 851
 852         pinctrl_fec_rgmii: dhcom-fec-rgmii-grp {        /* RGMII */
 853                 fsl,pins = <
 854                         MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK            0x1f
 855                         MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x3
 856                         MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x3
 857                         MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x91
 858                         MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x91
 859                         MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2         0x91
 860                         MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3         0x91
 861                         MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC          0x91
 862                         MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x91
 863                         MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x1f
 864                         MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x1f
 865                         MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2         0x1f
 866                         MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3         0x1f
 867                         MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x1f
 868                         MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC         0x1f
 869                         MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER             0x1f
 870                 >;
 871         };
 872
 873         pinctrl_fec_rmii: dhcom-fec-rmii-grp {  /* RMII */
 874                 fsl,pins = <
 875                         MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x3
 876                         MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x3
 877                         MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x91
 878                         MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x91
 879                         MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x91
 880                         MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER             0x91
 881                         MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x1f
 882                         MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x1f
 883                         MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x1f
 884                         /* Clock */
 885                         MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK            0x4000001f
 886                 >;
 887         };
 888
 889         pinctrl_flexcan1: dhcom-flexcan1-grp {
 890                 fsl,pins = <
 891                         MX8MP_IOMUXC_SPDIF_RX__CAN1_RX                  0x154
 892                         MX8MP_IOMUXC_SPDIF_TX__CAN1_TX                  0x154
 893                 >;
 894         };
 895
 896         pinctrl_flexcan2: dhcom-flexcan2-grp {
 897                 fsl,pins = <
 898                         MX8MP_IOMUXC_UART3_RXD__CAN2_TX                 0x154
 899                         MX8MP_IOMUXC_UART3_TXD__CAN2_RX                 0x154
 900                 >;
 901         };
 902
 903         pinctrl_flexspi: dhcom-flexspi-grp {
 904                 fsl,pins = <
 905                         MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK           0x1c2
 906                         MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B        0x82
 907                         MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00      0x82
 908                         MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01      0x82
 909                         MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02      0x82
 910                         MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03      0x82
 911                 >;
 912         };
 913
 914         pinctrl_hdmi: dhcom-hdmi-grp {
 915                 fsl,pins = <
 916                         MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC         0x154
 917                         MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD         0x154
 918                 >;
 919         };
 920
 921         pinctrl_i2c3: dhcom-i2c3-grp {
 922                 fsl,pins = <
 923                         MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL                 0x40000084
 924                         MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA                 0x40000084
 925                 >;
 926         };
 927
 928         pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {
 929                 fsl,pins = <
 930                         MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18               0x84
 931                         MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19               0x84
 932                 >;
 933         };
 934
 935         pinctrl_i2c4: dhcom-i2c4-grp {
 936                 fsl,pins = <
 937                         MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL                 0x40000084
 938                         MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA                 0x40000084
 939                 >;
 940         };
 941
 942         pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {
 943                 fsl,pins = <
 944                         MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20               0x84
 945                         MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21               0x84
 946                 >;
 947         };
 948
 949         pinctrl_i2c5: dhcom-i2c5-grp {
 950                 fsl,pins = <
 951                         MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL             0x40000084
 952                         MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA             0x40000084
 953                 >;
 954         };
 955
 956         pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {
 957                 fsl,pins = <
 958                         MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26           0x84
 959                         MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27           0x84
 960                 >;
 961         };
 962
 963         pinctrl_ioexp: dhcom-ioexp-grp {
 964                 fsl,pins = <
 965                         /* #GPIO_EXP_INT */
 966                         MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20               0x22
 967                 >;
 968         };
 969
 970         pinctrl_pmic: dhcom-pmic-grp {
 971                 fsl,pins = <
 972                         /* PMIC_nINT */
 973                         MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03             0x40000090
 974                 >;
 975         };
 976
 977         pinctrl_pwm1: dhcom-pwm1-grp {
 978                 fsl,pins = <
 979                         MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT               0x6
 980                 >;
 981         };
 982
 983         pinctrl_tc9595: dhcom-tc9595-grp {
 984                 fsl,pins = <
 985                         /* RESET_DSIBRIDGE */
 986                         MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01               0x40000146
 987                         /* DSI-CONV_INT Interrupt */
 988                         MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21              0x141
 989                 >;
 990         };
 991
 992         pinctrl_sai3: dhcom-sai3-grp {
 993                 fsl,pins = <
 994                         MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC   0xd6
 995                         MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK    0xd6
 996                         MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00  0xd6
 997                         MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00  0xd6
 998                 >;
 999         };
1000
1001         pinctrl_touch: dhcom-touch-grp {
1002                 fsl,pins = <
1003                         /* #TOUCH_INT */
1004                         MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00              0x40000080
1005                 >;
1006         };
1007
1008         pinctrl_uart1: dhcom-uart1-grp {
1009                 fsl,pins = <
1010                         /* Console UART */
1011                         MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX             0x49
1012                         MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX            0x49
1013                         MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS           0x49
1014                         MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS           0x49
1015                 >;
1016         };
1017
1018         pinctrl_uart2: dhcom-uart2-grp {
1019                 fsl,pins = <
1020                         /* Bluetooth UART */
1021                         MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX            0x49
1022                         MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX            0x49
1023                         MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS           0x49
1024                         MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS           0x49
1025                 >;
1026         };
1027
1028         pinctrl_uart3: dhcom-uart3-grp {
1029                 fsl,pins = <
1030                         MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX          0x49
1031                         MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX          0x49
1032                         MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS          0x49
1033                         MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS         0x49
1034                 >;
1035         };
1036
1037         pinctrl_uart4: dhcom-uart4-grp {
1038                 fsl,pins = <
1039                         MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX            0x49
1040                         MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX            0x49
1041                 >;
1042         };
1043
1044         pinctrl_usb1_vbus: dhcom-usb1-grp {
1045                 fsl,pins = <
1046                         MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR           0x6
1047                         MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC            0x80
1048                 >;
1049         };
1050
1051         pinctrl_usdhc1: dhcom-usdhc1-grp {
1052                 fsl,pins = <
1053                         MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK                0x190
1054                         MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD                0x1d0
1055                         MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0            0x1d0
1056                         MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1            0x1d0
1057                         MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2            0x1d0
1058                         MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3            0x1d0
1059                 >;
1060         };
1061
1062         pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
1063                 fsl,pins = <
1064                         MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK                0x194
1065                         MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD                0x1d4
1066                         MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0            0x1d4
1067                         MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1            0x1d4
1068                         MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2            0x1d4
1069                         MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3            0x1d4
1070                 >;
1071         };
1072
1073         pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
1074                 fsl,pins = <
1075                         MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK                0x196
1076                         MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD                0x1d6
1077                         MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0            0x1d6
1078                         MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1            0x1d6
1079                         MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2            0x1d6
1080                         MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3            0x1d6
1081                 >;
1082         };
1083
1084         pinctrl_usdhc2: dhcom-usdhc2-grp {
1085                 fsl,pins = <
1086                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                0x190
1087                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                0x1d0
1088                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0            0x1d0
1089                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1            0x1d0
1090                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2            0x1d0
1091                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3            0x1d0
1092                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT         0xc1
1093                 >;
1094         };
1095
1096         pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
1097                 fsl,pins = <
1098                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                0x194
1099                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                0x1d4
1100                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0            0x1d4
1101                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1            0x1d4
1102                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2            0x1d4
1103                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3            0x1d4
1104                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT         0xc1
1105                 >;
1106         };
1107
1108         pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {
1109                 fsl,pins = <
1110                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                0x196
1111                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                0x1d6
1112                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0            0x1d6
1113                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1            0x1d6
1114                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2            0x1d6
1115                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3            0x1d6
1116                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT         0xc1
1117                 >;
1118         };
1119
1120         pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {
1121                 fsl,pins = <
1122                         MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19            0x20
1123                 >;
1124         };
1125
1126         pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {
1127                 fsl,pins = <
1128                         MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12               0x40000080
1129                 >;
1130         };
1131
1132         pinctrl_usdhc3: dhcom-usdhc3-grp {
1133                 fsl,pins = <
1134                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK              0x190
1135                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD              0x1d0
1136                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0          0x1d0
1137                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1          0x1d0
1138                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2          0x1d0
1139                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3          0x1d0
1140                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4            0x1d0
1141                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5           0x1d0
1142                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6           0x1d0
1143                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7             0x1d0
1144                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE          0x190
1145                         MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B       0x141
1146                 >;
1147         };
1148
1149         pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {
1150                 fsl,pins = <
1151                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK              0x194
1152                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD              0x1d4
1153                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0          0x1d4
1154                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1          0x1d4
1155                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2          0x1d4
1156                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3          0x1d4
1157                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4            0x1d4
1158                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5           0x1d4
1159                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6           0x1d4
1160                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7             0x1d4
1161                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE          0x194
1162                         MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B       0x141
1163                 >;
1164         };
1165
1166         pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {
1167                 fsl,pins = <
1168                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK              0x196
1169                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD              0x1d6
1170                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0          0x1d6
1171                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1          0x1d6
1172                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2          0x1d6
1173                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3          0x1d6
1174                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4            0x1d6
1175                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5           0x1d6
1176                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6           0x1d6
1177                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7             0x1d6
1178                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE          0x196
1179                         MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B       0x141
1180                 >;
1181         };
1182
1183         pinctrl_wdog: dhcom-wdog-grp {
1184                 fsl,pins = <
1185                         MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B           0xc6
1186                 >;
1187         };
1188 };