1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de>
9 #include "imx8mp-debix-som-a.dtsi"
12 model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08";
13 compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a",
25 reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 {
26 compatible = "regulator-fixed";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-name = "BB_VDD3V3";
30 /* Required timings for ethernet phy's */
31 startup-delay-us = <50000>;
32 off-on-delay-us = <110000>;
33 gpio = <&expander0 10 GPIO_ACTIVE_HIGH>;
37 reg_baseboard_vdd5v0: regulator-baseboard-vdd5v0 {
38 compatible = "regulator-fixed";
39 regulator-min-microvolt = <5000000>;
40 regulator-max-microvolt = <5000000>;
41 regulator-name = "BB_VDD5V";
42 gpio = <&expander0 9 GPIO_ACTIVE_HIGH>;
46 regulator-som-vdd1v8 {
47 compatible = "regulator-fixed";
48 regulator-min-microvolt = <1800000>;
49 regulator-max-microvolt = <1800000>;
50 regulator-name = "SOM_VDD1V8_SW";
51 gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
56 regulator-som-vdd3v3 {
57 compatible = "regulator-fixed";
58 regulator-min-microvolt = <3300000>;
59 regulator-max-microvolt = <3300000>;
60 regulator-name = "SOM_VDD3V3_SW";
61 gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
66 regulator-vbus-usb20 {
67 compatible = "regulator-fixed";
68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>;
70 regulator-name = "USB20_5V";
71 gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
74 vin-supply = <®_baseboard_vdd5v0>;
77 regulator-vbus-usb30 {
78 compatible = "regulator-fixed";
79 regulator-min-microvolt = <5000000>;
80 regulator-max-microvolt = <5000000>;
81 regulator-name = "USB30_5V";
82 gpio = <&expander1 12 GPIO_ACTIVE_HIGH>;
85 vin-supply = <®_baseboard_vdd5v0>;
88 reg_vdd5v0: regulator-vdd5v0 {
89 compatible = "regulator-fixed";
90 regulator-min-microvolt = <5000000>;
91 regulator-max-microvolt = <5000000>;
92 regulator-name = "VDD_5V";
93 gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_eqos>;
101 nvmem-cells = <ðmac1>;
102 nvmem-cell-names = "mac-address";
103 phy-supply = <®_baseboard_vdd3v3>;
104 phy-handle = <ðphy0>;
105 phy-mode = "rgmii-id";
109 compatible = "snps,dwmac-mdio";
110 #address-cells = <1>;
113 ethphy0: ethernet-phy@1 {
114 compatible = "ethernet-phy-ieee802.3-c22";
116 reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
117 reset-assert-us = <20000>;
118 reset-deassert-us = <150000>;
120 realtek,clkout-disable;
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_fec>;
128 nvmem-cells = <ðmac2>;
129 nvmem-cell-names = "mac-address";
130 phy-supply = <®_baseboard_vdd3v3>;
131 phy-handle = <ðphy1>;
132 phy-mode = "rgmii-id";
137 #address-cells = <1>;
140 ethphy1: ethernet-phy@1 {
141 compatible = "ethernet-phy-ieee802.3-c22";
143 reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
144 reset-assert-us = <20000>;
145 reset-deassert-us = <150000>;
147 realtek,clkout-disable;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_flexcan1>;
155 xceiver-supply = <®_vdd5v0>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_flexcan2>;
162 xceiver-supply = <®_vdd5v0>;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_flexspi0>;
172 compatible = "jedec,spi-nor";
174 spi-max-frequency = <80000000>;
175 spi-tx-bus-width = <1>;
176 spi-rx-bus-width = <4>;
177 #address-cells = <1>;
184 compatible = "nxp,pca9535";
187 #gpio-cells = <0x02>;
191 compatible = "nxp,pca9535";
194 #gpio-cells = <0x02>;
197 * Since USB1 is bound to peripheral mode we need to ensure
198 * that VBUS is turned off.
202 gpios = <13 GPIO_ACTIVE_HIGH>;
204 line-name = "USB30_OTG_EN";
209 compatible = "haoyu,hym8563";
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_rtc>;
213 interrupt-parent = <&gpio4>;
214 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
219 compatible = "atmel,24c02";
222 #address-cells = <1>;
225 /* MACs stored in ASCII */
226 ethmac1: mac-address@0 {
230 ethmac2: mac-address@c {
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_uart2>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_uart3>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_uart4>;
268 dr_mode = "peripheral";
274 #address-cells = <1>;
278 /* 2.x hub on port 1 */
280 compatible = "usb5e3,610";
282 reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>;
283 vdd-supply = <®_vdd5v0>;
284 peer-hub = <&usb_hub_3_x>;
287 /* 3.x hub on port 2 */
289 compatible = "usb5e3,620";
291 reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>;
292 vdd-supply = <®_vdd5v0>;
293 peer-hub = <&usb_hub_2_x>;
307 pinctrl-names = "default", "state_100mhz", "state_200mhz";
308 pinctrl-0 = <&pinctrl_usdhc2>;
309 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
310 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
311 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
312 assigned-clock-rates = <400000000>;
313 vmmc-supply = <®_usdhc2_vmmc>;
322 pinctrl_eqos: eqosgrp {
324 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
325 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
326 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
327 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
328 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
329 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
330 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
331 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
332 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
333 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
334 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
335 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
336 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
337 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
339 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f
340 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19
344 pinctrl_fec: fecgrp {
346 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
347 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
348 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
349 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
350 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
351 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
352 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
353 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
354 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
355 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
356 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
357 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
358 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
359 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
360 MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f
361 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19
365 pinctrl_flexcan1: flexcan1grp {
367 MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
368 MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
372 pinctrl_flexcan2: flexcan2grp {
374 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
375 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
379 pinctrl_flexspi0: flexspi0grp {
381 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
382 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
383 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
384 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
385 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
386 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
390 pinctrl_i2c1: i2c1grp {
392 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
393 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
397 pinctrl_i2c4: i2c4grp {
399 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
400 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
404 pinctrl_rtc: rtcgrp {
406 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x140
410 pinctrl_pmic: pmicgrp {
412 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
416 pinctrl_uart2: uart2grp {
418 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f
419 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f
423 pinctrl_uart3: uart3grp {
425 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
426 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
430 pinctrl_uart4: uart4grp {
432 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
433 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
437 pinctrl_usdhc2: usdhc2grp {
439 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
440 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
441 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
442 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
443 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
444 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
445 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
449 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
451 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
452 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
453 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
454 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
455 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
456 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
457 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
461 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
463 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
464 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
465 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
466 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
467 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
468 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
469 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1