arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  * Copyright 2022 Ideas on Board Oy
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/leds/common.h>
  11 #include <dt-bindings/usb/pd.h>
  12
  13 #include "imx8mp.dtsi"
  14
  15 / {
  16         model = "Polyhex Debix Model A i.MX8MPlus board";
  17         compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp";
  18
  19         chosen {
  20                 stdout-path = &uart2;
  21         };
  22
  23         leds {
  24                 compatible = "gpio-leds";
  25                 pinctrl-names = "default";
  26                 pinctrl-0 = <&pinctrl_gpio_led>;
  27
  28                 led-0 {
  29                         function = LED_FUNCTION_POWER;
  30                         color = <LED_COLOR_ID_RED>;
  31                         gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  32                         default-state = "on";
  33                 };
  34         };
  35
  36         reg_usdhc2_vmmc: regulator-usdhc2 {
  37                 compatible = "regulator-fixed";
  38                 pinctrl-names = "default";
  39                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  40                 regulator-name = "VSD_3V3";
  41                 regulator-min-microvolt = <3300000>;
  42                 regulator-max-microvolt = <3300000>;
  43                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  44                 enable-active-high;
  45         };
  46
  47         reg_usb_hub: regulator-usb-hub {
  48                 compatible = "regulator-fixed";
  49                 pinctrl-names = "default";
  50                 pinctrl-0 = <&pinctrl_reg_usb_hub>;
  51                 regulator-name = "USB_HUB";
  52                 regulator-min-microvolt = <5000000>;
  53                 regulator-max-microvolt = <5000000>;
  54                 gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
  55                 enable-active-high;
  56         };
  57 };
  58
  59 &A53_0 {
  60         cpu-supply = <&buck2>;
  61 };
  62
  63 &A53_1 {
  64         cpu-supply = <&buck2>;
  65 };
  66
  67 &A53_2 {
  68         cpu-supply = <&buck2>;
  69 };
  70
  71 &A53_3 {
  72         cpu-supply = <&buck2>;
  73 };
  74
  75 &eqos {
  76         pinctrl-names = "default";
  77         pinctrl-0 = <&pinctrl_eqos>;
  78         phy-connection-type = "rgmii-id";
  79         phy-handle = <&ethphy0>;
  80         status = "okay";
  81
  82         mdio {
  83                 compatible = "snps,dwmac-mdio";
  84                 #address-cells = <1>;
  85                 #size-cells = <0>;
  86
  87                 ethphy0: ethernet-phy@0 { /* RTL8211E */
  88                         compatible = "ethernet-phy-ieee802.3-c22";
  89                         reg = <0>;
  90                         reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
  91                         reset-assert-us = <20>;
  92                         reset-deassert-us = <200000>;
  93                 };
  94         };
  95 };
  96
  97 &i2c1 {
  98         clock-frequency = <400000>;
  99         pinctrl-names = "default";
 100         pinctrl-0 = <&pinctrl_i2c1>;
 101         status = "okay";
 102
 103         pmic@25 {
 104                 compatible = "nxp,pca9450c";
 105                 reg = <0x25>;
 106                 pinctrl-names = "default";
 107                 pinctrl-0 = <&pinctrl_pmic>;
 108                 interrupt-parent = <&gpio1>;
 109                 interrupts = <3 IRQ_TYPE_EDGE_RISING>;
 110
 111                 regulators {
 112                         buck1: BUCK1 {
 113                                 regulator-name = "BUCK1";
 114                                 regulator-min-microvolt = <600000>;
 115                                 regulator-max-microvolt = <2187500>;
 116                                 regulator-boot-on;
 117                                 regulator-always-on;
 118                                 regulator-ramp-delay = <3125>;
 119                         };
 120
 121                         buck2: BUCK2 {
 122                                 regulator-name = "BUCK2";
 123                                 regulator-min-microvolt = <600000>;
 124                                 regulator-max-microvolt = <2187500>;
 125                                 regulator-boot-on;
 126                                 regulator-always-on;
 127                                 regulator-ramp-delay = <3125>;
 128                                 nxp,dvs-run-voltage = <950000>;
 129                                 nxp,dvs-standby-voltage = <850000>;
 130                         };
 131
 132                         buck4: BUCK4 {
 133                                 regulator-name = "BUCK4";
 134                                 regulator-min-microvolt = <600000>;
 135                                 regulator-max-microvolt = <3400000>;
 136                                 regulator-boot-on;
 137                                 regulator-always-on;
 138                         };
 139
 140                         buck5: BUCK5 {
 141                                 regulator-name = "BUCK5";
 142                                 regulator-min-microvolt = <600000>;
 143                                 regulator-max-microvolt = <3400000>;
 144                                 regulator-boot-on;
 145                                 regulator-always-on;
 146                         };
 147
 148                         buck6: BUCK6 {
 149                                 regulator-name = "BUCK6";
 150                                 regulator-min-microvolt = <600000>;
 151                                 regulator-max-microvolt = <3400000>;
 152                                 regulator-boot-on;
 153                                 regulator-always-on;
 154                         };
 155
 156                         ldo1: LDO1 {
 157                                 regulator-name = "LDO1";
 158                                 regulator-min-microvolt = <1600000>;
 159                                 regulator-max-microvolt = <3300000>;
 160                                 regulator-boot-on;
 161                                 regulator-always-on;
 162                         };
 163
 164                         ldo2: LDO2 {
 165                                 regulator-name = "LDO2";
 166                                 regulator-min-microvolt = <800000>;
 167                                 regulator-max-microvolt = <1150000>;
 168                                 regulator-boot-on;
 169                                 regulator-always-on;
 170                         };
 171
 172                         ldo3: LDO3 {
 173                                 regulator-name = "LDO3";
 174                                 regulator-min-microvolt = <800000>;
 175                                 regulator-max-microvolt = <3300000>;
 176                                 regulator-boot-on;
 177                                 regulator-always-on;
 178                         };
 179
 180                         ldo4: LDO4 {
 181                                 regulator-name = "LDO4";
 182                                 regulator-min-microvolt = <800000>;
 183                                 regulator-max-microvolt = <3300000>;
 184                                 regulator-boot-on;
 185                                 regulator-always-on;
 186                         };
 187
 188                         ldo5: LDO5 {
 189                                 regulator-name = "LDO5";
 190                                 regulator-min-microvolt = <1800000>;
 191                                 regulator-max-microvolt = <3300000>;
 192                                 regulator-boot-on;
 193                                 regulator-always-on;
 194                         };
 195                 };
 196         };
 197 };
 198
 199 &i2c2 {
 200         clock-frequency = <100000>;
 201         pinctrl-names = "default";
 202         pinctrl-0 = <&pinctrl_i2c2>;
 203         status = "okay";
 204 };
 205
 206 &i2c3 {
 207         clock-frequency = <400000>;
 208         pinctrl-names = "default";
 209         pinctrl-0 = <&pinctrl_i2c3>;
 210         status = "okay";
 211 };
 212
 213 &i2c4 {
 214         clock-frequency = <100000>;
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_i2c4>;
 217         status = "okay";
 218
 219         eeprom@50 {
 220                 compatible = "atmel,24c02";
 221                 reg = <0x50>;
 222                 pagesize = <16>;
 223         };
 224
 225         rtc@51 {
 226                 compatible = "haoyu,hym8563";
 227                 reg = <0x51>;
 228                 #clock-cells = <0>;
 229                 clock-output-names = "xin32k";
 230                 interrupt-parent = <&gpio2>;
 231                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 232                 pinctrl-names = "default";
 233                 pinctrl-0 = <&pinctrl_rtc_int>;
 234         };
 235 };
 236
 237 &i2c6 {
 238         clock-frequency = <400000>;
 239         pinctrl-names = "default";
 240         pinctrl-0 = <&pinctrl_i2c6>;
 241         status = "okay";
 242 };
 243
 244 &snvs_pwrkey {
 245         status = "okay";
 246 };
 247
 248 &uart2 {
 249         /* console */
 250         pinctrl-names = "default";
 251         pinctrl-0 = <&pinctrl_uart2>;
 252         status = "okay";
 253 };
 254
 255 &uart3 {
 256         pinctrl-names = "default";
 257         pinctrl-0 = <&pinctrl_uart3>;
 258         status = "okay";
 259 };
 260
 261 &uart4 {
 262         pinctrl-names = "default";
 263         pinctrl-0 = <&pinctrl_uart4>;
 264         status = "okay";
 265 };
 266
 267 &usb3_phy1 {
 268         status = "okay";
 269 };
 270
 271 &usb3_1 {
 272         status = "okay";
 273 };
 274
 275 &usb_dwc3_1 {
 276         #address-cells = <1>;
 277         #size-cells = <0>;
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_usb1>;
 280         dr_mode = "host";
 281         status = "okay";
 282
 283         /* 2.x hub on port 1 */
 284         usb_hub_2_x: hub@1 {
 285                 compatible = "usbbda,5411";
 286                 reg = <1>;
 287                 vdd-supply = <&reg_usb_hub>;
 288                 peer-hub = <&usb_hub_3_x>;
 289         };
 290
 291         /* 3.x hub on port 2 */
 292         usb_hub_3_x: hub@2 {
 293                 compatible = "usbbda,411";
 294                 reg = <2>;
 295                 vdd-supply = <&reg_usb_hub>;
 296                 peer-hub = <&usb_hub_2_x>;
 297         };
 298 };
 299
 300 /* SD Card */
 301 &usdhc2 {
 302         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 303         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 304         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 305         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 306         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 307         vmmc-supply = <&reg_usdhc2_vmmc>;
 308         bus-width = <4>;
 309         status = "okay";
 310 };
 311
 312 /* eMMC */
 313 &usdhc3 {
 314         assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
 315         assigned-clock-rates = <400000000>;
 316         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 317         pinctrl-0 = <&pinctrl_usdhc3>;
 318         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 319         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 320         bus-width = <8>;
 321         non-removable;
 322         status = "okay";
 323 };
 324
 325 &wdog1 {
 326         pinctrl-names = "default";
 327         pinctrl-0 = <&pinctrl_wdog>;
 328         fsl,ext-reset-output;
 329         status = "okay";
 330 };
 331
 332 &iomuxc {
 333         pinctrl_eqos: eqosgrp {
 334                 fsl,pins = <
 335                         MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                             0x3
 336                         MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                           0x3
 337                         MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0                       0x91
 338                         MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1                       0x91
 339                         MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2                       0x91
 340                         MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3                       0x91
 341                         MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK       0x91
 342                         MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL                 0x91
 343                         MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0                       0x1f
 344                         MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1                       0x1f
 345                         MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2                       0x1f
 346                         MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3                       0x1f
 347                         MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL                 0x1f
 348                         MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK       0x1f
 349                         MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN                    0x1f
 350                         MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT                    0x1f
 351                         MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18                              0x19
 352                 >;
 353         };
 354
 355         pinctrl_gpio_led: gpioledgrp {
 356                 fsl,pins = <
 357                         MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16                           0x19
 358                 >;
 359         };
 360
 361         pinctrl_i2c1: i2c1grp {
 362                 fsl,pins = <
 363                         MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL                                 0x400001c2
 364                         MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA                                 0x400001c2
 365                 >;
 366         };
 367
 368         pinctrl_i2c2: i2c2grp {
 369                 fsl,pins = <
 370                         MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL                                 0x400001c2
 371                         MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA                                 0x400001c2
 372                 >;
 373         };
 374
 375         pinctrl_i2c3: i2c3grp {
 376                 fsl,pins = <
 377                         MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL                                 0x400001c2
 378                         MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA                                 0x400001c2
 379                 >;
 380         };
 381
 382         pinctrl_i2c4: i2c4grp {
 383                 fsl,pins = <
 384                         MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL                                 0x400001c3
 385                         MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA                                 0x400001c3
 386                 >;
 387         };
 388
 389         pinctrl_i2c6: i2c6grp {
 390                 fsl,pins = <
 391                         MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL                                0x400001c3
 392                         MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA                                 0x400001c3
 393                 >;
 394         };
 395
 396         pinctrl_pmic: pmicirqgrp {
 397                 fsl,pins = <
 398                         MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03                             0x41
 399                 >;
 400         };
 401
 402         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 403                 fsl,pins = <
 404                         MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19                            0x41
 405                 >;
 406         };
 407
 408         pinctrl_reg_usb_hub: regusbhubgrp {
 409                 fsl,pins = <
 410                         MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26                              0x19
 411                 >;
 412         };
 413
 414         pinctrl_rtc_int: rtcintgrp {
 415                 fsl,pins = <
 416                         MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11                             0x140
 417                 >;
 418         };
 419
 420         pinctrl_uart2: uart2grp {
 421                 fsl,pins = <
 422                         MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX                            0x14f
 423                         MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX                            0x14f
 424                 >;
 425         };
 426
 427         pinctrl_uart3: uart3grp {
 428                 fsl,pins = <
 429                         MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX                            0x49
 430                         MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX                            0x49
 431                 >;
 432         };
 433
 434         pinctrl_uart4: uart4grp {
 435                 fsl,pins = <
 436                         MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX                            0x49
 437                         MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX                            0x49
 438                 >;
 439         };
 440
 441         pinctrl_usb1: usb1grp {
 442                 fsl,pins = <
 443                         MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR                           0x10
 444                 >;
 445         };
 446
 447         pinctrl_usdhc2: usdhc2grp {
 448                 fsl,pins = <
 449                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                                0x190
 450                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                                0x1d0
 451                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                            0x1d0
 452                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                            0x1d0
 453                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                            0x1d0
 454                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                            0x1d0
 455                 >;
 456         };
 457
 458         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 459                 fsl,pins = <
 460                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                                0x194
 461                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                                0x1d4
 462                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                            0x1d4
 463                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                            0x1d4
 464                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                            0x1d4
 465                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                            0x1d4
 466                 >;
 467         };
 468
 469         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 470                 fsl,pins = <
 471                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                                0x196
 472                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                                0x1d6
 473                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                            0x1d6
 474                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                            0x1d6
 475                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                            0x1d6
 476                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                            0x1d6
 477                 >;
 478         };
 479
 480         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 481                 fsl,pins = <
 482                         MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12                               0x1c4
 483                 >;
 484         };
 485
 486         pinctrl_usdhc3: usdhc3grp {
 487                 fsl,pins = <
 488                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK                              0x190
 489                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD                              0x1d0
 490                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0                          0x1d0
 491                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1                          0x1d0
 492                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2                          0x1d0
 493                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3                          0x1d0
 494                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4                            0x1d0
 495                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5                           0x1d0
 496                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6                           0x1d0
 497                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7                             0x1d0
 498                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE                          0x190
 499                 >;
 500         };
 501
 502         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 503                 fsl,pins = <
 504                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK                              0x194
 505                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD                              0x1d4
 506                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0                          0x1d4
 507                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1                          0x1d4
 508                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2                          0x1d4
 509                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3                          0x1d4
 510                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4                            0x1d4
 511                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5                           0x1d4
 512                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6                           0x1d4
 513                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7                             0x1d4
 514                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE                          0x194
 515                 >;
 516         };
 517
 518         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 519                 fsl,pins = <
 520                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK                              0x196
 521                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD                              0x1d6
 522                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0                          0x1d6
 523                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1                          0x1d6
 524                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2                          0x1d6
 525                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3                          0x1d6
 526                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4                            0x1d6
 527                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5                           0x1d6
 528                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6                           0x1d6
 529                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7                             0x1d6
 530                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE                          0x196
 531                 >;
 532         };
 533
 534         pinctrl_wdog: wdoggrp {
 535                 fsl,pins = <
 536                         MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B                           0xc6
 537                 >;
 538         };
 539 };