arch/arm64/boot/dts/freescale/imx8mn.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8mn-clock.h>
   7 #include <dt-bindings/power/imx8mn-power.h>
   8 #include <dt-bindings/reset/imx8mq-reset.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/input/input.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 #include "imx8mn-pinfunc.h"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 ethernet0 = &fec1;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 mmc0 = &usdhc1;
  33                 mmc1 = &usdhc2;
  34                 mmc2 = &usdhc3;
  35                 serial0 = &uart1;
  36                 serial1 = &uart2;
  37                 serial2 = &uart3;
  38                 serial3 = &uart4;
  39                 spi0 = &ecspi1;
  40                 spi1 = &ecspi2;
  41                 spi2 = &ecspi3;
  42         };
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 idle-states {
  49                         entry-method = "psci";
  50
  51                         cpu_pd_wait: cpu-pd-wait {
  52                                 compatible = "arm,idle-state";
  53                                 arm,psci-suspend-param = <0x0010033>;
  54                                 local-timer-stop;
  55                                 entry-latency-us = <1000>;
  56                                 exit-latency-us = <700>;
  57                                 min-residency-us = <2700>;
  58                         };
  59                 };
  60
  61                 A53_0: cpu@0 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a53";
  64                         reg = <0x0>;
  65                         clock-latency = <61036>;
  66                         clocks = <&clk IMX8MN_CLK_ARM>;
  67                         enable-method = "psci";
  68                         i-cache-size = <0x8000>;
  69                         i-cache-line-size = <64>;
  70                         i-cache-sets = <256>;
  71                         d-cache-size = <0x8000>;
  72                         d-cache-line-size = <64>;
  73                         d-cache-sets = <128>;
  74                         next-level-cache = <&A53_L2>;
  75                         operating-points-v2 = <&a53_opp_table>;
  76                         nvmem-cells = <&cpu_speed_grade>;
  77                         nvmem-cell-names = "speed_grade";
  78                         cpu-idle-states = <&cpu_pd_wait>;
  79                         #cooling-cells = <2>;
  80                 };
  81
  82                 A53_1: cpu@1 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53";
  85                         reg = <0x1>;
  86                         clock-latency = <61036>;
  87                         clocks = <&clk IMX8MN_CLK_ARM>;
  88                         enable-method = "psci";
  89                         i-cache-size = <0x8000>;
  90                         i-cache-line-size = <64>;
  91                         i-cache-sets = <256>;
  92                         d-cache-size = <0x8000>;
  93                         d-cache-line-size = <64>;
  94                         d-cache-sets = <128>;
  95                         next-level-cache = <&A53_L2>;
  96                         operating-points-v2 = <&a53_opp_table>;
  97                         cpu-idle-states = <&cpu_pd_wait>;
  98                         #cooling-cells = <2>;
  99                 };
 100
 101                 A53_2: cpu@2 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53";
 104                         reg = <0x2>;
 105                         clock-latency = <61036>;
 106                         clocks = <&clk IMX8MN_CLK_ARM>;
 107                         enable-method = "psci";
 108                         i-cache-size = <0x8000>;
 109                         i-cache-line-size = <64>;
 110                         i-cache-sets = <256>;
 111                         d-cache-size = <0x8000>;
 112                         d-cache-line-size = <64>;
 113                         d-cache-sets = <128>;
 114                         next-level-cache = <&A53_L2>;
 115                         operating-points-v2 = <&a53_opp_table>;
 116                         cpu-idle-states = <&cpu_pd_wait>;
 117                         #cooling-cells = <2>;
 118                 };
 119
 120                 A53_3: cpu@3 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53";
 123                         reg = <0x3>;
 124                         clock-latency = <61036>;
 125                         clocks = <&clk IMX8MN_CLK_ARM>;
 126                         enable-method = "psci";
 127                         i-cache-size = <0x8000>;
 128                         i-cache-line-size = <64>;
 129                         i-cache-sets = <256>;
 130                         d-cache-size = <0x8000>;
 131                         d-cache-line-size = <64>;
 132                         d-cache-sets = <128>;
 133                         next-level-cache = <&A53_L2>;
 134                         operating-points-v2 = <&a53_opp_table>;
 135                         cpu-idle-states = <&cpu_pd_wait>;
 136                         #cooling-cells = <2>;
 137                 };
 138
 139                 A53_L2: l2-cache0 {
 140                         compatible = "cache";
 141                         cache-level = <2>;
 142                         cache-size = <0x80000>;
 143                         cache-line-size = <64>;
 144                         cache-sets = <512>;
 145                 };
 146         };
 147
 148         a53_opp_table: opp-table {
 149                 compatible = "operating-points-v2";
 150                 opp-shared;
 151
 152                 opp-1200000000 {
 153                         opp-hz = /bits/ 64 <1200000000>;
 154                         opp-microvolt = <850000>;
 155                         opp-supported-hw = <0xb00>, <0x7>;
 156                         clock-latency-ns = <150000>;
 157                         opp-suspend;
 158                 };
 159
 160                 opp-1400000000 {
 161                         opp-hz = /bits/ 64 <1400000000>;
 162                         opp-microvolt = <950000>;
 163                         opp-supported-hw = <0x300>, <0x7>;
 164                         clock-latency-ns = <150000>;
 165                         opp-suspend;
 166                 };
 167
 168                 opp-1500000000 {
 169                         opp-hz = /bits/ 64 <1500000000>;
 170                         opp-microvolt = <1000000>;
 171                         opp-supported-hw = <0x100>, <0x3>;
 172                         clock-latency-ns = <150000>;
 173                         opp-suspend;
 174                 };
 175         };
 176
 177         osc_32k: clock-osc-32k {
 178                 compatible = "fixed-clock";
 179                 #clock-cells = <0>;
 180                 clock-frequency = <32768>;
 181                 clock-output-names = "osc_32k";
 182         };
 183
 184         osc_24m: clock-osc-24m {
 185                 compatible = "fixed-clock";
 186                 #clock-cells = <0>;
 187                 clock-frequency = <24000000>;
 188                 clock-output-names = "osc_24m";
 189         };
 190
 191         clk_ext1: clock-ext1 {
 192                 compatible = "fixed-clock";
 193                 #clock-cells = <0>;
 194                 clock-frequency = <133000000>;
 195                 clock-output-names = "clk_ext1";
 196         };
 197
 198         clk_ext2: clock-ext2 {
 199                 compatible = "fixed-clock";
 200                 #clock-cells = <0>;
 201                 clock-frequency = <133000000>;
 202                 clock-output-names = "clk_ext2";
 203         };
 204
 205         clk_ext3: clock-ext3 {
 206                 compatible = "fixed-clock";
 207                 #clock-cells = <0>;
 208                 clock-frequency = <133000000>;
 209                 clock-output-names = "clk_ext3";
 210         };
 211
 212         clk_ext4: clock-ext4 {
 213                 compatible = "fixed-clock";
 214                 #clock-cells = <0>;
 215                 clock-frequency = <133000000>;
 216                 clock-output-names = "clk_ext4";
 217         };
 218
 219         pmu {
 220                 compatible = "arm,cortex-a53-pmu";
 221                 interrupts = <GIC_PPI 7
 222                              (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 223         };
 224
 225         psci {
 226                 compatible = "arm,psci-1.0";
 227                 method = "smc";
 228         };
 229
 230         thermal-zones {
 231                 cpu-thermal {
 232                         polling-delay-passive = <250>;
 233                         polling-delay = <2000>;
 234                         thermal-sensors = <&tmu>;
 235                         trips {
 236                                 cpu_alert0: trip0 {
 237                                         temperature = <85000>;
 238                                         hysteresis = <2000>;
 239                                         type = "passive";
 240                                 };
 241
 242                                 cpu_crit0: trip1 {
 243                                         temperature = <95000>;
 244                                         hysteresis = <2000>;
 245                                         type = "critical";
 246                                 };
 247                         };
 248
 249                         cooling-maps {
 250                                 map0 {
 251                                         trip = <&cpu_alert0>;
 252                                         cooling-device =
 253                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 254                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 255                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 256                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 257                                 };
 258                         };
 259                 };
 260         };
 261
 262         timer {
 263                 compatible = "arm,armv8-timer";
 264                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 265                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 266                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 267                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 268                 clock-frequency = <8000000>;
 269                 arm,no-tick-in-suspend;
 270         };
 271
 272         soc: soc@0 {
 273                 compatible = "fsl,imx8mn-soc", "simple-bus";
 274                 #address-cells = <1>;
 275                 #size-cells = <1>;
 276                 ranges = <0x0 0x0 0x0 0x3e000000>;
 277                 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
 278                 nvmem-cells = <&imx8mn_uid>;
 279                 nvmem-cell-names = "soc_unique_id";
 280
 281                 aips1: bus@30000000 {
 282                         compatible = "fsl,aips-bus", "simple-bus";
 283                         reg = <0x30000000 0x400000>;
 284                         #address-cells = <1>;
 285                         #size-cells = <1>;
 286                         ranges;
 287
 288                         spba2: spba-bus@30000000 {
 289                                 compatible = "fsl,spba-bus", "simple-bus";
 290                                 #address-cells = <1>;
 291                                 #size-cells = <1>;
 292                                 reg = <0x30000000 0x100000>;
 293                                 ranges;
 294
 295                                 sai2: sai@30020000 {
 296                                         compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
 297                                         reg = <0x30020000 0x10000>;
 298                                         #sound-dai-cells = <0>;
 299                                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 300                                         clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
 301                                                 <&clk IMX8MN_CLK_DUMMY>,
 302                                                 <&clk IMX8MN_CLK_SAI2_ROOT>,
 303                                                 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
 304                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 305                                         dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
 306                                         dma-names = "rx", "tx";
 307                                         status = "disabled";
 308                                 };
 309
 310                                 sai3: sai@30030000 {
 311                                         compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
 312                                         reg = <0x30030000 0x10000>;
 313                                         #sound-dai-cells = <0>;
 314                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 315                                         clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
 316                                                  <&clk IMX8MN_CLK_DUMMY>,
 317                                                  <&clk IMX8MN_CLK_SAI3_ROOT>,
 318                                                  <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
 319                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 320                                         dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
 321                                         dma-names = "rx", "tx";
 322                                         status = "disabled";
 323                                 };
 324
 325                                 sai5: sai@30050000 {
 326                                         compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
 327                                         reg = <0x30050000 0x10000>;
 328                                         #sound-dai-cells = <0>;
 329                                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 330                                         clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
 331                                                  <&clk IMX8MN_CLK_DUMMY>,
 332                                                  <&clk IMX8MN_CLK_SAI5_ROOT>,
 333                                                  <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
 334                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 335                                         dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
 336                                         dma-names = "rx", "tx";
 337                                         fsl,shared-interrupt;
 338                                         fsl,dataline = <0 0xf 0xf>;
 339                                         status = "disabled";
 340                                 };
 341
 342                                 sai6: sai@30060000 {
 343                                         compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
 344                                         reg = <0x30060000  0x10000>;
 345                                         #sound-dai-cells = <0>;
 346                                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 347                                         clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
 348                                                  <&clk IMX8MN_CLK_DUMMY>,
 349                                                  <&clk IMX8MN_CLK_SAI6_ROOT>,
 350                                                  <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
 351                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 352                                         dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
 353                                         dma-names = "rx", "tx";
 354                                         status = "disabled";
 355                                 };
 356
 357                                 micfil: audio-controller@30080000 {
 358                                         compatible = "fsl,imx8mm-micfil";
 359                                         reg = <0x30080000 0x10000>;
 360                                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 361                                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 362                                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 363                                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 364                                         clocks = <&clk IMX8MN_CLK_PDM_IPG>,
 365                                                  <&clk IMX8MN_CLK_PDM_ROOT>,
 366                                                  <&clk IMX8MN_AUDIO_PLL1_OUT>,
 367                                                  <&clk IMX8MN_AUDIO_PLL2_OUT>,
 368                                                  <&clk IMX8MN_CLK_EXT3>;
 369                                         clock-names = "ipg_clk", "ipg_clk_app",
 370                                                       "pll8k", "pll11k", "clkext3";
 371                                         dmas = <&sdma2 24 25 0x80000000>;
 372                                         dma-names = "rx";
 373                                         #sound-dai-cells = <0>;
 374                                         status = "disabled";
 375                                 };
 376
 377                                 spdif1: spdif@30090000 {
 378                                         compatible = "fsl,imx35-spdif";
 379                                         reg = <0x30090000 0x10000>;
 380                                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 381                                         clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
 382                                                  <&clk IMX8MN_CLK_24M>, /* rxtx0 */
 383                                                  <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
 384                                                  <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
 385                                                  <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
 386                                                  <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
 387                                                  <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
 388                                                  <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
 389                                                  <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
 390                                                  <&clk IMX8MN_CLK_DUMMY>; /* spba */
 391                                         clock-names = "core", "rxtx0",
 392                                                       "rxtx1", "rxtx2",
 393                                                       "rxtx3", "rxtx4",
 394                                                       "rxtx5", "rxtx6",
 395                                                       "rxtx7", "spba";
 396                                         dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
 397                                         dma-names = "rx", "tx";
 398                                         status = "disabled";
 399                                 };
 400
 401                                 sai7: sai@300b0000 {
 402                                         compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
 403                                         reg = <0x300b0000 0x10000>;
 404                                         #sound-dai-cells = <0>;
 405                                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 406                                         clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
 407                                                  <&clk IMX8MN_CLK_DUMMY>,
 408                                                  <&clk IMX8MN_CLK_SAI7_ROOT>,
 409                                                  <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
 410                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 411                                         dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
 412                                         dma-names = "rx", "tx";
 413                                         status = "disabled";
 414                                 };
 415
 416                                 easrc: easrc@300c0000 {
 417                                         compatible = "fsl,imx8mn-easrc";
 418                                         reg = <0x300c0000 0x10000>;
 419                                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 420                                         clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
 421                                         clock-names = "mem";
 422                                         dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
 423                                                <&sdma2 18 23 0> , <&sdma2 19 23 0>,
 424                                                <&sdma2 20 23 0> , <&sdma2 21 23 0>,
 425                                                <&sdma2 22 23 0> , <&sdma2 23 23 0>;
 426                                         dma-names = "ctx0_rx", "ctx0_tx",
 427                                                     "ctx1_rx", "ctx1_tx",
 428                                                     "ctx2_rx", "ctx2_tx",
 429                                                     "ctx3_rx", "ctx3_tx";
 430                                         firmware-name = "/*(DEBLOBBED)*/";
 431                                         fsl,asrc-rate = <8000>;
 432                                         fsl,asrc-format = <2>;
 433                                         status = "disabled";
 434                                 };
 435                         };
 436
 437                         gpio1: gpio@30200000 {
 438                                 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
 439                                 reg = <0x30200000 0x10000>;
 440                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 441                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 442                                 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
 443                                 gpio-controller;
 444                                 #gpio-cells = <2>;
 445                                 interrupt-controller;
 446                                 #interrupt-cells = <2>;
 447                                 gpio-ranges = <&iomuxc 0 10 30>;
 448                         };
 449
 450                         gpio2: gpio@30210000 {
 451                                 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
 452                                 reg = <0x30210000 0x10000>;
 453                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 454                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 455                                 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
 456                                 gpio-controller;
 457                                 #gpio-cells = <2>;
 458                                 interrupt-controller;
 459                                 #interrupt-cells = <2>;
 460                                 gpio-ranges = <&iomuxc 0 40 21>;
 461                         };
 462
 463                         gpio3: gpio@30220000 {
 464                                 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
 465                                 reg = <0x30220000 0x10000>;
 466                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 467                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 468                                 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
 469                                 gpio-controller;
 470                                 #gpio-cells = <2>;
 471                                 interrupt-controller;
 472                                 #interrupt-cells = <2>;
 473                                 gpio-ranges = <&iomuxc 0 61 26>;
 474                         };
 475
 476                         gpio4: gpio@30230000 {
 477                                 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
 478                                 reg = <0x30230000 0x10000>;
 479                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 480                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 481                                 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
 482                                 gpio-controller;
 483                                 #gpio-cells = <2>;
 484                                 interrupt-controller;
 485                                 #interrupt-cells = <2>;
 486                                 gpio-ranges = <&iomuxc 21 108 11>;
 487                         };
 488
 489                         gpio5: gpio@30240000 {
 490                                 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
 491                                 reg = <0x30240000 0x10000>;
 492                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 493                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 494                                 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
 495                                 gpio-controller;
 496                                 #gpio-cells = <2>;
 497                                 interrupt-controller;
 498                                 #interrupt-cells = <2>;
 499                                 gpio-ranges = <&iomuxc 0 119 30>;
 500                         };
 501
 502                         tmu: tmu@30260000 {
 503                                 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
 504                                 reg = <0x30260000 0x10000>;
 505                                 clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
 506                                 #thermal-sensor-cells = <0>;
 507                         };
 508
 509                         wdog1: watchdog@30280000 {
 510                                 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
 511                                 reg = <0x30280000 0x10000>;
 512                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 513                                 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
 514                                 status = "disabled";
 515                         };
 516
 517                         wdog2: watchdog@30290000 {
 518                                 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
 519                                 reg = <0x30290000 0x10000>;
 520                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 521                                 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
 522                                 status = "disabled";
 523                         };
 524
 525                         wdog3: watchdog@302a0000 {
 526                                 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
 527                                 reg = <0x302a0000 0x10000>;
 528                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 529                                 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
 530                                 status = "disabled";
 531                         };
 532
 533                         sdma3: dma-controller@302b0000 {
 534                                 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
 535                                 reg = <0x302b0000 0x10000>;
 536                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 537                                 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
 538                                  <&clk IMX8MN_CLK_SDMA3_ROOT>;
 539                                 clock-names = "ipg", "ahb";
 540                                 #dma-cells = <3>;
 541                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
 542                         };
 543
 544                         sdma2: dma-controller@302c0000 {
 545                                 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
 546                                 reg = <0x302c0000 0x10000>;
 547                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 548                                 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
 549                                          <&clk IMX8MN_CLK_SDMA2_ROOT>;
 550                                 clock-names = "ipg", "ahb";
 551                                 #dma-cells = <3>;
 552                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
 553                         };
 554
 555                         iomuxc: pinctrl@30330000 {
 556                                 compatible = "fsl,imx8mn-iomuxc";
 557                                 reg = <0x30330000 0x10000>;
 558                         };
 559
 560                         gpr: iomuxc-gpr@30340000 {
 561                                 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
 562                                 reg = <0x30340000 0x10000>;
 563                         };
 564
 565                         ocotp: efuse@30350000 {
 566                                 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
 567                                 reg = <0x30350000 0x10000>;
 568                                 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
 569                                 #address-cells = <1>;
 570                                 #size-cells = <1>;
 571
 572                                 imx8mn_uid: unique-id@4 {
 573                                         reg = <0x4 0x8>;
 574                                 };
 575
 576                                 cpu_speed_grade: speed-grade@10 {
 577                                         reg = <0x10 4>;
 578                                 };
 579
 580                                 fec_mac_address: mac-address@90 {
 581                                         reg = <0x90 6>;
 582                                 };
 583                         };
 584
 585                         anatop: anatop@30360000 {
 586                                 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
 587                                              "syscon";
 588                                 reg = <0x30360000 0x10000>;
 589                         };
 590
 591                         snvs: snvs@30370000 {
 592                                 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 593                                 reg = <0x30370000 0x10000>;
 594
 595                                 snvs_rtc: snvs-rtc-lp {
 596                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 597                                         regmap = <&snvs>;
 598                                         offset = <0x34>;
 599                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 600                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 601                                         clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
 602                                         clock-names = "snvs-rtc";
 603                                 };
 604
 605                                 snvs_pwrkey: snvs-powerkey {
 606                                         compatible = "fsl,sec-v4.0-pwrkey";
 607                                         regmap = <&snvs>;
 608                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 609                                         clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
 610                                         clock-names = "snvs-pwrkey";
 611                                         linux,keycode = <KEY_POWER>;
 612                                         wakeup-source;
 613                                         status = "disabled";
 614                                 };
 615                         };
 616
 617                         clk: clock-controller@30380000 {
 618                                 compatible = "fsl,imx8mn-ccm";
 619                                 reg = <0x30380000 0x10000>;
 620                                 #clock-cells = <1>;
 621                                 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
 622                                          <&clk_ext3>, <&clk_ext4>;
 623                                 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 624                                               "clk_ext3", "clk_ext4";
 625                                 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
 626                                                 <&clk IMX8MN_CLK_A53_CORE>,
 627                                                 <&clk IMX8MN_CLK_NOC>,
 628                                                 <&clk IMX8MN_CLK_AUDIO_AHB>,
 629                                                 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
 630                                                 <&clk IMX8MN_SYS_PLL3>,
 631                                                 <&clk IMX8MN_AUDIO_PLL1>,
 632                                                 <&clk IMX8MN_AUDIO_PLL2>;
 633                                 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
 634                                                          <&clk IMX8MN_ARM_PLL_OUT>,
 635                                                          <&clk IMX8MN_SYS_PLL3_OUT>,
 636                                                          <&clk IMX8MN_SYS_PLL1_800M>;
 637                                 assigned-clock-rates = <0>, <0>, <0>,
 638                                                         <400000000>,
 639                                                         <400000000>,
 640                                                         <600000000>,
 641                                                         <393216000>,
 642                                                         <361267200>;
 643                         };
 644
 645                         src: reset-controller@30390000 {
 646                                 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
 647                                 reg = <0x30390000 0x10000>;
 648                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 649                                 #reset-cells = <1>;
 650                         };
 651
 652                         gpc: gpc@303a0000 {
 653                                 compatible = "fsl,imx8mn-gpc";
 654                                 reg = <0x303a0000 0x10000>;
 655                                 interrupt-parent = <&gic>;
 656                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 657
 658                                 pgc {
 659                                         #address-cells = <1>;
 660                                         #size-cells = <0>;
 661
 662                                         pgc_hsiomix: power-domain@0 {
 663                                                 #power-domain-cells = <0>;
 664                                                 reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
 665                                                 clocks = <&clk IMX8MN_CLK_USB_BUS>;
 666                                         };
 667
 668                                         pgc_otg1: power-domain@1 {
 669                                                 #power-domain-cells = <0>;
 670                                                 reg = <IMX8MN_POWER_DOMAIN_OTG1>;
 671                                         };
 672
 673                                         pgc_gpumix: power-domain@2 {
 674                                                 #power-domain-cells = <0>;
 675                                                 reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
 676                                                 clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
 677                                                          <&clk IMX8MN_CLK_GPU_SHADER>,
 678                                                          <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
 679                                                          <&clk IMX8MN_CLK_GPU_AHB>;
 680                                         };
 681
 682                                         pgc_dispmix: power-domain@3 {
 683                                                 #power-domain-cells = <0>;
 684                                                 reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
 685                                                 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
 686                                                          <&clk IMX8MN_CLK_DISP_APB_ROOT>;
 687                                         };
 688
 689                                         pgc_mipi: power-domain@4 {
 690                                                 #power-domain-cells = <0>;
 691                                                 reg = <IMX8MN_POWER_DOMAIN_MIPI>;
 692                                                 power-domains = <&pgc_dispmix>;
 693                                         };
 694                                 };
 695                         };
 696                 };
 697
 698                 aips2: bus@30400000 {
 699                         compatible = "fsl,aips-bus", "simple-bus";
 700                         reg = <0x30400000 0x400000>;
 701                         #address-cells = <1>;
 702                         #size-cells = <1>;
 703                         ranges;
 704
 705                         pwm1: pwm@30660000 {
 706                                 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
 707                                 reg = <0x30660000 0x10000>;
 708                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 709                                 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
 710                                         <&clk IMX8MN_CLK_PWM1_ROOT>;
 711                                 clock-names = "ipg", "per";
 712                                 #pwm-cells = <3>;
 713                                 status = "disabled";
 714                         };
 715
 716                         pwm2: pwm@30670000 {
 717                                 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
 718                                 reg = <0x30670000 0x10000>;
 719                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 720                                 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
 721                                          <&clk IMX8MN_CLK_PWM2_ROOT>;
 722                                 clock-names = "ipg", "per";
 723                                 #pwm-cells = <3>;
 724                                 status = "disabled";
 725                         };
 726
 727                         pwm3: pwm@30680000 {
 728                                 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
 729                                 reg = <0x30680000 0x10000>;
 730                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 731                                 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
 732                                          <&clk IMX8MN_CLK_PWM3_ROOT>;
 733                                 clock-names = "ipg", "per";
 734                                 #pwm-cells = <3>;
 735                                 status = "disabled";
 736                         };
 737
 738                         pwm4: pwm@30690000 {
 739                                 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
 740                                 reg = <0x30690000 0x10000>;
 741                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 742                                 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
 743                                          <&clk IMX8MN_CLK_PWM4_ROOT>;
 744                                 clock-names = "ipg", "per";
 745                                 #pwm-cells = <3>;
 746                                 status = "disabled";
 747                         };
 748
 749                         system_counter: timer@306a0000 {
 750                                 compatible = "nxp,sysctr-timer";
 751                                 reg = <0x306a0000 0x20000>;
 752                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 753                                 clocks = <&osc_24m>;
 754                                 clock-names = "per";
 755                         };
 756                 };
 757
 758                 aips3: bus@30800000 {
 759                         compatible = "fsl,aips-bus", "simple-bus";
 760                         reg = <0x30800000 0x400000>;
 761                         #address-cells = <1>;
 762                         #size-cells = <1>;
 763                         ranges;
 764
 765                         spba1: spba-bus@30800000 {
 766                                 compatible = "fsl,spba-bus", "simple-bus";
 767                                 #address-cells = <1>;
 768                                 #size-cells = <1>;
 769                                 reg = <0x30800000 0x100000>;
 770                                 ranges;
 771
 772                                 ecspi1: spi@30820000 {
 773                                         compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
 774                                         #address-cells = <1>;
 775                                         #size-cells = <0>;
 776                                         reg = <0x30820000 0x10000>;
 777                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 778                                         clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
 779                                                  <&clk IMX8MN_CLK_ECSPI1_ROOT>;
 780                                         clock-names = "ipg", "per";
 781                                         dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
 782                                         dma-names = "rx", "tx";
 783                                         status = "disabled";
 784                                 };
 785
 786                                 ecspi2: spi@30830000 {
 787                                         compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
 788                                         #address-cells = <1>;
 789                                         #size-cells = <0>;
 790                                         reg = <0x30830000 0x10000>;
 791                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 792                                         clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
 793                                                  <&clk IMX8MN_CLK_ECSPI2_ROOT>;
 794                                         clock-names = "ipg", "per";
 795                                         dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
 796                                         dma-names = "rx", "tx";
 797                                         status = "disabled";
 798                                 };
 799
 800                                 ecspi3: spi@30840000 {
 801                                         compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
 802                                         #address-cells = <1>;
 803                                         #size-cells = <0>;
 804                                         reg = <0x30840000 0x10000>;
 805                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 806                                         clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
 807                                                  <&clk IMX8MN_CLK_ECSPI3_ROOT>;
 808                                         clock-names = "ipg", "per";
 809                                         dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
 810                                         dma-names = "rx", "tx";
 811                                         status = "disabled";
 812                                 };
 813
 814                                 uart1: serial@30860000 {
 815                                         compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
 816                                         reg = <0x30860000 0x10000>;
 817                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 818                                         clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
 819                                                  <&clk IMX8MN_CLK_UART1_ROOT>;
 820                                         clock-names = "ipg", "per";
 821                                         dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
 822                                         dma-names = "rx", "tx";
 823                                         status = "disabled";
 824                                 };
 825
 826                                 uart3: serial@30880000 {
 827                                         compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
 828                                         reg = <0x30880000 0x10000>;
 829                                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 830                                         clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
 831                                                  <&clk IMX8MN_CLK_UART3_ROOT>;
 832                                         clock-names = "ipg", "per";
 833                                         dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
 834                                         dma-names = "rx", "tx";
 835                                         status = "disabled";
 836                                 };
 837
 838                                 uart2: serial@30890000 {
 839                                         compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
 840                                         reg = <0x30890000 0x10000>;
 841                                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 842                                         clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
 843                                                  <&clk IMX8MN_CLK_UART2_ROOT>;
 844                                         clock-names = "ipg", "per";
 845                                         status = "disabled";
 846                                 };
 847                         };
 848
 849                         crypto: crypto@30900000 {
 850                                 compatible = "fsl,sec-v4.0";
 851                                 #address-cells = <1>;
 852                                 #size-cells = <1>;
 853                                 reg = <0x30900000 0x40000>;
 854                                 ranges = <0 0x30900000 0x40000>;
 855                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 856                                 clocks = <&clk IMX8MN_CLK_AHB>,
 857                                          <&clk IMX8MN_CLK_IPG_ROOT>;
 858                                 clock-names = "aclk", "ipg";
 859
 860                                 sec_jr0: jr@1000 {
 861                                          compatible = "fsl,sec-v4.0-job-ring";
 862                                          reg = <0x1000 0x1000>;
 863                                          interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 864                                          status = "disabled";
 865                                 };
 866
 867                                 sec_jr1: jr@2000 {
 868                                          compatible = "fsl,sec-v4.0-job-ring";
 869                                          reg = <0x2000 0x1000>;
 870                                          interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 871                                 };
 872
 873                                 sec_jr2: jr@3000 {
 874                                          compatible = "fsl,sec-v4.0-job-ring";
 875                                          reg = <0x3000 0x1000>;
 876                                          interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 877                                 };
 878                         };
 879
 880                         i2c1: i2c@30a20000 {
 881                                 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
 882                                 #address-cells = <1>;
 883                                 #size-cells = <0>;
 884                                 reg = <0x30a20000 0x10000>;
 885                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 886                                 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
 887                                 status = "disabled";
 888                         };
 889
 890                         i2c2: i2c@30a30000 {
 891                                 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
 892                                 #address-cells = <1>;
 893                                 #size-cells = <0>;
 894                                 reg = <0x30a30000 0x10000>;
 895                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 896                                 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
 897                                 status = "disabled";
 898                         };
 899
 900                         i2c3: i2c@30a40000 {
 901                                 #address-cells = <1>;
 902                                 #size-cells = <0>;
 903                                 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
 904                                 reg = <0x30a40000 0x10000>;
 905                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 906                                 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
 907                                 status = "disabled";
 908                         };
 909
 910                         i2c4: i2c@30a50000 {
 911                                 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
 912                                 #address-cells = <1>;
 913                                 #size-cells = <0>;
 914                                 reg = <0x30a50000 0x10000>;
 915                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 916                                 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
 917                                 status = "disabled";
 918                         };
 919
 920                         uart4: serial@30a60000 {
 921                                 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
 922                                 reg = <0x30a60000 0x10000>;
 923                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 924                                 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
 925                                          <&clk IMX8MN_CLK_UART4_ROOT>;
 926                                 clock-names = "ipg", "per";
 927                                 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
 928                                 dma-names = "rx", "tx";
 929                                 status = "disabled";
 930                         };
 931
 932                         mu: mailbox@30aa0000 {
 933                                 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
 934                                 reg = <0x30aa0000 0x10000>;
 935                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 936                                 clocks = <&clk IMX8MN_CLK_MU_ROOT>;
 937                                 #mbox-cells = <2>;
 938                         };
 939
 940                         usdhc1: mmc@30b40000 {
 941                                 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 942                                 reg = <0x30b40000 0x10000>;
 943                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 944                                 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
 945                                          <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
 946                                          <&clk IMX8MN_CLK_USDHC1_ROOT>;
 947                                 clock-names = "ipg", "ahb", "per";
 948                                 fsl,tuning-start-tap = <20>;
 949                                 fsl,tuning-step = <2>;
 950                                 bus-width = <4>;
 951                                 status = "disabled";
 952                         };
 953
 954                         usdhc2: mmc@30b50000 {
 955                                 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 956                                 reg = <0x30b50000 0x10000>;
 957                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 958                                 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
 959                                          <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
 960                                          <&clk IMX8MN_CLK_USDHC2_ROOT>;
 961                                 clock-names = "ipg", "ahb", "per";
 962                                 fsl,tuning-start-tap = <20>;
 963                                 fsl,tuning-step = <2>;
 964                                 bus-width = <4>;
 965                                 status = "disabled";
 966                         };
 967
 968                         usdhc3: mmc@30b60000 {
 969                                 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 970                                 reg = <0x30b60000 0x10000>;
 971                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 972                                 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
 973                                          <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
 974                                          <&clk IMX8MN_CLK_USDHC3_ROOT>;
 975                                 clock-names = "ipg", "ahb", "per";
 976                                 fsl,tuning-start-tap = <20>;
 977                                 fsl,tuning-step = <2>;
 978                                 bus-width = <4>;
 979                                 status = "disabled";
 980                         };
 981
 982                         flexspi: spi@30bb0000 {
 983                                 #address-cells = <1>;
 984                                 #size-cells = <0>;
 985                                 compatible = "nxp,imx8mm-fspi";
 986                                 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
 987                                 reg-names = "fspi_base", "fspi_mmap";
 988                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 989                                 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
 990                                          <&clk IMX8MN_CLK_QSPI_ROOT>;
 991                                 clock-names = "fspi_en", "fspi";
 992                                 status = "disabled";
 993                         };
 994
 995                         sdma1: dma-controller@30bd0000 {
 996                                 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
 997                                 reg = <0x30bd0000 0x10000>;
 998                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 999                                 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
1000                                          <&clk IMX8MN_CLK_AHB>;
1001                                 clock-names = "ipg", "ahb";
1002                                 #dma-cells = <3>;
1003                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
1004                         };
1005
1006                         fec1: ethernet@30be0000 {
1007                                 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1008                                 reg = <0x30be0000 0x10000>;
1009                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1010                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1011                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1012                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1013                                 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
1014                                          <&clk IMX8MN_CLK_ENET1_ROOT>,
1015                                          <&clk IMX8MN_CLK_ENET_TIMER>,
1016                                          <&clk IMX8MN_CLK_ENET_REF>,
1017                                          <&clk IMX8MN_CLK_ENET_PHY_REF>;
1018                                 clock-names = "ipg", "ahb", "ptp",
1019                                               "enet_clk_ref", "enet_out";
1020                                 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
1021                                                   <&clk IMX8MN_CLK_ENET_TIMER>,
1022                                                   <&clk IMX8MN_CLK_ENET_REF>,
1023                                                   <&clk IMX8MN_CLK_ENET_PHY_REF>;
1024                                 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1025                                                          <&clk IMX8MN_SYS_PLL2_100M>,
1026                                                          <&clk IMX8MN_SYS_PLL2_125M>,
1027                                                          <&clk IMX8MN_SYS_PLL2_50M>;
1028                                 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1029                                 fsl,num-tx-queues = <3>;
1030                                 fsl,num-rx-queues = <3>;
1031                                 nvmem-cells = <&fec_mac_address>;
1032                                 nvmem-cell-names = "mac-address";
1033                                 fsl,stop-mode = <&gpr 0x10 3>;
1034                                 status = "disabled";
1035                         };
1036
1037                 };
1038
1039                 aips4: bus@32c00000 {
1040                         compatible = "fsl,aips-bus", "simple-bus";
1041                         reg = <0x32c00000 0x400000>;
1042                         #address-cells = <1>;
1043                         #size-cells = <1>;
1044                         ranges;
1045
1046                         disp_blk_ctrl: blk-ctrl@32e28000 {
1047                                 compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
1048                                 reg = <0x32e28000 0x100>;
1049                                 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1050                                                 <&pgc_dispmix>, <&pgc_mipi>,
1051                                                 <&pgc_mipi>;
1052                                 power-domain-names = "bus", "isi",
1053                                                      "lcdif", "mipi-dsi",
1054                                                      "mipi-csi";
1055                                 clocks = <&clk IMX8MN_CLK_DISP_AXI>,
1056                                          <&clk IMX8MN_CLK_DISP_APB>,
1057                                          <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1058                                          <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1059                                          <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1060                                          <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1061                                          <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
1062                                          <&clk IMX8MN_CLK_DSI_CORE>,
1063                                          <&clk IMX8MN_CLK_DSI_PHY_REF>,
1064                                          <&clk IMX8MN_CLK_CSI1_PHY_REF>,
1065                                          <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
1066                                 clock-names = "disp_axi", "disp_apb",
1067                                               "disp_axi_root", "disp_apb_root",
1068                                               "lcdif-axi", "lcdif-apb", "lcdif-pix",
1069                                               "dsi-pclk", "dsi-ref",
1070                                               "csi-aclk", "csi-pclk";
1071                                 #power-domain-cells = <1>;
1072                         };
1073
1074                         usbotg1: usb@32e40000 {
1075                                 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
1076                                 reg = <0x32e40000 0x200>;
1077                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1078                                 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
1079                                 clock-names = "usb1_ctrl_root_clk";
1080                                 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
1081                                 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
1082                                 phys = <&usbphynop1>;
1083                                 fsl,usbmisc = <&usbmisc1 0>;
1084                                 power-domains = <&pgc_hsiomix>;
1085                                 status = "disabled";
1086                         };
1087
1088                         usbmisc1: usbmisc@32e40200 {
1089                                 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
1090                                 #index-cells = <1>;
1091                                 reg = <0x32e40200 0x200>;
1092                         };
1093                 };
1094
1095                 dma_apbh: dma-controller@33000000 {
1096                         compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1097                         reg = <0x33000000 0x2000>;
1098                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1099                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1100                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1101                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1102                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1103                         #dma-cells = <1>;
1104                         dma-channels = <4>;
1105                         clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1106                 };
1107
1108                 gpmi: nand-controller@33002000 {
1109                         compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
1110                         #address-cells = <1>;
1111                         #size-cells = <0>;
1112                         reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1113                         reg-names = "gpmi-nand", "bch";
1114                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1115                         interrupt-names = "bch";
1116                         clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
1117                                  <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1118                         clock-names = "gpmi_io", "gpmi_bch_apb";
1119                         dmas = <&dma_apbh 0>;
1120                         dma-names = "rx-tx";
1121                         status = "disabled";
1122                 };
1123
1124                 gpu: gpu@38000000 {
1125                         compatible = "vivante,gc";
1126                         reg = <0x38000000 0x8000>;
1127                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1128                         clocks = <&clk IMX8MN_CLK_GPU_AHB>,
1129                                 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
1130                                 <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
1131                                 <&clk IMX8MN_CLK_GPU_SHADER>;
1132                         clock-names = "reg", "bus", "core", "shader";
1133                         assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
1134                                           <&clk IMX8MN_CLK_GPU_SHADER>,
1135                                           <&clk IMX8MN_CLK_GPU_AXI>,
1136                                           <&clk IMX8MN_CLK_GPU_AHB>,
1137                                           <&clk IMX8MN_GPU_PLL>;
1138                         assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
1139                                                   <&clk IMX8MN_GPU_PLL_OUT>,
1140                                                   <&clk IMX8MN_SYS_PLL1_800M>,
1141                                                   <&clk IMX8MN_SYS_PLL1_800M>;
1142                         assigned-clock-rates = <400000000>,
1143                                                <400000000>,
1144                                                <800000000>,
1145                                                <400000000>,
1146                                                <1200000000>;
1147                         power-domains = <&pgc_gpumix>;
1148                 };
1149
1150                 gic: interrupt-controller@38800000 {
1151                         compatible = "arm,gic-v3";
1152                         reg = <0x38800000 0x10000>,
1153                               <0x38880000 0xc0000>;
1154                         #interrupt-cells = <3>;
1155                         interrupt-controller;
1156                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1157                 };
1158
1159                 ddrc: memory-controller@3d400000 {
1160                         compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
1161                         reg = <0x3d400000 0x400000>;
1162                         clock-names = "core", "pll", "alt", "apb";
1163                         clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
1164                                  <&clk IMX8MN_DRAM_PLL>,
1165                                  <&clk IMX8MN_CLK_DRAM_ALT>,
1166                                  <&clk IMX8MN_CLK_DRAM_APB>;
1167                 };
1168
1169                 ddr-pmu@3d800000 {
1170                         compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
1171                         reg = <0x3d800000 0x400000>;
1172                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1173                 };
1174         };
1175
1176         usbphynop1: usbphynop1 {
1177                 #phy-cells = <0>;
1178                 compatible = "usb-nop-xceiv";
1179                 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1180                 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1181                 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1182                 clock-names = "main_clk";
1183                 power-domains = <&pgc_otg1>;
1184         };
1185 };