arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/usb/pd.h>
   7 #include "imx8mn.dtsi"
   8
   9 / {
  10         chosen {
  11                 stdout-path = &uart2;
  12         };
  13
  14         gpio-leds {
  15                 compatible = "gpio-leds";
  16                 pinctrl-names = "default";
  17                 pinctrl-0 = <&pinctrl_gpio_led>;
  18
  19                 status {
  20                         label = "yellow:status";
  21                         gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  22                         default-state = "on";
  23                 };
  24         };
  25
  26         hdmi-connector {
  27                 compatible = "hdmi-connector";
  28                 label = "hdmi";
  29                 type = "a";
  30
  31                 port {
  32                         hdmi_connector_in: endpoint {
  33                                 remote-endpoint = <&adv7533_out>;
  34                         };
  35                 };
  36         };
  37
  38         memory@40000000 {
  39                 device_type = "memory";
  40                 reg = <0x0 0x40000000 0 0x80000000>;
  41         };
  42
  43         reg_usdhc2_vmmc: regulator-usdhc2 {
  44                 compatible = "regulator-fixed";
  45                 pinctrl-names = "default";
  46                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  47                 regulator-name = "VSD_3V3";
  48                 regulator-min-microvolt = <3300000>;
  49                 regulator-max-microvolt = <3300000>;
  50                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  51                 off-on-delay-us = <12000>;
  52                 enable-active-high;
  53         };
  54
  55         ir-receiver {
  56                 compatible = "gpio-ir-receiver";
  57                 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
  58                 pinctrl-names = "default";
  59                 pinctrl-0 = <&pinctrl_ir>;
  60                 linux,autosuspend-period = <125>;
  61         };
  62
  63         audio_codec_bt_sco: audio-codec-bt-sco {
  64                 compatible = "linux,bt-sco";
  65                 #sound-dai-cells = <1>;
  66         };
  67
  68         wm8524: audio-codec {
  69                 #sound-dai-cells = <0>;
  70                 compatible = "wlf,wm8524";
  71                 pinctrl-names = "default";
  72                 pinctrl-0 = <&pinctrl_gpio_wlf>;
  73                 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
  74         };
  75
  76         sound-bt-sco {
  77                 compatible = "simple-audio-card";
  78                 simple-audio-card,name = "bt-sco-audio";
  79                 simple-audio-card,format = "dsp_a";
  80                 simple-audio-card,bitclock-inversion;
  81                 simple-audio-card,frame-master = <&btcpu>;
  82                 simple-audio-card,bitclock-master = <&btcpu>;
  83
  84                 btcpu: simple-audio-card,cpu {
  85                         sound-dai = <&sai2>;
  86                         dai-tdm-slot-num = <2>;
  87                         dai-tdm-slot-width = <16>;
  88                 };
  89
  90                 simple-audio-card,codec {
  91                         sound-dai = <&audio_codec_bt_sco 1>;
  92                 };
  93         };
  94
  95         sound-wm8524 {
  96                 compatible = "fsl,imx-audio-wm8524";
  97                 model = "wm8524-audio";
  98                 audio-cpu = <&sai3>;
  99                 audio-codec = <&wm8524>;
 100                 audio-asrc = <&easrc>;
 101                 audio-routing =
 102                         "Line Out Jack", "LINEVOUTL",
 103                         "Line Out Jack", "LINEVOUTR";
 104         };
 105
 106         sound-spdif {
 107                 compatible = "fsl,imx-audio-spdif";
 108                 model = "imx-spdif";
 109                 spdif-controller = <&spdif1>;
 110                 spdif-out;
 111                 spdif-in;
 112         };
 113 };
 114
 115 &easrc {
 116         fsl,asrc-rate = <48000>;
 117         status = "okay";
 118 };
 119
 120 &fec1 {
 121         pinctrl-names = "default";
 122         pinctrl-0 = <&pinctrl_fec1>;
 123         phy-mode = "rgmii-id";
 124         phy-handle = <&ethphy0>;
 125         fsl,magic-packet;
 126         status = "okay";
 127
 128         mdio {
 129                 #address-cells = <1>;
 130                 #size-cells = <0>;
 131
 132                 ethphy0: ethernet-phy@0 {
 133                         compatible = "ethernet-phy-ieee802.3-c22";
 134                         reg = <0>;
 135                         reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 136                         reset-assert-us = <10000>;
 137                         qca,disable-smarteee;
 138                         vddio-supply = <&vddio>;
 139
 140                         vddio: vddio-regulator {
 141                                 regulator-min-microvolt = <1800000>;
 142                                 regulator-max-microvolt = <1800000>;
 143                         };
 144                 };
 145         };
 146 };
 147
 148 &flexspi {
 149         pinctrl-names = "default";
 150         pinctrl-0 = <&pinctrl_flexspi>;
 151         status = "okay";
 152
 153         flash0: flash@0 {
 154                 compatible = "jedec,spi-nor";
 155                 reg = <0>;
 156                 #address-cells = <1>;
 157                 #size-cells = <1>;
 158                 spi-max-frequency = <166000000>;
 159                 spi-tx-bus-width = <4>;
 160                 spi-rx-bus-width = <4>;
 161         };
 162 };
 163
 164 &i2c1 {
 165         clock-frequency = <400000>;
 166         pinctrl-names = "default";
 167         pinctrl-0 = <&pinctrl_i2c1>;
 168         status = "okay";
 169 };
 170
 171 &i2c2 {
 172         clock-frequency = <400000>;
 173         pinctrl-names = "default", "gpio";
 174         pinctrl-0 = <&pinctrl_i2c2>;
 175         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 176         scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 177         sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 178         status = "okay";
 179
 180         hdmi@3d {
 181                 compatible = "adi,adv7535";
 182                 reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
 183                 reg-names = "main", "cec", "edid", "packet";
 184                 adi,dsi-lanes = <4>;
 185
 186                 adi,input-depth = <8>;
 187                 adi,input-colorspace = "rgb";
 188                 adi,input-clock = "1x";
 189                 adi,input-style = <1>;
 190                 adi,input-justification = "evenly";
 191
 192                 ports {
 193                         #address-cells = <1>;
 194                         #size-cells = <0>;
 195
 196                         port@0 {
 197                                 reg = <0>;
 198
 199                                 adv7533_in: endpoint {
 200                                         remote-endpoint = <&dsi_out>;
 201                                 };
 202                         };
 203
 204                         port@1 {
 205                                 reg = <1>;
 206
 207                                 adv7533_out: endpoint {
 208                                         remote-endpoint = <&hdmi_connector_in>;
 209                                 };
 210                         };
 211
 212                 };
 213         };
 214
 215         ptn5110: tcpc@50 {
 216                 compatible = "nxp,ptn5110";
 217                 pinctrl-names = "default";
 218                 pinctrl-0 = <&pinctrl_typec1>;
 219                 reg = <0x50>;
 220                 interrupt-parent = <&gpio2>;
 221                 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 222                 status = "okay";
 223
 224                 port {
 225                         typec1_dr_sw: endpoint {
 226                                 remote-endpoint = <&usb1_drd_sw>;
 227                         };
 228                 };
 229
 230                 typec1_con: connector {
 231                         compatible = "usb-c-connector";
 232                         label = "USB-C";
 233                         power-role = "dual";
 234                         data-role = "dual";
 235                         try-power-role = "sink";
 236                         source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
 237                         sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
 238                                      PDO_VAR(5000, 20000, 3000)>;
 239                         op-sink-microwatt = <15000000>;
 240                         self-powered;
 241                 };
 242         };
 243 };
 244
 245 &i2c3 {
 246         clock-frequency = <400000>;
 247         pinctrl-names = "default", "gpio";
 248         pinctrl-0 = <&pinctrl_i2c3>;
 249         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 250         scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
 251         sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
 252         status = "okay";
 253
 254         pca6416: gpio@20 {
 255                 compatible = "ti,tca6416";
 256                 reg = <0x20>;
 257                 gpio-controller;
 258                 #gpio-cells = <2>;
 259         };
 260
 261         camera@3c {
 262                 compatible = "ovti,ov5640";
 263                 reg = <0x3c>;
 264                 pinctrl-names = "default";
 265                 pinctrl-0 = <&pinctrl_camera>;
 266                 clocks = <&clk IMX8MN_CLK_CLKO1>;
 267                 clock-names = "xclk";
 268                 assigned-clocks = <&clk IMX8MN_CLK_CLKO1>;
 269                 assigned-clock-parents = <&clk IMX8MN_CLK_24M>;
 270                 assigned-clock-rates = <24000000>;
 271                 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 272                 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
 273
 274                 port {
 275                         ov5640_to_mipi_csi2: endpoint {
 276                                 remote-endpoint = <&imx8mn_mipi_csi_in>;
 277                                 clock-lanes = <0>;
 278                                 data-lanes = <1 2>;
 279                         };
 280                 };
 281         };
 282 };
 283
 284 &isi {
 285         status = "okay";
 286 };
 287
 288 &mipi_csi {
 289         status = "okay";
 290
 291         ports {
 292                 port@0 {
 293                         imx8mn_mipi_csi_in: endpoint {
 294                                 remote-endpoint = <&ov5640_to_mipi_csi2>;
 295                                 data-lanes = <1 2>;
 296                         };
 297                 };
 298         };
 299 };
 300
 301 &lcdif {
 302         status = "okay";
 303 };
 304
 305 &mipi_dsi {
 306         samsung,esc-clock-frequency = <10000000>;
 307         status = "okay";
 308
 309         ports {
 310                 port@1 {
 311                         reg = <1>;
 312
 313                         dsi_out: endpoint {
 314                                 remote-endpoint = <&adv7533_in>;
 315                                 data-lanes = <1 2 3 4>;
 316                         };
 317                 };
 318         };
 319 };
 320
 321 &sai2 {
 322         #sound-dai-cells = <0>;
 323         pinctrl-names = "default";
 324         pinctrl-0 = <&pinctrl_sai2>;
 325         assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
 326         assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
 327         assigned-clock-rates = <24576000>;
 328         status = "okay";
 329 };
 330
 331 &sai3 {
 332         pinctrl-names = "default";
 333         pinctrl-0 = <&pinctrl_sai3>;
 334         assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
 335         assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
 336         assigned-clock-rates = <24576000>;
 337         fsl,sai-mclk-direction-output;
 338         status = "okay";
 339 };
 340
 341 &snvs_pwrkey {
 342         status = "okay";
 343 };
 344
 345 &spdif1 {
 346         pinctrl-names = "default";
 347         pinctrl-0 = <&pinctrl_spdif1>;
 348         assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
 349         assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
 350         assigned-clock-rates = <24576000>;
 351         status = "okay";
 352 };
 353
 354 &uart1 { /* BT */
 355         pinctrl-names = "default";
 356         pinctrl-0 = <&pinctrl_uart1>;
 357         assigned-clocks = <&clk IMX8MN_CLK_UART1>;
 358         assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
 359         uart-has-rtscts;
 360         status = "okay";
 361 };
 362
 363 &uart2 { /* console */
 364         pinctrl-names = "default";
 365         pinctrl-0 = <&pinctrl_uart2>;
 366         status = "okay";
 367 };
 368
 369 &uart3 {
 370         pinctrl-names = "default";
 371         pinctrl-0 = <&pinctrl_uart3>;
 372         assigned-clocks = <&clk IMX8MN_CLK_UART3>;
 373         assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
 374         uart-has-rtscts;
 375         status = "okay";
 376 };
 377
 378 &usbphynop1 {
 379         wakeup-source;
 380 };
 381
 382 &usbotg1 {
 383         dr_mode = "otg";
 384         hnp-disable;
 385         srp-disable;
 386         adp-disable;
 387         usb-role-switch;
 388         disable-over-current;
 389         samsung,picophy-pre-emp-curr-control = <3>;
 390         samsung,picophy-dc-vol-level-adjust = <7>;
 391         status = "okay";
 392
 393         port {
 394                 usb1_drd_sw: endpoint {
 395                         remote-endpoint = <&typec1_dr_sw>;
 396                 };
 397         };
 398 };
 399
 400 &usdhc2 {
 401         assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
 402         assigned-clock-rates = <200000000>;
 403         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 404         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 405         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 406         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 407         cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 408         bus-width = <4>;
 409         vmmc-supply = <&reg_usdhc2_vmmc>;
 410         status = "okay";
 411 };
 412
 413 &usdhc3 {
 414         assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
 415         assigned-clock-rates = <400000000>;
 416         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 417         pinctrl-0 = <&pinctrl_usdhc3>;
 418         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 419         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 420         bus-width = <8>;
 421         non-removable;
 422         status = "okay";
 423 };
 424
 425 &wdog1 {
 426         pinctrl-names = "default";
 427         pinctrl-0 = <&pinctrl_wdog>;
 428         fsl,ext-reset-output;
 429         status = "okay";
 430 };
 431
 432 &iomuxc {
 433         pinctrl_camera: cameragrp {
 434                 fsl,pins = <
 435                         MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6               0x19
 436                         MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7               0x19
 437                         MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1      0x59
 438                 >;
 439         };
 440
 441         pinctrl_fec1: fec1grp {
 442                 fsl,pins = <
 443                         MX8MN_IOMUXC_ENET_MDC_ENET1_MDC         0x3
 444                         MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
 445                         MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
 446                         MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
 447                         MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
 448                         MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
 449                         MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
 450                         MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
 451                         MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
 452                         MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
 453                         MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
 454                         MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
 455                         MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 456                         MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 457                         MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
 458                 >;
 459         };
 460
 461         pinctrl_flexspi: flexspigrp {
 462                 fsl,pins = <
 463                         MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
 464                         MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
 465                         MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
 466                         MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
 467                         MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
 468                         MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
 469                 >;
 470         };
 471
 472         pinctrl_gpio_led: gpioledgrp {
 473                 fsl,pins = <
 474                         MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16    0x19
 475                 >;
 476         };
 477
 478         pinctrl_gpio_wlf: gpiowlfgrp {
 479                 fsl,pins = <
 480                         MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21        0xd6
 481                 >;
 482         };
 483
 484         pinctrl_ir: irgrp {
 485                 fsl,pins = <
 486                         MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
 487                 >;
 488         };
 489
 490         pinctrl_i2c1: i2c1grp {
 491                 fsl,pins = <
 492                         MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 493                         MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 494                 >;
 495         };
 496
 497         pinctrl_i2c2: i2c2grp {
 498                 fsl,pins = <
 499                         MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c3
 500                         MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c3
 501                 >;
 502         };
 503
 504         pinctrl_i2c2_gpio: i2c2gpiogrp {
 505                 fsl,pins = <
 506                         MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16        0x1c3
 507                         MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17        0x1c3
 508                 >;
 509         };
 510
 511         pinctrl_i2c3: i2c3grp {
 512                 fsl,pins = <
 513                         MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 514                         MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 515                 >;
 516         };
 517
 518         pinctrl_i2c3_gpio: i2c3gpiogrp {
 519                 fsl,pins = <
 520                         MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18        0x1c3
 521                         MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19        0x1c3
 522                 >;
 523         };
 524
 525         pinctrl_pmic: pmicirqgrp {
 526                 fsl,pins = <
 527                         MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x141
 528                 >;
 529         };
 530
 531         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 532                 fsl,pins = <
 533                         MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
 534                 >;
 535         };
 536
 537         pinctrl_sai2: sai2grp {
 538                 fsl,pins = <
 539                         MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
 540                         MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
 541                         MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
 542                         MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6
 543                 >;
 544         };
 545
 546         pinctrl_sai3: sai3grp {
 547                 fsl,pins = <
 548                         MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
 549                         MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
 550                         MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
 551                         MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
 552                 >;
 553         };
 554
 555         pinctrl_spdif1: spdif1grp {
 556                 fsl,pins = <
 557                         MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT        0xd6
 558                         MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN         0xd6
 559                 >;
 560         };
 561
 562         pinctrl_typec1: typec1grp {
 563                 fsl,pins = <
 564                         MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11      0x159
 565                 >;
 566         };
 567
 568         pinctrl_uart1: uart1grp {
 569                 fsl,pins = <
 570                         MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 571                         MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 572                         MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B  0x140
 573                         MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B  0x140
 574                 >;
 575         };
 576
 577         pinctrl_uart2: uart2grp {
 578                 fsl,pins = <
 579                         MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
 580                         MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
 581                 >;
 582         };
 583
 584         pinctrl_uart3: uart3grp {
 585                 fsl,pins = <
 586                         MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX           0x140
 587                         MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX           0x140
 588                         MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
 589                         MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B        0x140
 590                 >;
 591         };
 592
 593         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 594                 fsl,pins = <
 595                         MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x1c4
 596                 >;
 597         };
 598
 599         pinctrl_usdhc2: usdhc2grp {
 600                 fsl,pins = <
 601                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 602                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 603                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 604                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 605                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 606                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 607                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 608                 >;
 609         };
 610
 611         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 612                 fsl,pins = <
 613                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 614                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 615                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 616                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 617                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 618                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 619                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 620                 >;
 621         };
 622
 623         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 624                 fsl,pins = <
 625                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 626                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 627                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 628                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 629                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 630                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 631                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 632                 >;
 633         };
 634
 635         pinctrl_usdhc3: usdhc3grp {
 636                 fsl,pins = <
 637                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000190
 638                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
 639                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
 640                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
 641                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
 642                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
 643                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
 644                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
 645                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
 646                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
 647                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
 648                 >;
 649         };
 650
 651         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 652                 fsl,pins = <
 653                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000194
 654                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
 655                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
 656                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
 657                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
 658                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
 659                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
 660                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
 661                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
 662                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
 663                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
 664                 >;
 665         };
 666
 667         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 668                 fsl,pins = <
 669                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000196
 670                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
 671                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
 672                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
 673                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
 674                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
 675                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
 676                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
 677                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
 678                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
 679                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
 680                 >;
 681         };
 682
 683         pinctrl_wdog: wdoggrp {
 684                 fsl,pins = <
 685                         MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0x166
 686                 >;
 687         };
 688 };