arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/usb/pd.h>
   7 #include "imx8mn.dtsi"
   8
   9 / {
  10         chosen {
  11                 stdout-path = &uart2;
  12         };
  13
  14         gpio-leds {
  15                 compatible = "gpio-leds";
  16                 pinctrl-names = "default";
  17                 pinctrl-0 = <&pinctrl_gpio_led>;
  18
  19                 status {
  20                         label = "yellow:status";
  21                         gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  22                         default-state = "on";
  23                 };
  24         };
  25
  26         memory@40000000 {
  27                 device_type = "memory";
  28                 reg = <0x0 0x40000000 0 0x80000000>;
  29         };
  30
  31         reg_usdhc2_vmmc: regulator-usdhc2 {
  32                 compatible = "regulator-fixed";
  33                 pinctrl-names = "default";
  34                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  35                 regulator-name = "VSD_3V3";
  36                 regulator-min-microvolt = <3300000>;
  37                 regulator-max-microvolt = <3300000>;
  38                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  39                 enable-active-high;
  40         };
  41
  42         ir-receiver {
  43                 compatible = "gpio-ir-receiver";
  44                 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
  45                 pinctrl-names = "default";
  46                 pinctrl-0 = <&pinctrl_ir>;
  47                 linux,autosuspend-period = <125>;
  48         };
  49
  50         audio_codec_bt_sco: audio-codec-bt-sco {
  51                 compatible = "linux,bt-sco";
  52                 #sound-dai-cells = <1>;
  53         };
  54
  55         wm8524: audio-codec {
  56                 #sound-dai-cells = <0>;
  57                 compatible = "wlf,wm8524";
  58                 pinctrl-names = "default";
  59                 pinctrl-0 = <&pinctrl_gpio_wlf>;
  60                 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
  61                 clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
  62                 clock-names = "mclk";
  63         };
  64
  65         sound-bt-sco {
  66                 compatible = "simple-audio-card";
  67                 simple-audio-card,name = "bt-sco-audio";
  68                 simple-audio-card,format = "dsp_a";
  69                 simple-audio-card,bitclock-inversion;
  70                 simple-audio-card,frame-master = <&btcpu>;
  71                 simple-audio-card,bitclock-master = <&btcpu>;
  72
  73                 btcpu: simple-audio-card,cpu {
  74                         sound-dai = <&sai2>;
  75                         dai-tdm-slot-num = <2>;
  76                         dai-tdm-slot-width = <16>;
  77                 };
  78
  79                 simple-audio-card,codec {
  80                         sound-dai = <&audio_codec_bt_sco 1>;
  81                 };
  82         };
  83
  84         sound-wm8524 {
  85                 compatible = "fsl,imx-audio-wm8524";
  86                 model = "wm8524-audio";
  87                 audio-cpu = <&sai3>;
  88                 audio-codec = <&wm8524>;
  89                 audio-asrc = <&easrc>;
  90                 audio-routing =
  91                         "Line Out Jack", "LINEVOUTL",
  92                         "Line Out Jack", "LINEVOUTR";
  93         };
  94
  95         sound-spdif {
  96                 compatible = "fsl,imx-audio-spdif";
  97                 model = "imx-spdif";
  98                 spdif-controller = <&spdif1>;
  99                 spdif-out;
 100                 spdif-in;
 101         };
 102 };
 103
 104 &easrc {
 105         fsl,asrc-rate = <48000>;
 106         status = "okay";
 107 };
 108
 109 &fec1 {
 110         pinctrl-names = "default";
 111         pinctrl-0 = <&pinctrl_fec1>;
 112         phy-mode = "rgmii-id";
 113         phy-handle = <&ethphy0>;
 114         fsl,magic-packet;
 115         status = "okay";
 116
 117         mdio {
 118                 #address-cells = <1>;
 119                 #size-cells = <0>;
 120
 121                 ethphy0: ethernet-phy@0 {
 122                         compatible = "ethernet-phy-ieee802.3-c22";
 123                         reg = <0>;
 124                         reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 125                         reset-assert-us = <10000>;
 126                         qca,disable-smarteee;
 127                         vddio-supply = <&vddio>;
 128
 129                         vddio: vddio-regulator {
 130                                 regulator-min-microvolt = <1800000>;
 131                                 regulator-max-microvolt = <1800000>;
 132                         };
 133                 };
 134         };
 135 };
 136
 137 &flexspi {
 138         pinctrl-names = "default";
 139         pinctrl-0 = <&pinctrl_flexspi>;
 140         status = "okay";
 141
 142         flash0: flash@0 {
 143                 compatible = "jedec,spi-nor";
 144                 reg = <0>;
 145                 #address-cells = <1>;
 146                 #size-cells = <1>;
 147                 spi-max-frequency = <166000000>;
 148                 spi-tx-bus-width = <4>;
 149                 spi-rx-bus-width = <4>;
 150         };
 151 };
 152
 153 &i2c1 {
 154         clock-frequency = <400000>;
 155         pinctrl-names = "default";
 156         pinctrl-0 = <&pinctrl_i2c1>;
 157         status = "okay";
 158 };
 159
 160 &i2c2 {
 161         clock-frequency = <400000>;
 162         pinctrl-names = "default";
 163         pinctrl-0 = <&pinctrl_i2c2>;
 164         status = "okay";
 165
 166         ptn5110: tcpc@50 {
 167                 compatible = "nxp,ptn5110";
 168                 pinctrl-names = "default";
 169                 pinctrl-0 = <&pinctrl_typec1>;
 170                 reg = <0x50>;
 171                 interrupt-parent = <&gpio2>;
 172                 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 173                 status = "okay";
 174
 175                 port {
 176                         typec1_dr_sw: endpoint {
 177                                 remote-endpoint = <&usb1_drd_sw>;
 178                         };
 179                 };
 180
 181                 typec1_con: connector {
 182                         compatible = "usb-c-connector";
 183                         label = "USB-C";
 184                         power-role = "dual";
 185                         data-role = "dual";
 186                         try-power-role = "sink";
 187                         source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
 188                         sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
 189                                      PDO_VAR(5000, 20000, 3000)>;
 190                         op-sink-microwatt = <15000000>;
 191                         self-powered;
 192                 };
 193         };
 194 };
 195
 196 &i2c3 {
 197         clock-frequency = <400000>;
 198         pinctrl-names = "default";
 199         pinctrl-0 = <&pinctrl_i2c3>;
 200         status = "okay";
 201
 202         pca6416: gpio@20 {
 203                 compatible = "ti,tca6416";
 204                 reg = <0x20>;
 205                 gpio-controller;
 206                 #gpio-cells = <2>;
 207         };
 208 };
 209
 210 &sai2 {
 211         #sound-dai-cells = <0>;
 212         pinctrl-names = "default";
 213         pinctrl-0 = <&pinctrl_sai2>;
 214         assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
 215         assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
 216         assigned-clock-rates = <24576000>;
 217         status = "okay";
 218 };
 219
 220 &sai3 {
 221         pinctrl-names = "default";
 222         pinctrl-0 = <&pinctrl_sai3>;
 223         assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
 224         assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
 225         assigned-clock-rates = <24576000>;
 226         fsl,sai-mclk-direction-output;
 227         status = "okay";
 228 };
 229
 230 &snvs_pwrkey {
 231         status = "okay";
 232 };
 233
 234 &spdif1 {
 235         pinctrl-names = "default";
 236         pinctrl-0 = <&pinctrl_spdif1>;
 237         assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
 238         assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
 239         assigned-clock-rates = <24576000>;
 240         status = "okay";
 241 };
 242
 243 &uart2 { /* console */
 244         pinctrl-names = "default";
 245         pinctrl-0 = <&pinctrl_uart2>;
 246         status = "okay";
 247 };
 248
 249 &uart3 {
 250         pinctrl-names = "default";
 251         pinctrl-0 = <&pinctrl_uart3>;
 252         assigned-clocks = <&clk IMX8MN_CLK_UART3>;
 253         assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
 254         uart-has-rtscts;
 255         status = "okay";
 256 };
 257
 258 &usbotg1 {
 259         dr_mode = "otg";
 260         hnp-disable;
 261         srp-disable;
 262         adp-disable;
 263         usb-role-switch;
 264         disable-over-current;
 265         samsung,picophy-pre-emp-curr-control = <3>;
 266         samsung,picophy-dc-vol-level-adjust = <7>;
 267         status = "okay";
 268
 269         port {
 270                 usb1_drd_sw: endpoint {
 271                         remote-endpoint = <&typec1_dr_sw>;
 272                 };
 273         };
 274 };
 275
 276 &usdhc2 {
 277         assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
 278         assigned-clock-rates = <200000000>;
 279         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 280         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 281         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 282         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 283         cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 284         bus-width = <4>;
 285         vmmc-supply = <&reg_usdhc2_vmmc>;
 286         status = "okay";
 287 };
 288
 289 &usdhc3 {
 290         assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
 291         assigned-clock-rates = <400000000>;
 292         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 293         pinctrl-0 = <&pinctrl_usdhc3>;
 294         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 295         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 296         bus-width = <8>;
 297         non-removable;
 298         status = "okay";
 299 };
 300
 301 &wdog1 {
 302         pinctrl-names = "default";
 303         pinctrl-0 = <&pinctrl_wdog>;
 304         fsl,ext-reset-output;
 305         status = "okay";
 306 };
 307
 308 &iomuxc {
 309         pinctrl_fec1: fec1grp {
 310                 fsl,pins = <
 311                         MX8MN_IOMUXC_ENET_MDC_ENET1_MDC         0x3
 312                         MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
 313                         MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
 314                         MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
 315                         MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
 316                         MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
 317                         MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
 318                         MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
 319                         MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
 320                         MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
 321                         MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
 322                         MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
 323                         MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 324                         MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 325                         MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
 326                 >;
 327         };
 328
 329         pinctrl_flexspi: flexspigrp {
 330                 fsl,pins = <
 331                         MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
 332                         MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
 333                         MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
 334                         MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
 335                         MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
 336                         MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
 337                 >;
 338         };
 339
 340         pinctrl_gpio_led: gpioledgrp {
 341                 fsl,pins = <
 342                         MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16    0x19
 343                 >;
 344         };
 345
 346         pinctrl_gpio_wlf: gpiowlfgrp {
 347                 fsl,pins = <
 348                         MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21        0xd6
 349                 >;
 350         };
 351
 352         pinctrl_ir: irgrp {
 353                 fsl,pins = <
 354                         MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
 355                 >;
 356         };
 357
 358         pinctrl_i2c1: i2c1grp {
 359                 fsl,pins = <
 360                         MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 361                         MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 362                 >;
 363         };
 364
 365         pinctrl_i2c2: i2c2grp {
 366                 fsl,pins = <
 367                         MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c3
 368                         MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c3
 369                 >;
 370         };
 371
 372         pinctrl_i2c3: i2c3grp {
 373                 fsl,pins = <
 374                         MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 375                         MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 376                 >;
 377         };
 378
 379         pinctrl_pmic: pmicirqgrp {
 380                 fsl,pins = <
 381                         MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x141
 382                 >;
 383         };
 384
 385         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 386                 fsl,pins = <
 387                         MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
 388                 >;
 389         };
 390
 391         pinctrl_sai2: sai2grp {
 392                 fsl,pins = <
 393                         MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
 394                         MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
 395                         MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
 396                         MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6
 397                 >;
 398         };
 399
 400         pinctrl_sai3: sai3grp {
 401                 fsl,pins = <
 402                         MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
 403                         MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
 404                         MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
 405                         MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
 406                 >;
 407         };
 408
 409         pinctrl_spdif1: spdif1grp {
 410                 fsl,pins = <
 411                         MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT        0xd6
 412                         MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN         0xd6
 413                 >;
 414         };
 415
 416         pinctrl_typec1: typec1grp {
 417                 fsl,pins = <
 418                         MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11      0x159
 419                 >;
 420         };
 421
 422         pinctrl_uart2: uart2grp {
 423                 fsl,pins = <
 424                         MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
 425                         MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
 426                 >;
 427         };
 428
 429         pinctrl_uart3: uart3grp {
 430                 fsl,pins = <
 431                         MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX           0x140
 432                         MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX           0x140
 433                         MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
 434                         MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B        0x140
 435                 >;
 436         };
 437
 438         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 439                 fsl,pins = <
 440                         MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x1c4
 441                 >;
 442         };
 443
 444         pinctrl_usdhc2: usdhc2grp {
 445                 fsl,pins = <
 446                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 447                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 448                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 449                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 450                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 451                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 452                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 453                 >;
 454         };
 455
 456         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 457                 fsl,pins = <
 458                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 459                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 460                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 461                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 462                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 463                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 464                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 465                 >;
 466         };
 467
 468         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 469                 fsl,pins = <
 470                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 471                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 472                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 473                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 474                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 475                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 476                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 477                 >;
 478         };
 479
 480         pinctrl_usdhc3: usdhc3grp {
 481                 fsl,pins = <
 482                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000190
 483                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
 484                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
 485                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
 486                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
 487                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
 488                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
 489                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
 490                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
 491                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
 492                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
 493                 >;
 494         };
 495
 496         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 497                 fsl,pins = <
 498                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000194
 499                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
 500                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
 501                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
 502                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
 503                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
 504                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
 505                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
 506                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
 507                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
 508                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
 509                 >;
 510         };
 511
 512         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 513                 fsl,pins = <
 514                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000196
 515                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
 516                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
 517                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
 518                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
 519                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
 520                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
 521                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
 522                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
 523                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
 524                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
 525                 >;
 526         };
 527
 528         pinctrl_wdog: wdoggrp {
 529                 fsl,pins = <
 530                         MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0x166
 531                 >;
 532         };
 533 };