arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2021 Collabora Ltd.
   4  * Copyright 2021 BSH Hausgeraete GmbH
   5  */
   6
   7 /dts-v1/;
   8
   9 #include "imx8mn-bsh-smm-s2-common.dtsi"
  10 #include <dt-bindings/sound/tlv320aic31xx.h>
  11
  12 / {
  13         model = "BSH SMM S2 PRO";
  14         compatible = "bsh,imx8mn-bsh-smm-s2pro", "fsl,imx8mn";
  15
  16         memory@40000000 {
  17                 device_type = "memory";
  18                 reg = <0x0 0x40000000 0x0 0x20000000>;
  19         };
  20
  21         sound-tlv320aic31xx {
  22                 compatible = "fsl,imx-audio-tlv320aic31xx";
  23                 model = "tlv320aic31xx-hifi";
  24                 audio-cpu = <&sai3>;
  25                 audio-codec = <&tlv320dac3101>;
  26                 audio-asrc = <&easrc>;
  27                 audio-routing =
  28                         "Ext Spk", "SPL",
  29                         "Ext Spk", "SPR";
  30                 mclk-id = <PLL_CLKIN_BCLK>;
  31         };
  32
  33         vdd_input: vdd_input {
  34                 compatible = "regulator-fixed";
  35                 regulator-name = "vdd_input";
  36                 regulator-min-microvolt = <5000000>;
  37                 regulator-max-microvolt = <5000000>;
  38         };
  39 };
  40
  41 &easrc {
  42         fsl,asrc-rate = <48000>;
  43         fsl,asrc-format = <10>;
  44         status = "okay";
  45 };
  46
  47 &i2c2 {
  48         clock-frequency = <400000>;
  49         pinctrl-names = "default";
  50         pinctrl-0 = <&pinctrl_i2c2>;
  51         status = "okay";
  52
  53         tlv320dac3101: audio-codec@18 {
  54                 compatible = "ti,tlv320dac3101";
  55                 pinctrl-names = "default";
  56                 pinctrl-0 = <&pinctrl_dac_rst>;
  57                 reg = <0x18>;
  58                 #sound-dai-cells = <0>;
  59                 HPVDD-supply = <&buck4_reg>;
  60                 SPRVDD-supply = <&vdd_input>;
  61                 SPLVDD-supply = <&vdd_input>;
  62                 AVDD-supply = <&buck4_reg>;
  63                 IOVDD-supply = <&buck4_reg>;
  64                 DVDD-supply = <&buck5_reg>;
  65                 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
  66                 ai31xx-micbias-vg = <MICBIAS_AVDDV>;
  67                 clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
  68         };
  69 };
  70
  71 &sai3 {
  72         pinctrl-names = "default";
  73         pinctrl-0 = <&pinctrl_sai3>;
  74         assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
  75         assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
  76         assigned-clock-rates = <24576000>;
  77         fsl,sai-mclk-direction-output;
  78         status = "okay";
  79 };
  80
  81 /* eMMC */
  82 &usdhc1 {
  83         pinctrl-names = "default", "state_100mhz", "state_200mhz";
  84         pinctrl-0 = <&pinctrl_usdhc1>;
  85         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  86         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  87         bus-width = <8>;
  88         non-removable;
  89         status = "okay";
  90 };
  91
  92 &iomuxc {
  93         pinctrl_dac_rst: dacrstgrp {
  94                 fsl,pins = <
  95                         MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6               0x19 /* DAC_RST */
  96                 >;
  97         };
  98
  99         pinctrl_espi2: espi2grp {
 100                 fsl,pins = <
 101                         MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK            0x082
 102                         MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI            0x082
 103                         MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO            0x082
 104                         MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0              0x040
 105                 >;
 106         };
 107
 108         pinctrl_i2c2: i2c2grp {
 109                 fsl,pins = <
 110                         MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL                  0x400000c3
 111                         MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA                  0x400000c3
 112                 >;
 113         };
 114
 115         pinctrl_sai3: sai3grp {
 116                 fsl,pins = <
 117                         MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC             0xd6
 118                         MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK              0xd6
 119                         MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0             0xd6
 120                 >;
 121         };
 122
 123         pinctrl_usdhc1: usdhc1grp {
 124                 fsl,pins = <
 125                         MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK                 0x40000090
 126                         MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD                 0x0d0
 127                         MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0             0x0d0
 128                         MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1             0x0d0
 129                         MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2             0x0d0
 130                         MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3             0x0d0
 131                         MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4             0x0d0
 132                         MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5             0x0d0
 133                         MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6             0x0d0
 134                         MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7             0x0d0
 135                         MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x090
 136                 >;
 137         };
 138
 139         pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 140                 fsl,pins = <
 141                         MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK                 0x40000094
 142                         MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD                 0x0d4
 143                         MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0             0x0d4
 144                         MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1             0x0d4
 145                         MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2             0x0d4
 146                         MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3             0x0d4
 147                         MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4             0x0d4
 148                         MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5             0x0d4
 149                         MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6             0x0d4
 150                         MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7             0x0d4
 151                         MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x094
 152                 >;
 153         };
 154
 155         pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 156                 fsl,pins = <
 157                         MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK                 0x40000096
 158                         MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD                 0x0d6
 159                         MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0             0x0d6
 160                         MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1             0x0d6
 161                         MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2             0x0d6
 162                         MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3             0x0d6
 163                         MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4             0x0d6
 164                         MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5             0x0d6
 165                         MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6             0x0d6
 166                         MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7             0x0d6
 167                         MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x096
 168                 >;
 169         };
 170 };