1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright 2020 Compass Electronics Group, LLC
13 usdhc1_pwrseq: usdhc1_pwrseq {
14 compatible = "mmc-pwrseq-simple";
15 pinctrl-names = "default";
16 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
17 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
19 clock-names = "ext_clock";
20 post-power-on-delay-ms = <80>;
24 device_type = "memory";
25 reg = <0x0 0x40000000 0 0x80000000>;
30 cpu-supply = <&buck2_reg>;
34 cpu-supply = <&buck2_reg>;
38 cpu-supply = <&buck2_reg>;
42 cpu-supply = <&buck2_reg>;
45 /* DDR controller is running LPDDR at 800MHz which requires 0.95V */
48 opp-microvolt = <950000>;
53 operating-points-v2 = <&ddrc_opp_table>;
55 ddrc_opp_table: opp-table {
56 compatible = "operating-points-v2";
59 opp-hz = /bits/ 64 <25000000>;
63 opp-hz = /bits/ 64 <100000000>;
67 opp-hz = /bits/ 64 <800000000>;
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_fec1>;
75 phy-mode = "rgmii-id";
76 phy-handle = <ðphy0>;
77 phy-supply = <&buck6_reg>;
78 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
86 ethphy0: ethernet-phy@0 {
87 compatible = "ethernet-phy-ieee802.3-c22";
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_flexspi>;
100 #address-cells = <1>;
102 compatible = "jedec,spi-nor";
103 spi-max-frequency = <80000000>;
104 spi-tx-bus-width = <1>;
105 spi-rx-bus-width = <4>;
110 clock-frequency = <400000>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_i2c1>;
116 compatible = "rohm,bd71847";
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_pmic>;
120 interrupt-parent = <&gpio1>;
121 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
122 rohm,reset-snvs-powered;
125 clock-output-names = "clk-32k-out";
129 regulator-name = "buck1";
130 regulator-min-microvolt = <700000>;
131 regulator-max-microvolt = <1300000>;
134 regulator-ramp-delay = <1250>;
138 regulator-name = "buck2";
139 regulator-min-microvolt = <700000>;
140 regulator-max-microvolt = <1300000>;
143 regulator-ramp-delay = <1250>;
144 rohm,dvs-run-voltage = <1000000>;
145 rohm,dvs-idle-voltage = <900000>;
149 // BUCK5 in datasheet
150 regulator-name = "buck3";
151 regulator-min-microvolt = <700000>;
152 regulator-max-microvolt = <1350000>;
158 // BUCK6 in datasheet
159 regulator-name = "buck4";
160 regulator-min-microvolt = <3000000>;
161 regulator-max-microvolt = <3300000>;
167 // BUCK7 in datasheet
168 regulator-name = "buck5";
169 regulator-min-microvolt = <1605000>;
170 regulator-max-microvolt = <1995000>;
176 // BUCK8 in datasheet
177 regulator-name = "buck6";
178 regulator-min-microvolt = <800000>;
179 regulator-max-microvolt = <1400000>;
185 regulator-name = "ldo1";
186 regulator-min-microvolt = <1600000>;
187 regulator-max-microvolt = <3300000>;
193 regulator-name = "ldo2";
194 regulator-min-microvolt = <800000>;
195 regulator-max-microvolt = <900000>;
201 regulator-name = "ldo3";
202 regulator-min-microvolt = <1800000>;
203 regulator-max-microvolt = <3300000>;
209 regulator-name = "ldo4";
210 regulator-min-microvolt = <900000>;
211 regulator-max-microvolt = <1800000>;
217 regulator-name = "ldo6";
218 regulator-min-microvolt = <900000>;
219 regulator-max-microvolt = <1800000>;
228 clock-frequency = <400000>;
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_i2c3>;
234 compatible = "microchip,24c64", "atmel,24c64";
236 read-only; /* Manufacturing EEPROM programmed at factory */
241 compatible = "nxp,pcf85263";
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_uart1>;
249 assigned-clocks = <&clk IMX8MN_CLK_UART1>;
250 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
255 compatible = "brcm,bcm43438-bt";
256 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
257 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
258 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
260 max-speed = <4000000>;
261 clock-names = "extclk";
266 #address-cells = <1>;
268 pinctrl-names = "default", "state_100mhz", "state_200mhz";
269 pinctrl-0 = <&pinctrl_usdhc1>;
270 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
271 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
272 vmmc-supply = <&buck4_reg>;
273 vqmmc-supply = <&buck5_reg>;
277 keep-power-in-suspend;
278 mmc-pwrseq = <&usdhc1_pwrseq>;
283 compatible = "brcm,bcm4329-fmac";
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_wlan>;
286 interrupt-parent = <&gpio2>;
287 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
288 interrupt-names = "host-wake";
293 pinctrl-names = "default", "state_100mhz", "state_200mhz";
294 pinctrl-0 = <&pinctrl_usdhc3>;
295 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
296 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_wdog>;
305 fsl,ext-reset-output;
310 pinctrl_fec1: fec1grp {
312 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
313 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
314 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
315 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
316 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
317 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
318 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
319 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
320 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
321 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
322 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
323 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
324 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
325 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
326 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
330 pinctrl_i2c1: i2c1grp {
332 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
333 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
337 pinctrl_i2c3: i2c3grp {
339 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
340 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
344 pinctrl_flexspi: flexspigrp {
346 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
347 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
348 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
349 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
350 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
351 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
355 pinctrl_pmic: pmicirqgrp {
357 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
361 pinctrl_uart1: uart1grp {
363 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
364 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
365 MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
366 MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
367 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
368 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19
369 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19
370 MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
374 pinctrl_usdhc1_gpio: usdhc1gpiogrp {
376 MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
380 pinctrl_usdhc1: usdhc1grp {
382 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
383 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
384 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
385 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
386 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
387 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
391 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
393 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
394 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
395 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
396 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
397 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
398 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
402 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
404 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
405 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
406 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
407 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
408 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
409 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
413 pinctrl_usdhc3: usdhc3grp {
415 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
416 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
417 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
418 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
419 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
420 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
421 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
422 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
423 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
424 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
425 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
429 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
431 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
432 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
433 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
434 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
435 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
436 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
437 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
438 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
439 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
440 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
441 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
445 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
447 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
448 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
449 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
450 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
451 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
452 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
453 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
454 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
455 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
456 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
457 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
461 pinctrl_wdog: wdoggrp {
463 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
467 pinctrl_wlan: wlangrp {
469 MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111