1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/imx8mm-power.h>
11 #include <dt-bindings/reset/imx8mq-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mm-pinfunc.h"
17 interrupt-parent = <&gic>;
49 entry-method = "psci";
51 cpu_pd_wait: cpu-pd-wait {
52 compatible = "arm,idle-state";
53 arm,psci-suspend-param = <0x0010033>;
55 entry-latency-us = <1000>;
56 exit-latency-us = <700>;
57 min-residency-us = <2700>;
63 compatible = "arm,cortex-a53";
65 clock-latency = <61036>; /* two CLK32 periods */
66 clocks = <&clk IMX8MM_CLK_ARM>;
67 enable-method = "psci";
68 i-cache-size = <0x8000>;
69 i-cache-line-size = <64>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
74 next-level-cache = <&A53_L2>;
75 operating-points-v2 = <&a53_opp_table>;
76 nvmem-cells = <&cpu_speed_grade>;
77 nvmem-cell-names = "speed_grade";
78 cpu-idle-states = <&cpu_pd_wait>;
84 compatible = "arm,cortex-a53";
86 clock-latency = <61036>; /* two CLK32 periods */
87 clocks = <&clk IMX8MM_CLK_ARM>;
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
95 next-level-cache = <&A53_L2>;
96 operating-points-v2 = <&a53_opp_table>;
97 cpu-idle-states = <&cpu_pd_wait>;
103 compatible = "arm,cortex-a53";
105 clock-latency = <61036>; /* two CLK32 periods */
106 clocks = <&clk IMX8MM_CLK_ARM>;
107 enable-method = "psci";
108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
114 next-level-cache = <&A53_L2>;
115 operating-points-v2 = <&a53_opp_table>;
116 cpu-idle-states = <&cpu_pd_wait>;
117 #cooling-cells = <2>;
122 compatible = "arm,cortex-a53";
124 clock-latency = <61036>; /* two CLK32 periods */
125 clocks = <&clk IMX8MM_CLK_ARM>;
126 enable-method = "psci";
127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&A53_L2>;
134 operating-points-v2 = <&a53_opp_table>;
135 cpu-idle-states = <&cpu_pd_wait>;
136 #cooling-cells = <2>;
140 compatible = "cache";
142 cache-size = <0x80000>;
143 cache-line-size = <64>;
148 a53_opp_table: opp-table {
149 compatible = "operating-points-v2";
153 opp-hz = /bits/ 64 <1200000000>;
154 opp-microvolt = <850000>;
155 opp-supported-hw = <0xe>, <0x7>;
156 clock-latency-ns = <150000>;
161 opp-hz = /bits/ 64 <1600000000>;
162 opp-microvolt = <950000>;
163 opp-supported-hw = <0xc>, <0x7>;
164 clock-latency-ns = <150000>;
169 opp-hz = /bits/ 64 <1800000000>;
170 opp-microvolt = <1000000>;
171 opp-supported-hw = <0x8>, <0x3>;
172 clock-latency-ns = <150000>;
177 osc_32k: clock-osc-32k {
178 compatible = "fixed-clock";
180 clock-frequency = <32768>;
181 clock-output-names = "osc_32k";
184 osc_24m: clock-osc-24m {
185 compatible = "fixed-clock";
187 clock-frequency = <24000000>;
188 clock-output-names = "osc_24m";
191 clk_ext1: clock-ext1 {
192 compatible = "fixed-clock";
194 clock-frequency = <133000000>;
195 clock-output-names = "clk_ext1";
198 clk_ext2: clock-ext2 {
199 compatible = "fixed-clock";
201 clock-frequency = <133000000>;
202 clock-output-names = "clk_ext2";
205 clk_ext3: clock-ext3 {
206 compatible = "fixed-clock";
208 clock-frequency = <133000000>;
209 clock-output-names = "clk_ext3";
212 clk_ext4: clock-ext4 {
213 compatible = "fixed-clock";
215 clock-frequency = <133000000>;
216 clock-output-names = "clk_ext4";
220 compatible = "arm,psci-1.0";
225 compatible = "arm,cortex-a53-pmu";
226 interrupts = <GIC_PPI 7
227 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
231 compatible = "arm,armv8-timer";
232 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
233 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
234 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
235 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
236 clock-frequency = <8000000>;
237 arm,no-tick-in-suspend;
242 polling-delay-passive = <250>;
243 polling-delay = <2000>;
244 thermal-sensors = <&tmu>;
247 temperature = <85000>;
253 temperature = <95000>;
261 trip = <&cpu_alert0>;
263 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
264 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
265 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
266 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
272 usbphynop1: usbphynop1 {
274 compatible = "usb-nop-xceiv";
275 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
276 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
277 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
278 clock-names = "main_clk";
279 power-domains = <&pgc_otg1>;
282 usbphynop2: usbphynop2 {
284 compatible = "usb-nop-xceiv";
285 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
286 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
287 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
288 clock-names = "main_clk";
289 power-domains = <&pgc_otg2>;
293 compatible = "fsl,imx8mm-soc", "simple-bus";
294 #address-cells = <1>;
296 ranges = <0x0 0x0 0x0 0x3e000000>;
297 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
298 nvmem-cells = <&imx8mm_uid>;
299 nvmem-cell-names = "soc_unique_id";
301 aips1: bus@30000000 {
302 compatible = "fsl,aips-bus", "simple-bus";
303 reg = <0x30000000 0x400000>;
304 #address-cells = <1>;
306 ranges = <0x30000000 0x30000000 0x400000>;
308 spba2: spba-bus@30000000 {
309 compatible = "fsl,spba-bus", "simple-bus";
310 #address-cells = <1>;
312 reg = <0x30000000 0x100000>;
316 #sound-dai-cells = <0>;
317 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
318 reg = <0x30010000 0x10000>;
319 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
321 <&clk IMX8MM_CLK_SAI1_ROOT>,
322 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
323 clock-names = "bus", "mclk1", "mclk2", "mclk3";
324 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
325 dma-names = "rx", "tx";
330 #sound-dai-cells = <0>;
331 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
332 reg = <0x30020000 0x10000>;
333 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
335 <&clk IMX8MM_CLK_SAI2_ROOT>,
336 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
337 clock-names = "bus", "mclk1", "mclk2", "mclk3";
338 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
339 dma-names = "rx", "tx";
344 #sound-dai-cells = <0>;
345 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
346 reg = <0x30030000 0x10000>;
347 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
349 <&clk IMX8MM_CLK_SAI3_ROOT>,
350 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
351 clock-names = "bus", "mclk1", "mclk2", "mclk3";
352 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
353 dma-names = "rx", "tx";
358 #sound-dai-cells = <0>;
359 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
360 reg = <0x30050000 0x10000>;
361 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
363 <&clk IMX8MM_CLK_SAI5_ROOT>,
364 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
365 clock-names = "bus", "mclk1", "mclk2", "mclk3";
366 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
367 dma-names = "rx", "tx";
372 #sound-dai-cells = <0>;
373 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
374 reg = <0x30060000 0x10000>;
375 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
377 <&clk IMX8MM_CLK_SAI6_ROOT>,
378 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
379 clock-names = "bus", "mclk1", "mclk2", "mclk3";
380 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
381 dma-names = "rx", "tx";
385 micfil: audio-controller@30080000 {
386 compatible = "fsl,imx8mm-micfil";
387 reg = <0x30080000 0x10000>;
388 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
390 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&clk IMX8MM_CLK_PDM_IPG>,
393 <&clk IMX8MM_CLK_PDM_ROOT>,
394 <&clk IMX8MM_AUDIO_PLL1_OUT>,
395 <&clk IMX8MM_AUDIO_PLL2_OUT>,
396 <&clk IMX8MM_CLK_EXT3>;
397 clock-names = "ipg_clk", "ipg_clk_app",
398 "pll8k", "pll11k", "clkext3";
399 dmas = <&sdma2 24 25 0x80000000>;
401 #sound-dai-cells = <0>;
405 spdif1: spdif@30090000 {
406 compatible = "fsl,imx35-spdif";
407 reg = <0x30090000 0x10000>;
408 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
410 <&clk IMX8MM_CLK_24M>, /* rxtx0 */
411 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
412 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
413 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
414 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
415 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
416 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
417 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
418 <&clk IMX8MM_CLK_DUMMY>; /* spba */
419 clock-names = "core", "rxtx0",
424 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
425 dma-names = "rx", "tx";
430 gpio1: gpio@30200000 {
431 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
432 reg = <0x30200000 0x10000>;
433 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
438 interrupt-controller;
439 #interrupt-cells = <2>;
440 gpio-ranges = <&iomuxc 0 10 30>;
443 gpio2: gpio@30210000 {
444 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
445 reg = <0x30210000 0x10000>;
446 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
451 interrupt-controller;
452 #interrupt-cells = <2>;
453 gpio-ranges = <&iomuxc 0 40 21>;
456 gpio3: gpio@30220000 {
457 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
458 reg = <0x30220000 0x10000>;
459 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
464 interrupt-controller;
465 #interrupt-cells = <2>;
466 gpio-ranges = <&iomuxc 0 61 26>;
469 gpio4: gpio@30230000 {
470 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
471 reg = <0x30230000 0x10000>;
472 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
477 interrupt-controller;
478 #interrupt-cells = <2>;
479 gpio-ranges = <&iomuxc 0 87 32>;
482 gpio5: gpio@30240000 {
483 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
484 reg = <0x30240000 0x10000>;
485 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
492 gpio-ranges = <&iomuxc 0 119 30>;
496 compatible = "fsl,imx8mm-tmu";
497 reg = <0x30260000 0x10000>;
498 clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
499 #thermal-sensor-cells = <0>;
502 wdog1: watchdog@30280000 {
503 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
504 reg = <0x30280000 0x10000>;
505 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
510 wdog2: watchdog@30290000 {
511 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
512 reg = <0x30290000 0x10000>;
513 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
518 wdog3: watchdog@302a0000 {
519 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
520 reg = <0x302a0000 0x10000>;
521 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
526 sdma2: dma-controller@302c0000 {
527 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
528 reg = <0x302c0000 0x10000>;
529 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
531 <&clk IMX8MM_CLK_SDMA2_ROOT>;
532 clock-names = "ipg", "ahb";
534 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
537 sdma3: dma-controller@302b0000 {
538 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
539 reg = <0x302b0000 0x10000>;
540 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
542 <&clk IMX8MM_CLK_SDMA3_ROOT>;
543 clock-names = "ipg", "ahb";
545 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
548 iomuxc: pinctrl@30330000 {
549 compatible = "fsl,imx8mm-iomuxc";
550 reg = <0x30330000 0x10000>;
553 gpr: iomuxc-gpr@30340000 {
554 compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
555 reg = <0x30340000 0x10000>;
558 ocotp: efuse@30350000 {
559 compatible = "fsl,imx8mm-ocotp", "syscon";
560 reg = <0x30350000 0x10000>;
561 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
562 /* For nvmem subnodes */
563 #address-cells = <1>;
566 imx8mm_uid: unique-id@4 {
570 cpu_speed_grade: speed-grade@10 {
574 fec_mac_address: mac-address@90 {
579 anatop: anatop@30360000 {
580 compatible = "fsl,imx8mm-anatop", "syscon";
581 reg = <0x30360000 0x10000>;
584 snvs: snvs@30370000 {
585 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
586 reg = <0x30370000 0x10000>;
588 snvs_rtc: snvs-rtc-lp {
589 compatible = "fsl,sec-v4.0-mon-rtc-lp";
592 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
595 clock-names = "snvs-rtc";
598 snvs_pwrkey: snvs-powerkey {
599 compatible = "fsl,sec-v4.0-pwrkey";
601 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
603 clock-names = "snvs-pwrkey";
604 linux,keycode = <KEY_POWER>;
609 snvs_lpgpr: snvs-lpgpr {
610 compatible = "fsl,imx8mm-snvs-lpgpr",
611 "fsl,imx7d-snvs-lpgpr";
615 clk: clock-controller@30380000 {
616 compatible = "fsl,imx8mm-ccm";
617 reg = <0x30380000 0x10000>;
619 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
620 <&clk_ext3>, <&clk_ext4>;
621 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
622 "clk_ext3", "clk_ext4";
623 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
624 <&clk IMX8MM_CLK_A53_CORE>,
625 <&clk IMX8MM_CLK_NOC>,
626 <&clk IMX8MM_CLK_AUDIO_AHB>,
627 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
628 <&clk IMX8MM_SYS_PLL3>,
629 <&clk IMX8MM_VIDEO_PLL1>,
630 <&clk IMX8MM_AUDIO_PLL1>;
631 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
632 <&clk IMX8MM_ARM_PLL_OUT>,
633 <&clk IMX8MM_SYS_PLL3_OUT>,
634 <&clk IMX8MM_SYS_PLL1_800M>;
635 assigned-clock-rates = <0>, <0>, <0>,
643 src: reset-controller@30390000 {
644 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
645 reg = <0x30390000 0x10000>;
646 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
651 compatible = "fsl,imx8mm-gpc";
652 reg = <0x303a0000 0x10000>;
653 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
654 interrupt-parent = <&gic>;
655 interrupt-controller;
656 #interrupt-cells = <3>;
659 #address-cells = <1>;
662 pgc_hsiomix: power-domain@0 {
663 #power-domain-cells = <0>;
664 reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
665 clocks = <&clk IMX8MM_CLK_USB_BUS>;
666 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
667 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
670 pgc_pcie: power-domain@1 {
671 #power-domain-cells = <0>;
672 reg = <IMX8MM_POWER_DOMAIN_PCIE>;
673 power-domains = <&pgc_hsiomix>;
674 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
677 pgc_otg1: power-domain@2 {
678 #power-domain-cells = <0>;
679 reg = <IMX8MM_POWER_DOMAIN_OTG1>;
682 pgc_otg2: power-domain@3 {
683 #power-domain-cells = <0>;
684 reg = <IMX8MM_POWER_DOMAIN_OTG2>;
687 pgc_gpumix: power-domain@4 {
688 #power-domain-cells = <0>;
689 reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
690 clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
691 <&clk IMX8MM_CLK_GPU_AHB>;
692 assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
693 <&clk IMX8MM_CLK_GPU_AHB>;
694 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
695 <&clk IMX8MM_SYS_PLL1_800M>;
696 assigned-clock-rates = <800000000>, <400000000>;
699 pgc_gpu: power-domain@5 {
700 #power-domain-cells = <0>;
701 reg = <IMX8MM_POWER_DOMAIN_GPU>;
702 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
703 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
704 <&clk IMX8MM_CLK_GPU2D_ROOT>,
705 <&clk IMX8MM_CLK_GPU3D_ROOT>;
706 resets = <&src IMX8MQ_RESET_GPU_RESET>;
707 power-domains = <&pgc_gpumix>;
710 pgc_vpumix: power-domain@6 {
711 #power-domain-cells = <0>;
712 reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
713 clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
714 assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
715 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
718 pgc_vpu_g1: power-domain@7 {
719 #power-domain-cells = <0>;
720 reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
723 pgc_vpu_g2: power-domain@8 {
724 #power-domain-cells = <0>;
725 reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
728 pgc_vpu_h1: power-domain@9 {
729 #power-domain-cells = <0>;
730 reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
733 pgc_dispmix: power-domain@10 {
734 #power-domain-cells = <0>;
735 reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
736 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
737 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
738 assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
739 <&clk IMX8MM_CLK_DISP_APB>;
740 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
741 <&clk IMX8MM_SYS_PLL1_800M>;
742 assigned-clock-rates = <500000000>, <200000000>;
745 pgc_mipi: power-domain@11 {
746 #power-domain-cells = <0>;
747 reg = <IMX8MM_POWER_DOMAIN_MIPI>;
753 aips2: bus@30400000 {
754 compatible = "fsl,aips-bus", "simple-bus";
755 reg = <0x30400000 0x400000>;
756 #address-cells = <1>;
758 ranges = <0x30400000 0x30400000 0x400000>;
761 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
762 reg = <0x30660000 0x10000>;
763 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
765 <&clk IMX8MM_CLK_PWM1_ROOT>;
766 clock-names = "ipg", "per";
772 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
773 reg = <0x30670000 0x10000>;
774 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
776 <&clk IMX8MM_CLK_PWM2_ROOT>;
777 clock-names = "ipg", "per";
783 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
784 reg = <0x30680000 0x10000>;
785 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
787 <&clk IMX8MM_CLK_PWM3_ROOT>;
788 clock-names = "ipg", "per";
794 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
795 reg = <0x30690000 0x10000>;
796 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
797 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
798 <&clk IMX8MM_CLK_PWM4_ROOT>;
799 clock-names = "ipg", "per";
804 system_counter: timer@306a0000 {
805 compatible = "nxp,sysctr-timer";
806 reg = <0x306a0000 0x20000>;
807 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
813 aips3: bus@30800000 {
814 compatible = "fsl,aips-bus", "simple-bus";
815 reg = <0x30800000 0x400000>;
816 #address-cells = <1>;
818 ranges = <0x30800000 0x30800000 0x400000>,
819 <0x8000000 0x8000000 0x10000000>;
821 spba1: spba-bus@30800000 {
822 compatible = "fsl,spba-bus", "simple-bus";
823 #address-cells = <1>;
825 reg = <0x30800000 0x100000>;
828 ecspi1: spi@30820000 {
829 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
830 #address-cells = <1>;
832 reg = <0x30820000 0x10000>;
833 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
835 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
836 clock-names = "ipg", "per";
837 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
838 dma-names = "rx", "tx";
842 ecspi2: spi@30830000 {
843 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
844 #address-cells = <1>;
846 reg = <0x30830000 0x10000>;
847 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
849 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
850 clock-names = "ipg", "per";
851 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
852 dma-names = "rx", "tx";
856 ecspi3: spi@30840000 {
857 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
858 #address-cells = <1>;
860 reg = <0x30840000 0x10000>;
861 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
863 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
864 clock-names = "ipg", "per";
865 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
866 dma-names = "rx", "tx";
870 uart1: serial@30860000 {
871 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
872 reg = <0x30860000 0x10000>;
873 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
874 clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
875 <&clk IMX8MM_CLK_UART1_ROOT>;
876 clock-names = "ipg", "per";
877 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
878 dma-names = "rx", "tx";
882 uart3: serial@30880000 {
883 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
884 reg = <0x30880000 0x10000>;
885 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
887 <&clk IMX8MM_CLK_UART3_ROOT>;
888 clock-names = "ipg", "per";
889 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
890 dma-names = "rx", "tx";
894 uart2: serial@30890000 {
895 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
896 reg = <0x30890000 0x10000>;
897 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
899 <&clk IMX8MM_CLK_UART2_ROOT>;
900 clock-names = "ipg", "per";
905 crypto: crypto@30900000 {
906 compatible = "fsl,sec-v4.0";
907 #address-cells = <1>;
909 reg = <0x30900000 0x40000>;
910 ranges = <0 0x30900000 0x40000>;
911 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&clk IMX8MM_CLK_AHB>,
913 <&clk IMX8MM_CLK_IPG_ROOT>;
914 clock-names = "aclk", "ipg";
917 compatible = "fsl,sec-v4.0-job-ring";
918 reg = <0x1000 0x1000>;
919 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
924 compatible = "fsl,sec-v4.0-job-ring";
925 reg = <0x2000 0x1000>;
926 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
930 compatible = "fsl,sec-v4.0-job-ring";
931 reg = <0x3000 0x1000>;
932 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
937 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
938 #address-cells = <1>;
940 reg = <0x30a20000 0x10000>;
941 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
942 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
947 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
948 #address-cells = <1>;
950 reg = <0x30a30000 0x10000>;
951 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
952 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
957 #address-cells = <1>;
959 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
960 reg = <0x30a40000 0x10000>;
961 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
967 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
968 #address-cells = <1>;
970 reg = <0x30a50000 0x10000>;
971 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
972 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
976 uart4: serial@30a60000 {
977 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
978 reg = <0x30a60000 0x10000>;
979 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
981 <&clk IMX8MM_CLK_UART4_ROOT>;
982 clock-names = "ipg", "per";
983 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
984 dma-names = "rx", "tx";
988 mu: mailbox@30aa0000 {
989 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
990 reg = <0x30aa0000 0x10000>;
991 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&clk IMX8MM_CLK_MU_ROOT>;
996 usdhc1: mmc@30b40000 {
997 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
998 reg = <0x30b40000 0x10000>;
999 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1000 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1001 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1002 <&clk IMX8MM_CLK_USDHC1_ROOT>;
1003 clock-names = "ipg", "ahb", "per";
1004 fsl,tuning-start-tap = <20>;
1005 fsl,tuning-step = <2>;
1007 status = "disabled";
1010 usdhc2: mmc@30b50000 {
1011 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1012 reg = <0x30b50000 0x10000>;
1013 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1015 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1016 <&clk IMX8MM_CLK_USDHC2_ROOT>;
1017 clock-names = "ipg", "ahb", "per";
1018 fsl,tuning-start-tap = <20>;
1019 fsl,tuning-step = <2>;
1021 status = "disabled";
1024 usdhc3: mmc@30b60000 {
1025 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1026 reg = <0x30b60000 0x10000>;
1027 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1028 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1029 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1030 <&clk IMX8MM_CLK_USDHC3_ROOT>;
1031 clock-names = "ipg", "ahb", "per";
1032 fsl,tuning-start-tap = <20>;
1033 fsl,tuning-step = <2>;
1035 status = "disabled";
1038 flexspi: spi@30bb0000 {
1039 #address-cells = <1>;
1041 compatible = "nxp,imx8mm-fspi";
1042 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1043 reg-names = "fspi_base", "fspi_mmap";
1044 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
1046 <&clk IMX8MM_CLK_QSPI_ROOT>;
1047 clock-names = "fspi_en", "fspi";
1048 status = "disabled";
1051 sdma1: dma-controller@30bd0000 {
1052 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
1053 reg = <0x30bd0000 0x10000>;
1054 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1055 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
1056 <&clk IMX8MM_CLK_AHB>;
1057 clock-names = "ipg", "ahb";
1059 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
1062 fec1: ethernet@30be0000 {
1063 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1064 reg = <0x30be0000 0x10000>;
1065 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1066 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1067 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1068 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1069 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
1070 <&clk IMX8MM_CLK_ENET1_ROOT>,
1071 <&clk IMX8MM_CLK_ENET_TIMER>,
1072 <&clk IMX8MM_CLK_ENET_REF>,
1073 <&clk IMX8MM_CLK_ENET_PHY_REF>;
1074 clock-names = "ipg", "ahb", "ptp",
1075 "enet_clk_ref", "enet_out";
1076 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
1077 <&clk IMX8MM_CLK_ENET_TIMER>,
1078 <&clk IMX8MM_CLK_ENET_REF>,
1079 <&clk IMX8MM_CLK_ENET_PHY_REF>;
1080 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1081 <&clk IMX8MM_SYS_PLL2_100M>,
1082 <&clk IMX8MM_SYS_PLL2_125M>,
1083 <&clk IMX8MM_SYS_PLL2_50M>;
1084 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1085 fsl,num-tx-queues = <3>;
1086 fsl,num-rx-queues = <3>;
1087 nvmem-cells = <&fec_mac_address>;
1088 nvmem-cell-names = "mac-address";
1089 fsl,stop-mode = <&gpr 0x10 3>;
1090 status = "disabled";
1095 aips4: bus@32c00000 {
1096 compatible = "fsl,aips-bus", "simple-bus";
1097 reg = <0x32c00000 0x400000>;
1098 #address-cells = <1>;
1100 ranges = <0x32c00000 0x32c00000 0x400000>;
1103 compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
1104 reg = <0x32e20000 0x1000>;
1105 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
1107 clock-names = "mclk";
1108 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
1109 status = "disabled";
1113 remote-endpoint = <&imx8mm_mipi_csi_out>;
1118 disp_blk_ctrl: blk-ctrl@32e28000 {
1119 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
1120 reg = <0x32e28000 0x100>;
1121 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1122 <&pgc_dispmix>, <&pgc_mipi>,
1124 power-domain-names = "bus", "csi-bridge",
1125 "lcdif", "mipi-dsi",
1127 clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
1128 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1129 <&clk IMX8MM_CLK_CSI1_ROOT>,
1130 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
1131 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1132 <&clk IMX8MM_CLK_DISP_ROOT>,
1133 <&clk IMX8MM_CLK_DSI_CORE>,
1134 <&clk IMX8MM_CLK_DSI_PHY_REF>,
1135 <&clk IMX8MM_CLK_CSI1_CORE>,
1136 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
1137 clock-names = "csi-bridge-axi","csi-bridge-apb",
1138 "csi-bridge-core", "lcdif-axi",
1139 "lcdif-apb", "lcdif-pix",
1140 "dsi-pclk", "dsi-ref",
1141 "csi-aclk", "csi-pclk";
1142 #power-domain-cells = <1>;
1145 mipi_csi: mipi-csi@32e30000 {
1146 compatible = "fsl,imx8mm-mipi-csi2";
1147 reg = <0x32e30000 0x1000>;
1148 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1149 assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;
1150 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;
1152 clock-frequency = <333000000>;
1153 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1154 <&clk IMX8MM_CLK_CSI1_ROOT>,
1155 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
1156 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
1157 clock-names = "pclk", "wrap", "phy", "axi";
1158 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
1159 status = "disabled";
1162 #address-cells = <1>;
1172 imx8mm_mipi_csi_out: endpoint {
1173 remote-endpoint = <&csi_in>;
1179 usbotg1: usb@32e40000 {
1180 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1181 reg = <0x32e40000 0x200>;
1182 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1183 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
1184 clock-names = "usb1_ctrl_root_clk";
1185 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1186 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1187 phys = <&usbphynop1>;
1188 fsl,usbmisc = <&usbmisc1 0>;
1189 power-domains = <&pgc_hsiomix>;
1190 status = "disabled";
1193 usbmisc1: usbmisc@32e40200 {
1194 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1196 reg = <0x32e40200 0x200>;
1199 usbotg2: usb@32e50000 {
1200 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1201 reg = <0x32e50000 0x200>;
1202 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1203 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
1204 clock-names = "usb1_ctrl_root_clk";
1205 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1206 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1207 phys = <&usbphynop2>;
1208 fsl,usbmisc = <&usbmisc2 0>;
1209 power-domains = <&pgc_hsiomix>;
1210 status = "disabled";
1213 usbmisc2: usbmisc@32e50200 {
1214 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1216 reg = <0x32e50200 0x200>;
1219 pcie_phy: pcie-phy@32f00000 {
1220 compatible = "fsl,imx8mm-pcie-phy";
1221 reg = <0x32f00000 0x10000>;
1222 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1223 clock-names = "ref";
1224 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1225 assigned-clock-rates = <100000000>;
1226 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
1227 resets = <&src IMX8MQ_RESET_PCIEPHY>;
1228 reset-names = "pciephy";
1230 status = "disabled";
1234 dma_apbh: dma-controller@33000000 {
1235 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1236 reg = <0x33000000 0x2000>;
1237 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1241 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1244 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1247 gpmi: nand-controller@33002000 {
1248 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1249 #address-cells = <1>;
1251 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1252 reg-names = "gpmi-nand", "bch";
1253 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1254 interrupt-names = "bch";
1255 clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
1256 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1257 clock-names = "gpmi_io", "gpmi_bch_apb";
1258 dmas = <&dma_apbh 0>;
1259 dma-names = "rx-tx";
1260 status = "disabled";
1263 pcie0: pcie@33800000 {
1264 compatible = "fsl,imx8mm-pcie";
1265 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1266 reg-names = "dbi", "config";
1267 #address-cells = <3>;
1269 device_type = "pci";
1270 bus-range = <0x00 0xff>;
1271 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1272 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1275 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1276 interrupt-names = "msi";
1277 #interrupt-cells = <1>;
1278 interrupt-map-mask = <0 0 0 0x7>;
1279 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1280 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1281 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1282 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1283 fsl,max-link-speed = <2>;
1284 linux,pci-domain = <0>;
1285 power-domains = <&pgc_pcie>;
1286 resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1287 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1288 reset-names = "apps", "turnoff";
1290 phy-names = "pcie-phy";
1291 status = "disabled";
1294 gpu_3d: gpu@38000000 {
1295 compatible = "vivante,gc";
1296 reg = <0x38000000 0x8000>;
1297 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
1299 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
1300 <&clk IMX8MM_CLK_GPU3D_ROOT>,
1301 <&clk IMX8MM_CLK_GPU3D_ROOT>;
1302 clock-names = "reg", "bus", "core", "shader";
1303 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
1304 <&clk IMX8MM_GPU_PLL_OUT>;
1305 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1306 assigned-clock-rates = <0>, <800000000>;
1307 power-domains = <&pgc_gpu>;
1310 gpu_2d: gpu@38008000 {
1311 compatible = "vivante,gc";
1312 reg = <0x38008000 0x8000>;
1313 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1314 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
1315 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
1316 <&clk IMX8MM_CLK_GPU2D_ROOT>;
1317 clock-names = "reg", "bus", "core";
1318 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
1319 <&clk IMX8MM_GPU_PLL_OUT>;
1320 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1321 assigned-clock-rates = <0>, <800000000>;
1322 power-domains = <&pgc_gpu>;
1325 vpu_g1: video-codec@38300000 {
1326 compatible = "nxp,imx8mm-vpu-g1";
1327 reg = <0x38300000 0x10000>;
1328 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1329 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
1330 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
1333 vpu_g2: video-codec@38310000 {
1334 compatible = "nxp,imx8mq-vpu-g2";
1335 reg = <0x38310000 0x10000>;
1336 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1337 clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
1338 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
1341 vpu_blk_ctrl: blk-ctrl@38330000 {
1342 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
1343 reg = <0x38330000 0x100>;
1344 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1345 <&pgc_vpu_g2>, <&pgc_vpu_h1>;
1346 power-domain-names = "bus", "g1", "g2", "h1";
1347 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
1348 <&clk IMX8MM_CLK_VPU_G2_ROOT>,
1349 <&clk IMX8MM_CLK_VPU_H1_ROOT>;
1350 clock-names = "g1", "g2", "h1";
1351 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
1352 <&clk IMX8MM_CLK_VPU_G2>;
1353 assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
1354 <&clk IMX8MM_VPU_PLL_OUT>;
1355 assigned-clock-rates = <600000000>,
1357 #power-domain-cells = <1>;
1360 gic: interrupt-controller@38800000 {
1361 compatible = "arm,gic-v3";
1362 reg = <0x38800000 0x10000>, /* GIC Dist */
1363 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
1364 #interrupt-cells = <3>;
1365 interrupt-controller;
1366 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1369 ddrc: memory-controller@3d400000 {
1370 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
1371 reg = <0x3d400000 0x400000>;
1372 clock-names = "core", "pll", "alt", "apb";
1373 clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
1374 <&clk IMX8MM_DRAM_PLL>,
1375 <&clk IMX8MM_CLK_DRAM_ALT>,
1376 <&clk IMX8MM_CLK_DRAM_APB>;
1380 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
1381 reg = <0x3d800000 0x400000>;
1382 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;