arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /*
   3  * Copyright 2022 Toradex
   4  */
   5
   6 #include "dt-bindings/phy/phy-imx8-pcie.h"
   7 #include "dt-bindings/pwm/pwm.h"
   8 #include "imx8mm.dtsi"
   9
  10 / {
  11         chosen {
  12                 stdout-path = &uart1;
  13         };
  14
  15         aliases {
  16                 rtc0 = &rtc_i2c;
  17                 rtc1 = &snvs_rtc;
  18         };
  19
  20         backlight: backlight {
  21                 compatible = "pwm-backlight";
  22                 brightness-levels = <0 45 63 88 119 158 203 255>;
  23                 default-brightness-level = <4>;
  24                 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
  25                 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
  26                 pinctrl-names = "default";
  27                 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
  28                 power-supply = <&reg_3p3v>;
  29                 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
  30                 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
  31                 status = "disabled";
  32         };
  33
  34         /* Fixed clock dedicated to SPI CAN controller */
  35         clk40m: oscillator {
  36                 compatible = "fixed-clock";
  37                 #clock-cells = <0>;
  38                 clock-frequency = <40000000>;
  39         };
  40
  41         gpio-keys {
  42                 compatible = "gpio-keys";
  43                 pinctrl-names = "default";
  44                 pinctrl-0 = <&pinctrl_gpio_keys>;
  45
  46                 key-wakeup {
  47                         debounce-interval = <10>;
  48                         /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
  49                         gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
  50                         label = "Wake-Up";
  51                         linux,code = <KEY_WAKEUP>;
  52                         wakeup-source;
  53                 };
  54         };
  55
  56         hdmi_connector: hdmi-connector {
  57                 compatible = "hdmi-connector";
  58                 ddc-i2c-bus = <&i2c2>;
  59                 label = "hdmi";
  60                 type = "a";
  61                 status = "disabled";
  62         };
  63
  64         panel_lvds: panel-lvds {
  65                 compatible = "panel-lvds";
  66                 backlight = <&backlight>;
  67                 data-mapping = "vesa-24";
  68                 status = "disabled";
  69         };
  70
  71         /* Carrier Board Supplies */
  72         reg_1p8v: regulator-1p8v {
  73                 compatible = "regulator-fixed";
  74                 regulator-max-microvolt = <1800000>;
  75                 regulator-min-microvolt = <1800000>;
  76                 regulator-name = "+V1.8_SW";
  77         };
  78
  79         reg_3p3v: regulator-3p3v {
  80                 compatible = "regulator-fixed";
  81                 regulator-max-microvolt = <3300000>;
  82                 regulator-min-microvolt = <3300000>;
  83                 regulator-name = "+V3.3_SW";
  84         };
  85
  86         reg_5p0v: regulator-5p0v {
  87                 compatible = "regulator-fixed";
  88                 regulator-max-microvolt = <5000000>;
  89                 regulator-min-microvolt = <5000000>;
  90                 regulator-name = "+V5_SW";
  91         };
  92
  93         /* Non PMIC On-module Supplies */
  94         reg_ethphy: regulator-ethphy {
  95                 compatible = "regulator-fixed";
  96                 enable-active-high;
  97                 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
  98                 off-on-delay-us = <500000>;
  99                 pinctrl-names = "default";
 100                 pinctrl-0 = <&pinctrl_reg_eth>;
 101                 regulator-always-on;
 102                 regulator-boot-on;
 103                 regulator-max-microvolt = <3300000>;
 104                 regulator-min-microvolt = <3300000>;
 105                 regulator-name = "On-module +V3.3_ETH";
 106                 startup-delay-us = <200000>;
 107         };
 108
 109         reg_usb_otg1_vbus: regulator-usb-otg1 {
 110                 compatible = "regulator-fixed";
 111                 enable-active-high;
 112                 /* Verdin USB_1_EN (SODIMM 155) */
 113                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 114                 pinctrl-names = "default";
 115                 pinctrl-0 = <&pinctrl_reg_usb1_en>;
 116                 regulator-max-microvolt = <5000000>;
 117                 regulator-min-microvolt = <5000000>;
 118                 regulator-name = "USB_1_EN";
 119         };
 120
 121         reg_usb_otg2_vbus: regulator-usb-otg2 {
 122                 compatible = "regulator-fixed";
 123                 enable-active-high;
 124                 /* Verdin USB_2_EN (SODIMM 185) */
 125                 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
 126                 pinctrl-names = "default";
 127                 pinctrl-0 = <&pinctrl_reg_usb2_en>;
 128                 regulator-max-microvolt = <5000000>;
 129                 regulator-min-microvolt = <5000000>;
 130                 regulator-name = "USB_2_EN";
 131         };
 132
 133         reg_usdhc2_vmmc: regulator-usdhc2 {
 134                 compatible = "regulator-fixed";
 135                 enable-active-high;
 136                 /* Verdin SD_1_PWR_EN (SODIMM 76) */
 137                 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
 138                 off-on-delay-us = <100000>;
 139                 pinctrl-names = "default";
 140                 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
 141                 regulator-max-microvolt = <3300000>;
 142                 regulator-min-microvolt = <3300000>;
 143                 regulator-name = "+V3.3_SD";
 144                 startup-delay-us = <2000>;
 145         };
 146
 147         reserved-memory {
 148                 #address-cells = <2>;
 149                 #size-cells = <2>;
 150                 ranges;
 151
 152                 /* Use the kernel configuration settings instead */
 153                 /delete-node/ linux,cma;
 154         };
 155 };
 156
 157 &A53_0 {
 158         cpu-supply = <&reg_vdd_arm>;
 159 };
 160
 161 &A53_1 {
 162         cpu-supply = <&reg_vdd_arm>;
 163 };
 164
 165 &A53_2 {
 166         cpu-supply = <&reg_vdd_arm>;
 167 };
 168
 169 &A53_3 {
 170         cpu-supply = <&reg_vdd_arm>;
 171 };
 172
 173 &cpu_alert0 {
 174         temperature = <95000>;
 175 };
 176
 177 &cpu_crit0 {
 178         temperature = <105000>;
 179 };
 180
 181 &ddrc {
 182         operating-points-v2 = <&ddrc_opp_table>;
 183
 184         ddrc_opp_table: opp-table {
 185                 compatible = "operating-points-v2";
 186
 187                 opp-25M {
 188                         opp-hz = /bits/ 64 <25000000>;
 189                 };
 190
 191                 opp-100M {
 192                         opp-hz = /bits/ 64 <100000000>;
 193                 };
 194
 195                 opp-750M {
 196                         opp-hz = /bits/ 64 <750000000>;
 197                 };
 198         };
 199 };
 200
 201 /* Verdin SPI_1 */
 202 &ecspi2 {
 203         #address-cells = <1>;
 204         #size-cells = <0>;
 205         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 206         pinctrl-names = "default";
 207         pinctrl-0 = <&pinctrl_ecspi2>;
 208 };
 209
 210 /* Verdin CAN_1 (On-module) */
 211 &ecspi3 {
 212         #address-cells = <1>;
 213         #size-cells = <0>;
 214         cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_ecspi3>;
 217         status = "okay";
 218
 219         can1: can@0 {
 220                 compatible = "microchip,mcp251xfd";
 221                 clocks = <&clk40m>;
 222                 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
 223                 pinctrl-names = "default";
 224                 pinctrl-0 = <&pinctrl_can1_int>;
 225                 reg = <0>;
 226                 spi-max-frequency = <8500000>;
 227         };
 228 };
 229
 230 /* Verdin ETH_1 (On-module PHY) */
 231 &fec1 {
 232         fsl,magic-packet;
 233         phy-handle = <&ethphy0>;
 234         phy-mode = "rgmii-id";
 235         phy-supply = <&reg_ethphy>;
 236         pinctrl-names = "default", "sleep";
 237         pinctrl-0 = <&pinctrl_fec1>;
 238         pinctrl-1 = <&pinctrl_fec1_sleep>;
 239
 240         mdio {
 241                 #address-cells = <1>;
 242                 #size-cells = <0>;
 243
 244                 ethphy0: ethernet-phy@7 {
 245                         compatible = "ethernet-phy-ieee802.3-c22";
 246                         interrupt-parent = <&gpio1>;
 247                         interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
 248                         micrel,led-mode = <0>;
 249                         reg = <7>;
 250                 };
 251         };
 252 };
 253
 254 /* Verdin QSPI_1 */
 255 &flexspi {
 256         pinctrl-names = "default";
 257         pinctrl-0 = <&pinctrl_flexspi0>;
 258 };
 259
 260 &gpio1 {
 261         gpio-line-names = "SODIMM_216",
 262                           "SODIMM_19",
 263                           "",
 264                           "",
 265                           "",
 266                           "",
 267                           "",
 268                           "",
 269                           "SODIMM_220",
 270                           "SODIMM_222",
 271                           "",
 272                           "SODIMM_218",
 273                           "SODIMM_155",
 274                           "SODIMM_157",
 275                           "SODIMM_185",
 276                           "SODIMM_187";
 277 };
 278
 279 &gpio2 {
 280         gpio-line-names = "",
 281                           "",
 282                           "",
 283                           "",
 284                           "",
 285                           "",
 286                           "",
 287                           "",
 288                           "",
 289                           "",
 290                           "",
 291                           "",
 292                           "SODIMM_84",
 293                           "SODIMM_78",
 294                           "SODIMM_74",
 295                           "SODIMM_80",
 296                           "SODIMM_82",
 297                           "SODIMM_70",
 298                           "SODIMM_72";
 299 };
 300
 301 &gpio5 {
 302         gpio-line-names = "SODIMM_131",
 303                           "",
 304                           "SODIMM_91",
 305                           "SODIMM_16",
 306                           "SODIMM_15",
 307                           "SODIMM_208",
 308                           "SODIMM_137",
 309                           "SODIMM_139",
 310                           "SODIMM_141",
 311                           "SODIMM_143",
 312                           "SODIMM_196",
 313                           "SODIMM_200",
 314                           "SODIMM_198",
 315                           "SODIMM_202",
 316                           "",
 317                           "",
 318                           "SODIMM_55",
 319                           "SODIMM_53",
 320                           "SODIMM_95",
 321                           "SODIMM_93",
 322                           "SODIMM_14",
 323                           "SODIMM_12",
 324                           "",
 325                           "",
 326                           "",
 327                           "",
 328                           "SODIMM_210",
 329                           "SODIMM_212",
 330                           "SODIMM_151",
 331                           "SODIMM_153";
 332
 333         ctrl-sleep-moci-hog {
 334                 gpio-hog;
 335                 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
 336                 gpios = <1 GPIO_ACTIVE_HIGH>;
 337                 line-name = "CTRL_SLEEP_MOCI#";
 338                 output-high;
 339                 pinctrl-names = "default";
 340                 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
 341         };
 342 };
 343
 344 /* On-module I2C */
 345 &i2c1 {
 346         clock-frequency = <400000>;
 347         pinctrl-names = "default", "gpio";
 348         pinctrl-0 = <&pinctrl_i2c1>;
 349         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 350         scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 351         sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 352         status = "okay";
 353
 354         pca9450: pmic@25 {
 355                 compatible = "nxp,pca9450a";
 356                 interrupt-parent = <&gpio1>;
 357                 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
 358                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 359                 pinctrl-names = "default";
 360                 pinctrl-0 = <&pinctrl_pmic>;
 361                 reg = <0x25>;
 362                 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 363
 364                 /*
 365                  * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
 366                  * behind this PMIC.
 367                  */
 368
 369                 regulators {
 370                         reg_vdd_soc: BUCK1 {
 371                                 nxp,dvs-run-voltage = <850000>;
 372                                 nxp,dvs-standby-voltage = <800000>;
 373                                 regulator-always-on;
 374                                 regulator-boot-on;
 375                                 regulator-max-microvolt = <850000>;
 376                                 regulator-min-microvolt = <800000>;
 377                                 regulator-name = "On-module +VDD_SOC (BUCK1)";
 378                                 regulator-ramp-delay = <3125>;
 379                         };
 380
 381                         reg_vdd_arm: BUCK2 {
 382                                 nxp,dvs-run-voltage = <950000>;
 383                                 nxp,dvs-standby-voltage = <850000>;
 384                                 regulator-always-on;
 385                                 regulator-boot-on;
 386                                 regulator-max-microvolt = <1050000>;
 387                                 regulator-min-microvolt = <805000>;
 388                                 regulator-name = "On-module +VDD_ARM (BUCK2)";
 389                                 regulator-ramp-delay = <3125>;
 390                         };
 391
 392                         reg_vdd_dram: BUCK3 {
 393                                 regulator-always-on;
 394                                 regulator-boot-on;
 395                                 regulator-max-microvolt = <1000000>;
 396                                 regulator-min-microvolt = <805000>;
 397                                 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
 398                         };
 399
 400                         reg_vdd_3v3: BUCK4 {
 401                                 regulator-always-on;
 402                                 regulator-boot-on;
 403                                 regulator-max-microvolt = <3300000>;
 404                                 regulator-min-microvolt = <3300000>;
 405                                 regulator-name = "On-module +V3.3 (BUCK4)";
 406                         };
 407
 408                         reg_vdd_1v8: BUCK5 {
 409                                 regulator-always-on;
 410                                 regulator-boot-on;
 411                                 regulator-max-microvolt = <1800000>;
 412                                 regulator-min-microvolt = <1800000>;
 413                                 regulator-name = "PWR_1V8_MOCI (BUCK5)";
 414                         };
 415
 416                         reg_nvcc_dram: BUCK6 {
 417                                 regulator-always-on;
 418                                 regulator-boot-on;
 419                                 regulator-max-microvolt = <1100000>;
 420                                 regulator-min-microvolt = <1100000>;
 421                                 regulator-name = "On-module +VDD_DDR (BUCK6)";
 422                         };
 423
 424                         reg_nvcc_snvs: LDO1 {
 425                                 regulator-always-on;
 426                                 regulator-boot-on;
 427                                 regulator-max-microvolt = <1800000>;
 428                                 regulator-min-microvolt = <1800000>;
 429                                 regulator-name = "On-module +V1.8_SNVS (LDO1)";
 430                         };
 431
 432                         reg_vdd_snvs: LDO2 {
 433                                 regulator-always-on;
 434                                 regulator-boot-on;
 435                                 regulator-max-microvolt = <800000>;
 436                                 regulator-min-microvolt = <800000>;
 437                                 regulator-name = "On-module +V0.8_SNVS (LDO2)";
 438                         };
 439
 440                         reg_vdda: LDO3 {
 441                                 regulator-always-on;
 442                                 regulator-boot-on;
 443                                 regulator-max-microvolt = <1800000>;
 444                                 regulator-min-microvolt = <1800000>;
 445                                 regulator-name = "On-module +V1.8A (LDO3)";
 446                         };
 447
 448                         reg_vdd_phy: LDO4 {
 449                                 regulator-always-on;
 450                                 regulator-boot-on;
 451                                 regulator-max-microvolt = <900000>;
 452                                 regulator-min-microvolt = <900000>;
 453                                 regulator-name = "On-module +V0.9_MIPI (LDO4)";
 454                         };
 455
 456                         reg_nvcc_sd: LDO5 {
 457                                 regulator-max-microvolt = <3300000>;
 458                                 regulator-min-microvolt = <1800000>;
 459                                 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
 460                         };
 461                 };
 462         };
 463
 464         rtc_i2c: rtc@32 {
 465                 compatible = "epson,rx8130";
 466                 reg = <0x32>;
 467         };
 468
 469         adc@49 {
 470                 compatible = "ti,ads1015";
 471                 reg = <0x49>;
 472                 #address-cells = <1>;
 473                 #size-cells = <0>;
 474
 475                 /* Verdin I2C_1 (ADC_4 - ADC_3) */
 476                 channel@0 {
 477                         reg = <0>;
 478                         ti,datarate = <4>;
 479                         ti,gain = <2>;
 480                 };
 481
 482                 /* Verdin I2C_1 (ADC_4 - ADC_1) */
 483                 channel@1 {
 484                         reg = <1>;
 485                         ti,datarate = <4>;
 486                         ti,gain = <2>;
 487                 };
 488
 489                 /* Verdin I2C_1 (ADC_3 - ADC_1) */
 490                 channel@2 {
 491                         reg = <2>;
 492                         ti,datarate = <4>;
 493                         ti,gain = <2>;
 494                 };
 495
 496                 /* Verdin I2C_1 (ADC_2 - ADC_1) */
 497                 channel@3 {
 498                         reg = <3>;
 499                         ti,datarate = <4>;
 500                         ti,gain = <2>;
 501                 };
 502
 503                 /* Verdin I2C_1 ADC_4 */
 504                 channel@4 {
 505                         reg = <4>;
 506                         ti,datarate = <4>;
 507                         ti,gain = <2>;
 508                 };
 509
 510                 /* Verdin I2C_1 ADC_3 */
 511                 channel@5 {
 512                         reg = <5>;
 513                         ti,datarate = <4>;
 514                         ti,gain = <2>;
 515                 };
 516
 517                 /* Verdin I2C_1 ADC_2 */
 518                 channel@6 {
 519                         reg = <6>;
 520                         ti,datarate = <4>;
 521                         ti,gain = <2>;
 522                 };
 523
 524                 /* Verdin I2C_1 ADC_1 */
 525                 channel@7 {
 526                         reg = <7>;
 527                         ti,datarate = <4>;
 528                         ti,gain = <2>;
 529                 };
 530         };
 531
 532         eeprom@50 {
 533                 compatible = "st,24c02";
 534                 pagesize = <16>;
 535                 reg = <0x50>;
 536         };
 537 };
 538
 539 /* Verdin I2C_2_DSI */
 540 &i2c2 {
 541         clock-frequency = <10000>;
 542         pinctrl-names = "default", "gpio";
 543         pinctrl-0 = <&pinctrl_i2c2>;
 544         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 545         scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 546         sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 547         status = "disabled";
 548 };
 549
 550 /* Verdin I2C_3_HDMI N/A */
 551
 552 /* Verdin I2C_4_CSI */
 553 &i2c3 {
 554         clock-frequency = <400000>;
 555         pinctrl-names = "default", "gpio";
 556         pinctrl-0 = <&pinctrl_i2c3>;
 557         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 558         scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 559         sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 560 };
 561
 562 /* Verdin I2C_1 */
 563 &i2c4 {
 564         clock-frequency = <400000>;
 565         pinctrl-names = "default", "gpio";
 566         pinctrl-0 = <&pinctrl_i2c4>;
 567         pinctrl-1 = <&pinctrl_i2c4_gpio>;
 568         scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 569         sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 570
 571         gpio_expander_21: gpio-expander@21 {
 572                 compatible = "nxp,pcal6416";
 573                 #gpio-cells = <2>;
 574                 gpio-controller;
 575                 reg = <0x21>;
 576                 vcc-supply = <&reg_3p3v>;
 577                 status = "disabled";
 578         };
 579
 580         lvds_ti_sn65dsi84: bridge@2c {
 581                 compatible = "ti,sn65dsi84";
 582                 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
 583                 /* Verdin GPIO_10_DSI (SODIMM 21) */
 584                 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
 587                 reg = <0x2c>;
 588                 status = "disabled";
 589         };
 590
 591         /* Current measurement into module VCC */
 592         hwmon: hwmon@40 {
 593                 compatible = "ti,ina219";
 594                 reg = <0x40>;
 595                 shunt-resistor = <10000>;
 596                 status = "disabled";
 597         };
 598
 599         hdmi_lontium_lt8912: hdmi@48 {
 600                 compatible = "lontium,lt8912b";
 601                 pinctrl-names = "default";
 602                 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
 603                 reg = <0x48>;
 604                 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
 605                 /* Verdin GPIO_10_DSI (SODIMM 21) */
 606                 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
 607                 status = "disabled";
 608         };
 609
 610         atmel_mxt_ts: touch@4a {
 611                 compatible = "atmel,maxtouch";
 612                 /*
 613                  * Verdin GPIO_9_DSI
 614                  * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
 615                  */
 616                 interrupt-parent = <&gpio3>;
 617                 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
 618                 pinctrl-names = "default";
 619                 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
 620                 reg = <0x4a>;
 621                 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
 622                 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 623                 status = "disabled";
 624         };
 625
 626         /* Temperature sensor on carrier board */
 627         hwmon_temp: sensor@4f {
 628                 compatible = "ti,tmp75c";
 629                 reg = <0x4f>;
 630                 status = "disabled";
 631         };
 632
 633         /* EEPROM on display adapter (MIPI DSI Display Adapter) */
 634         eeprom_display_adapter: eeprom@50 {
 635                 compatible = "st,24c02";
 636                 pagesize = <16>;
 637                 reg = <0x50>;
 638                 status = "disabled";
 639         };
 640
 641         /* EEPROM on carrier board */
 642         eeprom_carrier_board: eeprom@57 {
 643                 compatible = "st,24c02";
 644                 pagesize = <16>;
 645                 reg = <0x57>;
 646                 status = "disabled";
 647         };
 648 };
 649
 650 /* Verdin PCIE_1 */
 651 &pcie0 {
 652         assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 653                           <&clk IMX8MM_CLK_PCIE1_CTRL>;
 654         assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 655                                  <&clk IMX8MM_SYS_PLL2_250M>;
 656         assigned-clock-rates = <10000000>, <250000000>;
 657         clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
 658                  <&clk IMX8MM_CLK_PCIE1_PHY>;
 659         clock-names = "pcie", "pcie_aux", "pcie_bus";
 660         pinctrl-names = "default";
 661         pinctrl-0 = <&pinctrl_pcie0>;
 662         /* PCIE_1_RESET# (SODIMM 244) */
 663         reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
 664 };
 665
 666 &pcie_phy {
 667         clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
 668         fsl,clkreq-unsupported;
 669         fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
 670         fsl,tx-deemph-gen1 = <0x2d>;
 671         fsl,tx-deemph-gen2 = <0xf>;
 672 };
 673
 674 /* Verdin PWM_3_DSI */
 675 &pwm1 {
 676         pinctrl-names = "default";
 677         pinctrl-0 = <&pinctrl_pwm_1>;
 678         #pwm-cells = <3>;
 679 };
 680
 681 /* Verdin PWM_1 */
 682 &pwm2 {
 683         pinctrl-names = "default";
 684         pinctrl-0 = <&pinctrl_pwm_2>;
 685         #pwm-cells = <3>;
 686 };
 687
 688 /* Verdin PWM_2 */
 689 &pwm3 {
 690         pinctrl-names = "default";
 691         pinctrl-0 = <&pinctrl_pwm_3>;
 692         #pwm-cells = <3>;
 693 };
 694
 695 /* Verdin I2S_1 */
 696 &sai2 {
 697         #sound-dai-cells = <0>;
 698         assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
 699         assigned-clock-rates = <24576000>;
 700         assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
 701         pinctrl-names = "default";
 702         pinctrl-0 = <&pinctrl_sai2>;
 703 };
 704
 705 &snvs_pwrkey {
 706         status = "okay";
 707 };
 708
 709 /* Verdin UART_3, used as the Linux console */
 710 &uart1 {
 711         pinctrl-names = "default";
 712         pinctrl-0 = <&pinctrl_uart1>;
 713 };
 714
 715 /* Verdin UART_1 */
 716 &uart2 {
 717         pinctrl-names = "default";
 718         pinctrl-0 = <&pinctrl_uart2>;
 719         uart-has-rtscts;
 720 };
 721
 722 /* Verdin UART_2 */
 723 &uart3 {
 724         pinctrl-names = "default";
 725         pinctrl-0 = <&pinctrl_uart3>;
 726         uart-has-rtscts;
 727 };
 728
 729 /*
 730  * Verdin UART_4
 731  * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
 732  */
 733 &uart4 {
 734         pinctrl-names = "default";
 735         pinctrl-0 = <&pinctrl_uart4>;
 736 };
 737
 738 /* Verdin USB_1 */
 739 &usbotg1 {
 740         adp-disable;
 741         dr_mode = "otg";
 742         hnp-disable;
 743         over-current-active-low;
 744         samsung,picophy-dc-vol-level-adjust = <7>;
 745         samsung,picophy-pre-emp-curr-control = <3>;
 746         srp-disable;
 747         vbus-supply = <&reg_usb_otg1_vbus>;
 748 };
 749
 750 /* Verdin USB_2 */
 751 &usbotg2 {
 752         dr_mode = "host";
 753         over-current-active-low;
 754         samsung,picophy-dc-vol-level-adjust = <7>;
 755         samsung,picophy-pre-emp-curr-control = <3>;
 756         vbus-supply = <&reg_usb_otg2_vbus>;
 757 };
 758
 759 &usbphynop1 {
 760         vcc-supply = <&reg_vdd_3v3>;
 761 };
 762
 763 &usbphynop2 {
 764         power-domains = <&pgc_otg2>;
 765         vcc-supply = <&reg_vdd_3v3>;
 766 };
 767
 768 /* On-module eMMC */
 769 &usdhc1 {
 770         bus-width = <8>;
 771         keep-power-in-suspend;
 772         non-removable;
 773         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 774         pinctrl-0 = <&pinctrl_usdhc1>;
 775         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 776         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 777         status = "okay";
 778 };
 779
 780 /* Verdin SD_1 */
 781 &usdhc2 {
 782         bus-width = <4>;
 783         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 784         disable-wp;
 785         pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
 786         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
 787         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
 788         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
 789         pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
 790         vmmc-supply = <&reg_usdhc2_vmmc>;
 791 };
 792
 793 &wdog1 {
 794         fsl,ext-reset-output;
 795         pinctrl-names = "default";
 796         pinctrl-0 = <&pinctrl_wdog>;
 797         status = "okay";
 798 };
 799
 800 &iomuxc {
 801         pinctrl-names = "default";
 802         pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
 803                     <&pinctrl_gpio3>, <&pinctrl_gpio4>,
 804                     <&pinctrl_gpio7>, <&pinctrl_gpio8>,
 805                     <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
 806                     <&pinctrl_pmic_tpm_ena>;
 807
 808         pinctrl_can1_int: can1intgrp {
 809                 fsl,pins =
 810                         <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6              0x146>; /* CAN_1_SPI_INT#_1.8V */
 811         };
 812
 813         pinctrl_can2_int: can2intgrp {
 814                 fsl,pins =
 815                         <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7              0x106>; /* CAN_2_SPI_INT#_1.8V, unused */
 816         };
 817
 818         pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
 819                 fsl,pins =
 820                         <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1                0x106>; /* SODIMM 256 */
 821         };
 822
 823         pinctrl_ecspi2: ecspi2grp {
 824                 fsl,pins =
 825                         <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO           0x6>,   /* SODIMM 198 */
 826                         <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI           0x6>,   /* SODIMM 200 */
 827                         <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK           0x6>,   /* SODIMM 196 */
 828                         <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13             0x6>;   /* SODIMM 202 */
 829         };
 830
 831         pinctrl_ecspi3: ecspi3grp {
 832                 fsl,pins =
 833                         <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5              0x146>, /* CAN_2_SPI_CS#_1.8V */
 834                         <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK             0x6>,   /* CAN_SPI_SCK_1.8V */
 835                         <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI             0x6>,   /* CAN_SPI_MOSI_1.8V */
 836                         <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO             0x6>,   /* CAN_SPI_MISO_1.8V */
 837                         <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25              0x6>;   /* CAN_1_SPI_CS_1.8V# */
 838         };
 839
 840         pinctrl_fec1: fec1grp {
 841                 fsl,pins =
 842                         <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                0x3>,
 843                         <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO              0x3>,
 844                         <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0          0x91>,
 845                         <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1          0x91>,
 846                         <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2          0x91>,
 847                         <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3          0x91>,
 848                         <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC          0x91>,
 849                         <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL    0x91>,
 850                         <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0          0x1f>,
 851                         <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1          0x1f>,
 852                         <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2          0x1f>,
 853                         <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3          0x1f>,
 854                         <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC          0x1f>,
 855                         <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL    0x1f>,
 856                         <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10             0x146>;
 857         };
 858
 859         pinctrl_fec1_sleep: fec1-sleepgrp {
 860                 fsl,pins =
 861                         <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                0x3>,
 862                         <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO              0x3>,
 863                         <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0          0x91>,
 864                         <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1          0x91>,
 865                         <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2          0x91>,
 866                         <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3          0x91>,
 867                         <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC          0x91>,
 868                         <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL    0x91>,
 869                         <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21               0x1f>,
 870                         <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20               0x1f>,
 871                         <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19               0x1f>,
 872                         <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18               0x1f>,
 873                         <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23               0x1f>,
 874                         <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22            0x1f>,
 875                         <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10             0x106>;
 876         };
 877
 878         pinctrl_flexspi0: flexspi0grp {
 879                 fsl,pins =
 880                         <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK              0x106>, /* SODIMM 52 */
 881                         <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B           0x106>, /* SODIMM 54 */
 882                         <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B           0x106>, /* SODIMM 64 */
 883                         <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0          0x106>, /* SODIMM 56 */
 884                         <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1          0x106>, /* SODIMM 58 */
 885                         <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2          0x106>, /* SODIMM 60 */
 886                         <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3          0x106>, /* SODIMM 62 */
 887                         <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS               0x106>; /* SODIMM 66 */
 888         };
 889
 890         pinctrl_gpio1: gpio1grp {
 891                 fsl,pins =
 892                         <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4              0x106>; /* SODIMM 206 */
 893         };
 894
 895         pinctrl_gpio2: gpio2grp {
 896                 fsl,pins =
 897                         <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5           0x106>; /* SODIMM 208 */
 898         };
 899
 900         pinctrl_gpio3: gpio3grp {
 901                 fsl,pins =
 902                         <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26              0x106>; /* SODIMM 210 */
 903         };
 904
 905         pinctrl_gpio4: gpio4grp {
 906                 fsl,pins =
 907                         <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27              0x106>; /* SODIMM 212 */
 908         };
 909
 910         pinctrl_gpio5: gpio5grp {
 911                 fsl,pins =
 912                         <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0              0x106>; /* SODIMM 216 */
 913         };
 914
 915         pinctrl_gpio6: gpio6grp {
 916                 fsl,pins =
 917                         <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11             0x106>; /* SODIMM 218 */
 918         };
 919
 920         pinctrl_gpio7: gpio7grp {
 921                 fsl,pins =
 922                         <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8              0x106>; /* SODIMM 220 */
 923         };
 924
 925         pinctrl_gpio8: gpio8grp {
 926                 fsl,pins =
 927                         <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9              0x106>; /* SODIMM 222 */
 928         };
 929
 930         /* Verdin GPIO_9_DSI (pulled-up as active-low) */
 931         pinctrl_gpio_9_dsi: gpio9dsigrp {
 932                 fsl,pins =
 933                         <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15              0x146>; /* SODIMM 17 */
 934         };
 935
 936         /* Verdin GPIO_10_DSI (pulled-up as active-low) */
 937         pinctrl_gpio_10_dsi: gpio10dsigrp {
 938                 fsl,pins =
 939                         <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3              0x146>; /* SODIMM 21 */
 940         };
 941
 942         pinctrl_gpio_hog1: gpiohog1grp {
 943                 fsl,pins =
 944                         <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20              0x106>, /* SODIMM 88 */
 945                         <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1                0x106>, /* SODIMM 90 */
 946                         <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2               0x106>, /* SODIMM 92 */
 947                         <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3               0x106>, /* SODIMM 94 */
 948                         <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4               0x106>, /* SODIMM 96 */
 949                         <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5               0x106>, /* SODIMM 100 */
 950                         <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0               0x106>, /* SODIMM 102 */
 951                         <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11               0x106>, /* SODIMM 104 */
 952                         <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12              0x106>, /* SODIMM 106 */
 953                         <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13              0x106>, /* SODIMM 108 */
 954                         <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14              0x106>, /* SODIMM 112 */
 955                         <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15              0x106>, /* SODIMM 114 */
 956                         <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16              0x106>, /* SODIMM 116 */
 957                         <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18              0x106>, /* SODIMM 118 */
 958                         <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10              0x106>; /* SODIMM 120 */
 959         };
 960
 961         pinctrl_gpio_hog2: gpiohog2grp {
 962                 fsl,pins =
 963                         <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2               0x106>; /* SODIMM 91 */
 964         };
 965
 966         pinctrl_gpio_hog3: gpiohog3grp {
 967                 fsl,pins =
 968                         <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13             0x146>, /* SODIMM 157 */
 969                         <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15             0x146>; /* SODIMM 187 */
 970         };
 971
 972         pinctrl_gpio_keys: gpiokeysgrp {
 973                 fsl,pins =
 974                         <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28              0x146>; /* SODIMM 252 */
 975         };
 976
 977         /* On-module I2C */
 978         pinctrl_i2c1: i2c1grp {
 979                 fsl,pins =
 980                         <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL                 0x40000146>,    /* PMIC_I2C_SCL */
 981                         <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA                 0x40000146>;    /* PMIC_I2C_SDA */
 982         };
 983
 984         pinctrl_i2c1_gpio: i2c1gpiogrp {
 985                 fsl,pins =
 986                         <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14               0x146>, /* PMIC_I2C_SCL */
 987                         <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15               0x146>; /* PMIC_I2C_SDA */
 988         };
 989
 990         /* Verdin I2C_4_CSI */
 991         pinctrl_i2c2: i2c2grp {
 992                 fsl,pins =
 993                         <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL                 0x40000146>,    /* SODIMM 55 */
 994                         <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA                 0x40000146>;    /* SODIMM 53 */
 995         };
 996
 997         pinctrl_i2c2_gpio: i2c2gpiogrp {
 998                 fsl,pins =
 999                         <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16               0x146>, /* SODIMM 55 */
1000                         <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17               0x146>; /* SODIMM 53 */
1001         };
1002
1003         /* Verdin I2C_2_DSI */
1004         pinctrl_i2c3: i2c3grp {
1005                 fsl,pins =
1006                         <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL                 0x40000146>,    /* SODIMM 95 */
1007                         <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA                 0x40000146>;    /* SODIMM 93 */
1008         };
1009
1010         pinctrl_i2c3_gpio: i2c3gpiogrp {
1011                 fsl,pins =
1012                         <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18               0x146>, /* SODIMM 95 */
1013                         <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19               0x146>; /* SODIMM 93 */
1014         };
1015
1016         /* Verdin I2C_1 */
1017         pinctrl_i2c4: i2c4grp {
1018                 fsl,pins =
1019                         <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL                 0x40000146>,    /* SODIMM 14 */
1020                         <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA                 0x40000146>;    /* SODIMM 12 */
1021         };
1022
1023         pinctrl_i2c4_gpio: i2c4gpiogrp {
1024                 fsl,pins =
1025                         <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20               0x146>, /* SODIMM 14 */
1026                         <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21               0x146>; /* SODIMM 12 */
1027         };
1028
1029         /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1030         pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1031                 fsl,pins =
1032                         <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23              0x6>;   /* SODIMM 42 */
1033         };
1034
1035         /* Verdin I2S_2_D_OUT shared with SAI5 */
1036         pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1037                 fsl,pins =
1038                         <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24              0x6>;   /* SODIMM 46 */
1039         };
1040
1041         pinctrl_pcie0: pcie0grp {
1042                 fsl,pins =
1043                         <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19              0x6>,   /* SODIMM 244 */
1044                         /* PMIC_EN_PCIe_CLK, unused */
1045                         <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19            0x6>;
1046         };
1047
1048         pinctrl_pmic: pmicirqgrp {
1049                 fsl,pins =
1050                         <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3              0x141>; /* PMIC_INT# */
1051         };
1052
1053         /* Verdin PWM_3_DSI shared with GPIO1_IO1 */
1054         pinctrl_pwm_1: pwm1grp {
1055                 fsl,pins =
1056                         <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT               0x6>;   /* SODIMM 19 */
1057         };
1058
1059         pinctrl_pwm_2: pwm2grp {
1060                 fsl,pins =
1061                         <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT                 0x6>;   /* SODIMM 15 */
1062         };
1063
1064         pinctrl_pwm_3: pwm3grp {
1065                 fsl,pins =
1066                         <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT                 0x6>;   /* SODIMM 16 */
1067         };
1068
1069         /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
1070         pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
1071                 fsl,pins =
1072                         <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1              0x106>; /* SODIMM 19 */
1073         };
1074
1075         pinctrl_reg_eth: regethgrp {
1076                 fsl,pins =
1077                         <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20                 0x146>; /* PMIC_EN_ETH */
1078         };
1079
1080         pinctrl_reg_usb1_en: regusb1engrp {
1081                 fsl,pins =
1082                         <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12             0x106>; /* SODIMM 155 */
1083         };
1084
1085         pinctrl_reg_usb2_en: regusb2engrp {
1086                 fsl,pins =
1087                         <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14             0x106>; /* SODIMM 185 */
1088         };
1089
1090         pinctrl_sai2: sai2grp {
1091                 fsl,pins =
1092                         <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK               0x6>,   /* SODIMM 38 */
1093                         <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK             0x6>,   /* SODIMM 30 */
1094                         <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC            0x6>,   /* SODIMM 32 */
1095                         <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0           0x6>,   /* SODIMM 36 */
1096                         <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0           0x6>;   /* SODIMM 34 */
1097         };
1098
1099         pinctrl_sai5: sai5grp {
1100                 fsl,pins =
1101                         <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0           0x6>,   /* SODIMM 48 */
1102                         <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC            0x6>,   /* SODIMM 44 */
1103                         <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK            0x6>,   /* SODIMM 42 */
1104                         <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0           0x6>;   /* SODIMM 46 */
1105         };
1106
1107         /* control signal for optional ATTPM20P or SE050 */
1108         pinctrl_pmic_tpm_ena: pmictpmenagrp {
1109                 fsl,pins =
1110                         <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19              0x106>; /* PMIC_TPM_ENA */
1111         };
1112
1113         pinctrl_tsp: tspgrp {
1114                 fsl,pins =
1115                         <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6               0x6>,   /* SODIMM 148 */
1116                         <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7               0x6>,   /* SODIMM 152 */
1117                         <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8               0x6>,   /* SODIMM 154 */
1118                         <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9               0x146>, /* SODIMM 174 */
1119                         <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17              0x6>;   /* SODIMM 150 */
1120         };
1121
1122         pinctrl_uart1: uart1grp {
1123                 fsl,pins =
1124                         <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX             0x146>, /* SODIMM 147 */
1125                         <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX            0x146>; /* SODIMM 149 */
1126         };
1127
1128         pinctrl_uart2: uart2grp {
1129                 fsl,pins =
1130                         <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B          0x146>, /* SODIMM 133 */
1131                         <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B          0x146>, /* SODIMM 135 */
1132                         <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX             0x146>, /* SODIMM 131 */
1133                         <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX            0x146>; /* SODIMM 129 */
1134         };
1135
1136         pinctrl_uart3: uart3grp {
1137                 fsl,pins =
1138                         <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B       0x146>, /* SODIMM 141 */
1139                         <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX          0x146>, /* SODIMM 139 */
1140                         <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX          0x146>, /* SODIMM 137 */
1141                         <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B        0x146>; /* SODIMM 143 */
1142         };
1143
1144         pinctrl_uart4: uart4grp {
1145                 fsl,pins =
1146                         <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX            0x146>, /* SODIMM 151 */
1147                         <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX            0x146>; /* SODIMM 153 */
1148         };
1149
1150         pinctrl_usdhc1: usdhc1grp {
1151                 fsl,pins =
1152                         <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK                0x190>,
1153                         <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD                0x1d0>,
1154                         <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0            0x1d0>,
1155                         <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1            0x1d0>,
1156                         <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2            0x1d0>,
1157                         <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3            0x1d0>,
1158                         <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4            0x1d0>,
1159                         <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5            0x1d0>,
1160                         <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6            0x1d0>,
1161                         <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7            0x1d0>,
1162                         <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B        0x1d1>,
1163                         <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE          0x190>;
1164         };
1165
1166         pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1167                 fsl,pins =
1168                         <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK                0x194>,
1169                         <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD                0x1d4>,
1170                         <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0            0x1d4>,
1171                         <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1            0x1d4>,
1172                         <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2            0x1d4>,
1173                         <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3            0x1d4>,
1174                         <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4            0x1d4>,
1175                         <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5            0x1d4>,
1176                         <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6            0x1d4>,
1177                         <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7            0x1d4>,
1178                         <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B        0x1d1>,
1179                         <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE          0x194>;
1180         };
1181
1182         pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1183                 fsl,pins =
1184                         <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK                0x196>,
1185                         <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD                0x1d6>,
1186                         <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0            0x1d6>,
1187                         <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1            0x1d6>,
1188                         <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2            0x1d6>,
1189                         <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3            0x1d6>,
1190                         <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4            0x1d6>,
1191                         <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5            0x1d6>,
1192                         <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6            0x1d6>,
1193                         <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7            0x1d6>,
1194                         <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B        0x1d1>,
1195                         <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE          0x196>;
1196         };
1197
1198         pinctrl_usdhc2_cd: usdhc2cdgrp {
1199                 fsl,pins =
1200                         <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12               0x6>;   /* SODIMM 84 */
1201         };
1202
1203         pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1204                 fsl,pins =
1205                         <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12               0x0>;   /* SODIMM 84 */
1206         };
1207
1208         pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1209                 fsl,pins =
1210                         <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5                0x6>;   /* SODIMM 76 */
1211         };
1212
1213         /*
1214          * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
1215          * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
1216          */
1217         pinctrl_usdhc2: usdhc2grp {
1218                 fsl,pins =
1219                         <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT         0x10>,
1220                         <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                0x90>,  /* SODIMM 78 */
1221                         <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                0x90>,  /* SODIMM 74 */
1222                         <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0            0x90>,  /* SODIMM 80 */
1223                         <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1            0x90>,  /* SODIMM 82 */
1224                         <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2            0x90>,  /* SODIMM 70 */
1225                         <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3            0x90>;  /* SODIMM 72 */
1226         };
1227
1228         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1229                 fsl,pins =
1230                         <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT         0x10>,
1231                         <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                0x94>,
1232                         <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                0x94>,
1233                         <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0            0x94>,
1234                         <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1            0x94>,
1235                         <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2            0x94>,
1236                         <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3            0x94>;
1237         };
1238
1239         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1240                 fsl,pins =
1241                         <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT         0x10>,
1242                         <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                0x96>,
1243                         <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                0x96>,
1244                         <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0            0x96>,
1245                         <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1            0x96>,
1246                         <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2            0x96>,
1247                         <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3            0x96>;
1248         };
1249
1250         /* Avoid backfeeding with removed card power */
1251         pinctrl_usdhc2_sleep: usdhc2slpgrp {
1252                 fsl,pins =
1253                         <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT         0x0>,
1254                         <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                0x0>,
1255                         <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                0x0>,
1256                         <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0            0x0>,
1257                         <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1            0x0>,
1258                         <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2            0x0>,
1259                         <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3            0x0>;
1260         };
1261
1262         /*
1263          * On-module Wi-Fi/BT or type specific SDHC interface
1264          * (e.g. on X52 extension slot of Verdin Development Board)
1265          */
1266         pinctrl_usdhc3: usdhc3grp {
1267                 fsl,pins =
1268                         <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0          0x150>,
1269                         <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1          0x150>,
1270                         <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2          0x150>,
1271                         <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3          0x150>,
1272                         <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK              0x150>,
1273                         <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD              0x150>;
1274         };
1275
1276         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1277                 fsl,pins =
1278                         <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0          0x154>,
1279                         <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1          0x154>,
1280                         <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2          0x154>,
1281                         <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3          0x154>,
1282                         <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK              0x154>,
1283                         <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD              0x154>;
1284         };
1285
1286         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1287                 fsl,pins =
1288                         <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0          0x156>,
1289                         <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1          0x156>,
1290                         <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2          0x156>,
1291                         <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3          0x156>,
1292                         <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK              0x156>,
1293                         <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD              0x156>;
1294         };
1295
1296         pinctrl_wdog: wdoggrp {
1297                 fsl,pins =
1298                         <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B           0x166>; /* PMIC_WDI */
1299         };
1300
1301         pinctrl_wifi_ctrl: wifictrlgrp {
1302                 fsl,pins =
1303                         <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16           0x46>,  /* WIFI_WKUP_BT */
1304                         <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9               0x146>, /* WIFI_W_WKUP_HOST */
1305                         <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20               0x46>;  /* WIFI_WKUP_WLAN */
1306         };
1307
1308         pinctrl_wifi_i2s: bti2sgrp {
1309                 fsl,pins =
1310                         <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK            0x6>,   /* WIFI_TX_BCLK */
1311                         <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0           0x6>,   /* WIFI_TX_DATA0 */
1312                         <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC            0x6>,   /* WIFI_TX_SYNC */
1313                         <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0           0x6>;   /* WIFI_RX_DATA0 */
1314         };
1315
1316         pinctrl_wifi_pwr_en: wifipwrengrp {
1317                 fsl,pins =
1318                         <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25              0x6>;   /* PMIC_EN_WIFI */
1319         };
1320 };