1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2022 Toradex
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
7 #include <dt-bindings/pwm/pwm.h>
20 backlight: backlight {
21 compatible = "pwm-backlight";
22 brightness-levels = <0 45 63 88 119 158 203 255>;
23 default-brightness-level = <4>;
24 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
25 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
28 power-supply = <®_3p3v>;
29 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
30 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
34 /* Fixed clock dedicated to SPI CAN controller */
36 compatible = "fixed-clock";
38 clock-frequency = <40000000>;
42 compatible = "gpio-keys";
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_gpio_keys>;
47 debounce-interval = <10>;
48 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
49 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
51 linux,code = <KEY_WAKEUP>;
56 hdmi_connector: hdmi-connector {
57 compatible = "hdmi-connector";
58 ddc-i2c-bus = <&i2c2>;
59 /* Verdin PWM_3_DSI (SODIMM 19) */
60 hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>;
68 panel_lvds: panel-lvds {
69 compatible = "panel-lvds";
70 backlight = <&backlight>;
71 data-mapping = "vesa-24";
75 /* Carrier Board Supplies */
76 reg_1p8v: regulator-1p8v {
77 compatible = "regulator-fixed";
78 regulator-max-microvolt = <1800000>;
79 regulator-min-microvolt = <1800000>;
80 regulator-name = "+V1.8_SW";
83 reg_3p3v: regulator-3p3v {
84 compatible = "regulator-fixed";
85 regulator-max-microvolt = <3300000>;
86 regulator-min-microvolt = <3300000>;
87 regulator-name = "+V3.3_SW";
90 reg_5p0v: regulator-5p0v {
91 compatible = "regulator-fixed";
92 regulator-max-microvolt = <5000000>;
93 regulator-min-microvolt = <5000000>;
94 regulator-name = "+V5_SW";
97 /* Non PMIC On-module Supplies */
98 reg_ethphy: regulator-ethphy {
99 compatible = "regulator-fixed";
101 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
102 off-on-delay-us = <500000>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_reg_eth>;
107 regulator-max-microvolt = <3300000>;
108 regulator-min-microvolt = <3300000>;
109 regulator-name = "On-module +V3.3_ETH";
110 startup-delay-us = <200000>;
113 reg_usb_otg1_vbus: regulator-usb-otg1 {
114 compatible = "regulator-fixed";
116 /* Verdin USB_1_EN (SODIMM 155) */
117 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_reg_usb1_en>;
120 regulator-max-microvolt = <5000000>;
121 regulator-min-microvolt = <5000000>;
122 regulator-name = "USB_1_EN";
125 reg_usb_otg2_vbus: regulator-usb-otg2 {
126 compatible = "regulator-fixed";
128 /* Verdin USB_2_EN (SODIMM 185) */
129 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_reg_usb2_en>;
132 regulator-max-microvolt = <5000000>;
133 regulator-min-microvolt = <5000000>;
134 regulator-name = "USB_2_EN";
137 reg_usdhc2_vmmc: regulator-usdhc2 {
138 compatible = "regulator-fixed";
140 /* Verdin SD_1_PWR_EN (SODIMM 76) */
141 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
142 off-on-delay-us = <100000>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
145 regulator-max-microvolt = <3300000>;
146 regulator-min-microvolt = <3300000>;
147 regulator-name = "+V3.3_SD";
148 startup-delay-us = <2000>;
152 #address-cells = <2>;
156 /* Use the kernel configuration settings instead */
157 /delete-node/ linux,cma;
162 cpu-supply = <®_vdd_arm>;
166 cpu-supply = <®_vdd_arm>;
170 cpu-supply = <®_vdd_arm>;
174 cpu-supply = <®_vdd_arm>;
178 temperature = <95000>;
182 temperature = <105000>;
186 operating-points-v2 = <&ddrc_opp_table>;
188 ddrc_opp_table: opp-table {
189 compatible = "operating-points-v2";
192 opp-hz = /bits/ 64 <25000000>;
196 opp-hz = /bits/ 64 <100000000>;
200 opp-hz = /bits/ 64 <750000000>;
207 #address-cells = <1>;
209 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_ecspi2>;
214 /* Verdin CAN_1 (On-module) */
216 #address-cells = <1>;
218 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_ecspi3>;
224 compatible = "microchip,mcp251xfd";
226 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_can1_int>;
230 spi-max-frequency = <8500000>;
234 /* Verdin ETH_1 (On-module PHY) */
237 phy-handle = <ðphy0>;
238 phy-mode = "rgmii-id";
239 phy-supply = <®_ethphy>;
240 pinctrl-names = "default", "sleep";
241 pinctrl-0 = <&pinctrl_fec1>;
242 pinctrl-1 = <&pinctrl_fec1_sleep>;
245 #address-cells = <1>;
248 ethphy0: ethernet-phy@7 {
249 compatible = "ethernet-phy-ieee802.3-c22";
250 interrupt-parent = <&gpio1>;
251 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
252 micrel,led-mode = <0>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_flexspi0>;
265 gpio-line-names = "SODIMM_216",
284 gpio-line-names = "",
306 gpio-line-names = "SODIMM_131",
337 ctrl-sleep-moci-hog {
339 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
340 gpios = <1 GPIO_ACTIVE_HIGH>;
341 line-name = "CTRL_SLEEP_MOCI#";
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
350 clock-frequency = <400000>;
351 pinctrl-names = "default", "gpio";
352 pinctrl-0 = <&pinctrl_i2c1>;
353 pinctrl-1 = <&pinctrl_i2c1_gpio>;
354 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
355 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
359 compatible = "nxp,pca9450a";
360 interrupt-parent = <&gpio1>;
361 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
362 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_pmic>;
368 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
374 nxp,dvs-run-voltage = <850000>;
375 nxp,dvs-standby-voltage = <800000>;
378 regulator-max-microvolt = <850000>;
379 regulator-min-microvolt = <800000>;
380 regulator-name = "On-module +VDD_SOC (BUCK1)";
381 regulator-ramp-delay = <3125>;
385 nxp,dvs-run-voltage = <950000>;
386 nxp,dvs-standby-voltage = <850000>;
389 regulator-max-microvolt = <1050000>;
390 regulator-min-microvolt = <805000>;
391 regulator-name = "On-module +VDD_ARM (BUCK2)";
392 regulator-ramp-delay = <3125>;
395 reg_vdd_dram: BUCK3 {
398 regulator-max-microvolt = <1000000>;
399 regulator-min-microvolt = <805000>;
400 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
406 regulator-max-microvolt = <3300000>;
407 regulator-min-microvolt = <3300000>;
408 regulator-name = "On-module +V3.3 (BUCK4)";
414 regulator-max-microvolt = <1800000>;
415 regulator-min-microvolt = <1800000>;
416 regulator-name = "PWR_1V8_MOCI (BUCK5)";
419 reg_nvcc_dram: BUCK6 {
422 regulator-max-microvolt = <1100000>;
423 regulator-min-microvolt = <1100000>;
424 regulator-name = "On-module +VDD_DDR (BUCK6)";
427 reg_nvcc_snvs: LDO1 {
430 regulator-max-microvolt = <1800000>;
431 regulator-min-microvolt = <1800000>;
432 regulator-name = "On-module +V1.8_SNVS (LDO1)";
438 regulator-max-microvolt = <800000>;
439 regulator-min-microvolt = <800000>;
440 regulator-name = "On-module +V0.8_SNVS (LDO2)";
446 regulator-max-microvolt = <1800000>;
447 regulator-min-microvolt = <1800000>;
448 regulator-name = "On-module +V1.8A (LDO3)";
454 regulator-max-microvolt = <900000>;
455 regulator-min-microvolt = <900000>;
456 regulator-name = "On-module +V0.9_MIPI (LDO4)";
460 regulator-max-microvolt = <3300000>;
461 regulator-min-microvolt = <1800000>;
462 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
468 compatible = "epson,rx8130";
473 compatible = "ti,ads1015";
475 #address-cells = <1>;
478 /* Verdin I2C_1 (ADC_4 - ADC_3) */
485 /* Verdin I2C_1 (ADC_4 - ADC_1) */
492 /* Verdin I2C_1 (ADC_3 - ADC_1) */
499 /* Verdin I2C_1 (ADC_2 - ADC_1) */
506 /* Verdin I2C_1 ADC_4 */
513 /* Verdin I2C_1 ADC_3 */
520 /* Verdin I2C_1 ADC_2 */
527 /* Verdin I2C_1 ADC_1 */
536 compatible = "st,24c02";
542 /* Verdin I2C_2_DSI */
544 clock-frequency = <10000>;
545 pinctrl-names = "default", "gpio";
546 pinctrl-0 = <&pinctrl_i2c2>;
547 pinctrl-1 = <&pinctrl_i2c2_gpio>;
548 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
549 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
553 /* Verdin I2C_3_HDMI N/A */
555 /* Verdin I2C_4_CSI */
557 clock-frequency = <400000>;
558 pinctrl-names = "default", "gpio";
559 pinctrl-0 = <&pinctrl_i2c3>;
560 pinctrl-1 = <&pinctrl_i2c3_gpio>;
561 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
562 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
567 clock-frequency = <400000>;
568 pinctrl-names = "default", "gpio";
569 pinctrl-0 = <&pinctrl_i2c4>;
570 pinctrl-1 = <&pinctrl_i2c4_gpio>;
571 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
572 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
574 gpio_expander_21: gpio-expander@21 {
575 compatible = "nxp,pcal6416";
579 vcc-supply = <®_3p3v>;
583 lvds_ti_sn65dsi84: bridge@2c {
584 compatible = "ti,sn65dsi84";
585 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
586 /* Verdin GPIO_10_DSI (SODIMM 21) */
587 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
588 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
594 /* Current measurement into module VCC */
596 compatible = "ti,ina219";
598 shunt-resistor = <10000>;
602 hdmi_lontium_lt8912: hdmi@48 {
603 compatible = "lontium,lt8912b";
604 pinctrl-names = "default";
605 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
607 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
608 /* Verdin GPIO_10_DSI (SODIMM 21) */
609 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
613 atmel_mxt_ts: touch@4a {
614 compatible = "atmel,maxtouch";
617 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
619 interrupt-parent = <&gpio3>;
620 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
624 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
625 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
629 /* Temperature sensor on carrier board */
630 hwmon_temp: sensor@4f {
631 compatible = "ti,tmp75c";
636 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
637 eeprom_display_adapter: eeprom@50 {
638 compatible = "st,24c02";
644 /* EEPROM on carrier board */
645 eeprom_carrier_board: eeprom@57 {
646 compatible = "st,24c02";
655 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
656 <&clk IMX8MM_CLK_PCIE1_CTRL>;
657 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
658 <&clk IMX8MM_SYS_PLL2_250M>;
659 assigned-clock-rates = <10000000>, <250000000>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&pinctrl_pcie0>;
662 /* PCIE_1_RESET# (SODIMM 244) */
663 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
667 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
669 fsl,clkreq-unsupported;
670 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
671 fsl,tx-deemph-gen1 = <0x2d>;
672 fsl,tx-deemph-gen2 = <0xf>;
675 /* Verdin PWM_3_DSI */
677 pinctrl-names = "default";
678 pinctrl-0 = <&pinctrl_pwm_1>;
684 pinctrl-names = "default";
685 pinctrl-0 = <&pinctrl_pwm_2>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&pinctrl_pwm_3>;
698 #sound-dai-cells = <0>;
699 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
700 assigned-clock-rates = <24576000>;
701 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
702 pinctrl-names = "default";
703 pinctrl-0 = <&pinctrl_sai2>;
710 /* Verdin UART_3, used as the Linux console */
712 pinctrl-names = "default";
713 pinctrl-0 = <&pinctrl_uart1>;
718 pinctrl-names = "default";
719 pinctrl-0 = <&pinctrl_uart2>;
725 pinctrl-names = "default";
726 pinctrl-0 = <&pinctrl_uart3>;
732 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
735 pinctrl-names = "default";
736 pinctrl-0 = <&pinctrl_uart4>;
744 samsung,picophy-dc-vol-level-adjust = <7>;
745 samsung,picophy-pre-emp-curr-control = <3>;
747 vbus-supply = <®_usb_otg1_vbus>;
753 samsung,picophy-dc-vol-level-adjust = <7>;
754 samsung,picophy-pre-emp-curr-control = <3>;
755 vbus-supply = <®_usb_otg2_vbus>;
759 vcc-supply = <®_vdd_3v3>;
763 power-domains = <&pgc_otg2>;
764 vcc-supply = <®_vdd_3v3>;
770 keep-power-in-suspend;
772 pinctrl-names = "default", "state_100mhz", "state_200mhz";
773 pinctrl-0 = <&pinctrl_usdhc1>;
774 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
775 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
782 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
784 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
785 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
786 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
787 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
788 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
789 vmmc-supply = <®_usdhc2_vmmc>;
793 fsl,ext-reset-output;
794 pinctrl-names = "default";
795 pinctrl-0 = <&pinctrl_wdog>;
800 pinctrl-names = "default";
801 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
802 <&pinctrl_gpio3>, <&pinctrl_gpio4>,
803 <&pinctrl_gpio7>, <&pinctrl_gpio8>,
804 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
805 <&pinctrl_pmic_tpm_ena>;
807 pinctrl_can1_int: can1intgrp {
809 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */
812 pinctrl_can2_int: can2intgrp {
814 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */
817 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
819 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */
822 pinctrl_ecspi2: ecspi2grp {
824 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */
825 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
826 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
827 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */
830 pinctrl_ecspi3: ecspi3grp {
832 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */
833 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */
834 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */
835 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */
836 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */
839 pinctrl_fec1: fec1grp {
841 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
842 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
843 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
844 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
845 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
846 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
847 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
848 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
849 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
850 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
851 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
852 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
853 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
854 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>,
855 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>;
858 pinctrl_fec1_sleep: fec1-sleepgrp {
860 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
861 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
862 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
863 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
864 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
865 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
866 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
867 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
868 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
869 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
870 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
871 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
872 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
873 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>,
874 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>;
877 pinctrl_flexspi0: flexspi0grp {
879 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */
880 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */
881 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */
882 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */
883 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */
884 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */
885 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */
886 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */
889 pinctrl_gpio1: gpio1grp {
891 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */
894 pinctrl_gpio2: gpio2grp {
896 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */
899 pinctrl_gpio3: gpio3grp {
901 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */
904 pinctrl_gpio4: gpio4grp {
906 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */
909 pinctrl_gpio5: gpio5grp {
911 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */
914 pinctrl_gpio6: gpio6grp {
916 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */
919 pinctrl_gpio7: gpio7grp {
921 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */
924 pinctrl_gpio8: gpio8grp {
926 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */
929 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
930 pinctrl_gpio_9_dsi: gpio9dsigrp {
932 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */
935 /* Verdin GPIO_10_DSI (pulled-up as active-low) */
936 pinctrl_gpio_10_dsi: gpio10dsigrp {
938 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */
941 pinctrl_gpio_hog1: gpiohog1grp {
943 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */
944 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */
945 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */
946 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */
947 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */
948 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */
949 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */
950 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */
951 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */
952 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */
953 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */
954 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */
955 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */
956 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */
957 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */
960 pinctrl_gpio_hog2: gpiohog2grp {
962 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */
965 pinctrl_gpio_hog3: gpiohog3grp {
967 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */
968 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */
971 pinctrl_gpio_keys: gpiokeysgrp {
973 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */
977 pinctrl_i2c1: i2c1grp {
979 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */
980 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */
983 pinctrl_i2c1_gpio: i2c1gpiogrp {
985 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */
986 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */
989 /* Verdin I2C_4_CSI */
990 pinctrl_i2c2: i2c2grp {
992 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */
993 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */
996 pinctrl_i2c2_gpio: i2c2gpiogrp {
998 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */
999 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */
1002 /* Verdin I2C_2_DSI */
1003 pinctrl_i2c3: i2c3grp {
1005 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */
1006 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */
1009 pinctrl_i2c3_gpio: i2c3gpiogrp {
1011 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */
1012 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */
1016 pinctrl_i2c4: i2c4grp {
1018 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */
1019 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */
1022 pinctrl_i2c4_gpio: i2c4gpiogrp {
1024 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */
1025 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */
1028 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1029 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1031 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */
1034 /* Verdin I2S_2_D_OUT shared with SAI5 */
1035 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1037 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */
1040 pinctrl_pcie0: pcie0grp {
1042 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */
1043 /* PMIC_EN_PCIe_CLK, unused */
1044 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>;
1047 pinctrl_pmic: pmicirqgrp {
1049 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */
1052 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */
1053 pinctrl_pwm_1: pwm1grp {
1055 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */
1058 pinctrl_pwm_2: pwm2grp {
1060 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */
1063 pinctrl_pwm_3: pwm3grp {
1065 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */
1068 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
1069 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
1071 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */
1074 pinctrl_reg_eth: regethgrp {
1076 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */
1079 pinctrl_reg_usb1_en: regusb1engrp {
1081 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */
1084 pinctrl_reg_usb2_en: regusb2engrp {
1086 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */
1089 pinctrl_sai2: sai2grp {
1091 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */
1092 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
1093 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
1094 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */
1095 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */
1098 pinctrl_sai5: sai5grp {
1100 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */
1101 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */
1102 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */
1103 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */
1106 /* control signal for optional ATTPM20P or SE050 */
1107 pinctrl_pmic_tpm_ena: pmictpmenagrp {
1109 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */
1112 pinctrl_tsp: tspgrp {
1114 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */
1115 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */
1116 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */
1117 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */
1118 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */
1121 pinctrl_uart1: uart1grp {
1123 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */
1124 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */
1127 pinctrl_uart2: uart2grp {
1129 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */
1130 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */
1131 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
1132 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */
1135 pinctrl_uart3: uart3grp {
1137 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
1138 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
1139 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
1140 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
1143 pinctrl_uart4: uart4grp {
1145 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */
1146 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */
1149 pinctrl_usdhc1: usdhc1grp {
1151 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>,
1152 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>,
1153 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>,
1154 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>,
1155 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>,
1156 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>,
1157 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>,
1158 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>,
1159 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>,
1160 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>,
1161 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1162 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>;
1165 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1167 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>,
1168 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>,
1169 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>,
1170 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>,
1171 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>,
1172 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>,
1173 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>,
1174 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>,
1175 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>,
1176 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>,
1177 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1178 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>;
1181 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1183 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>,
1184 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>,
1185 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>,
1186 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>,
1187 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>,
1188 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>,
1189 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>,
1190 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>,
1191 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>,
1192 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>,
1193 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1194 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>;
1197 pinctrl_usdhc2_cd: usdhc2cdgrp {
1199 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */
1202 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1204 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */
1207 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1209 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
1213 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
1214 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
1216 pinctrl_usdhc2: usdhc2grp {
1218 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1219 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
1220 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
1221 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
1222 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */
1223 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */
1224 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */
1227 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1229 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1230 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
1231 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
1232 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
1233 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>,
1234 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>,
1235 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>;
1238 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1240 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1241 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
1242 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
1243 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
1244 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>,
1245 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>,
1246 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>;
1249 /* Avoid backfeeding with removed card power */
1250 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1252 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>,
1253 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>,
1254 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>,
1255 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>,
1256 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>,
1257 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>,
1258 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>;
1262 * On-module Wi-Fi/BT or type specific SDHC interface
1263 * (e.g. on X52 extension slot of Verdin Development Board)
1265 pinctrl_usdhc3: usdhc3grp {
1267 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>,
1268 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>,
1269 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>,
1270 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>,
1271 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
1272 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>;
1275 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1277 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>,
1278 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>,
1279 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>,
1280 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>,
1281 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
1282 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>;
1285 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1287 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>,
1288 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>,
1289 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>,
1290 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>,
1291 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
1292 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>;
1295 pinctrl_wdog: wdoggrp {
1297 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */
1300 pinctrl_wifi_ctrl: wifictrlgrp {
1302 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */
1303 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */
1304 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */
1307 pinctrl_wifi_i2s: bti2sgrp {
1309 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */
1310 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */
1311 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */
1312 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */
1315 pinctrl_wifi_pwr_en: wifipwrengrp {
1317 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */