1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2022 Gateworks Corporation
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
13 #include "imx8mm.dtsi"
16 model = "Gateworks Venice GW7904 i.MX8MM board";
17 compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm";
24 device_type = "memory";
25 reg = <0x0 0x40000000 0 0x80000000>;
29 compatible = "gpio-keys";
33 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
40 interrupt-parent = <&gsc>;
47 interrupt-parent = <&gsc>;
54 interrupt-parent = <&gsc>;
59 label = "switch_hold";
61 interrupt-parent = <&gsc>;
67 compatible = "gpio-leds";
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_gpio_leds>;
72 function = LED_FUNCTION_STATUS;
73 color = <LED_COLOR_ID_GREEN>;
75 gpios = <&gpioled 0 GPIO_ACTIVE_LOW>;
76 default-state = "off";
80 function = LED_FUNCTION_STATUS;
81 color = <LED_COLOR_ID_YELLOW>;
83 gpios = <&gpioled 1 GPIO_ACTIVE_LOW>;
84 default-state = "off";
88 function = LED_FUNCTION_STATUS;
89 color = <LED_COLOR_ID_GREEN>;
91 gpios = <&gpioled 2 GPIO_ACTIVE_LOW>;
92 default-state = "off";
96 function = LED_FUNCTION_STATUS;
97 color = <LED_COLOR_ID_YELLOW>;
99 gpios = <&gpioled 3 GPIO_ACTIVE_LOW>;
100 default-state = "off";
104 function = LED_FUNCTION_STATUS;
105 color = <LED_COLOR_ID_GREEN>;
107 gpios = <&gpioled 4 GPIO_ACTIVE_LOW>;
108 default-state = "off";
112 function = LED_FUNCTION_STATUS;
113 color = <LED_COLOR_ID_YELLOW>;
115 gpios = <&gpioled 5 GPIO_ACTIVE_LOW>;
116 default-state = "off";
120 function = LED_FUNCTION_STATUS;
121 color = <LED_COLOR_ID_GREEN>;
123 gpios = <&gpioled 6 GPIO_ACTIVE_LOW>;
124 default-state = "off";
128 function = LED_FUNCTION_STATUS;
129 color = <LED_COLOR_ID_YELLOW>;
131 gpios = <&gpioled 7 GPIO_ACTIVE_LOW>;
132 default-state = "off";
136 function = LED_FUNCTION_STATUS;
137 color = <LED_COLOR_ID_GREEN>;
139 gpios = <&gpioled 8 GPIO_ACTIVE_LOW>;
140 default-state = "off";
144 function = LED_FUNCTION_STATUS;
145 color = <LED_COLOR_ID_YELLOW>;
147 gpios = <&gpioled 9 GPIO_ACTIVE_LOW>;
148 default-state = "off";
152 function = LED_FUNCTION_STATUS;
153 color = <LED_COLOR_ID_GREEN>;
155 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
156 default-state = "off";
160 function = LED_FUNCTION_STATUS;
161 color = <LED_COLOR_ID_RED>;
163 gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
164 default-state = "off";
168 function = LED_FUNCTION_STATUS;
169 color = <LED_COLOR_ID_GREEN>;
171 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
172 default-state = "off";
176 function = LED_FUNCTION_STATUS;
177 color = <LED_COLOR_ID_RED>;
179 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
180 default-state = "off";
184 function = LED_FUNCTION_STATUS;
185 color = <LED_COLOR_ID_GREEN>;
187 gpios = <&gpioled 10 GPIO_ACTIVE_LOW>;
188 default-state = "off";
192 function = LED_FUNCTION_STATUS;
193 color = <LED_COLOR_ID_YELLOW>;
195 gpios = <&gpioled 11 GPIO_ACTIVE_LOW>;
196 default-state = "off";
200 function = LED_FUNCTION_STATUS;
201 color = <LED_COLOR_ID_GREEN>;
203 gpios = <&gpioled 12 GPIO_ACTIVE_LOW>;
204 default-state = "off";
208 function = LED_FUNCTION_STATUS;
209 color = <LED_COLOR_ID_YELLOW>;
211 gpios = <&gpioled 13 GPIO_ACTIVE_LOW>;
212 default-state = "off";
216 function = LED_FUNCTION_STATUS;
217 color = <LED_COLOR_ID_GREEN>;
219 gpios = <&gpioled 14 GPIO_ACTIVE_LOW>;
220 default-state = "off";
224 function = LED_FUNCTION_STATUS;
225 color = <LED_COLOR_ID_YELLOW>;
227 gpios = <&gpioled 15 GPIO_ACTIVE_LOW>;
228 default-state = "off";
232 pcie0_refclk: pcie0-refclk {
233 compatible = "fixed-clock";
235 clock-frequency = <100000000>;
238 reg_3p3v: regulator-3p3v {
239 compatible = "regulator-fixed";
240 regulator-name = "3P3V";
241 regulator-min-microvolt = <3300000>;
242 regulator-max-microvolt = <3300000>;
248 cpu-supply = <&buck2>;
252 cpu-supply = <&buck2>;
256 cpu-supply = <&buck2>;
260 cpu-supply = <&buck2>;
264 operating-points-v2 = <&ddrc_opp_table>;
266 ddrc_opp_table: opp-table {
267 compatible = "operating-points-v2";
270 opp-hz = /bits/ 64 <25000000>;
274 opp-hz = /bits/ 64 <100000000>;
278 opp-hz = /bits/ 64 <750000000>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_fec1>;
286 phy-mode = "rgmii-id";
287 phy-handle = <ðphy0>;
288 local-mac-address = [00 00 00 00 00 00];
292 #address-cells = <1>;
295 ethphy0: ethernet-phy@0 {
296 compatible = "ethernet-phy-ieee802.3-c22";
303 gpio-line-names = "", "", "", "", "", "", "", "",
304 "", "", "", "", "rs232_en#", "", "", "",
305 "", "", "", "", "", "", "", "",
306 "", "", "", "", "", "", "", "";
310 gpio-line-names = "", "", "", "", "", "", "", "",
311 "", "", "", "", "pci_wdis#", "", "", "",
312 "", "", "", "", "", "", "", "",
313 "", "", "", "", "", "", "", "";
317 clock-frequency = <100000>;
318 pinctrl-names = "default", "gpio";
319 pinctrl-0 = <&pinctrl_i2c1>;
320 pinctrl-1 = <&pinctrl_i2c1_gpio>;
321 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
322 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
326 compatible = "gw,gsc";
328 pinctrl-0 = <&pinctrl_gsc>;
329 interrupt-parent = <&gpio4>;
330 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
331 interrupt-controller;
332 #interrupt-cells = <1>;
333 #address-cells = <1>;
337 compatible = "gw,gsc-adc";
338 #address-cells = <1>;
351 gw,voltage-divider-ohms = <22100 1000>;
352 gw,voltage-offset-microvolt = <700000>;
359 gw,voltage-divider-ohms = <10000 10000>;
366 gw,voltage-divider-ohms = <10000 10000>;
403 gw,voltage-divider-ohms = <10000 10000>;
409 compatible = "nxp,pca9555";
413 interrupt-parent = <&gsc>;
418 compatible = "atmel,24c02";
424 compatible = "atmel,24c02";
430 compatible = "atmel,24c02";
436 compatible = "atmel,24c02";
442 compatible = "dallas,ds1672";
448 clock-frequency = <400000>;
449 pinctrl-names = "default", "gpio";
450 pinctrl-0 = <&pinctrl_i2c2>;
451 pinctrl-1 = <&pinctrl_i2c2_gpio>;
452 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
453 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
457 compatible = "rohm,bd71847";
459 pinctrl-names = "default";
460 pinctrl-0 = <&pinctrl_pmic>;
461 interrupt-parent = <&gpio3>;
462 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
463 rohm,reset-snvs-powered;
466 clock-output-names = "clk-32k-out";
469 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
471 regulator-name = "buck1";
472 regulator-min-microvolt = <700000>;
473 regulator-max-microvolt = <1300000>;
476 regulator-ramp-delay = <1250>;
479 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
481 regulator-name = "buck2";
482 regulator-min-microvolt = <700000>;
483 regulator-max-microvolt = <1300000>;
486 regulator-ramp-delay = <1250>;
487 rohm,dvs-run-voltage = <1000000>;
488 rohm,dvs-idle-voltage = <900000>;
491 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
493 regulator-name = "buck3";
494 regulator-min-microvolt = <700000>;
495 regulator-max-microvolt = <1350000>;
502 regulator-name = "buck4";
503 regulator-min-microvolt = <3000000>;
504 regulator-max-microvolt = <3300000>;
511 regulator-name = "buck5";
512 regulator-min-microvolt = <1605000>;
513 regulator-max-microvolt = <1995000>;
520 regulator-name = "buck6";
521 regulator-min-microvolt = <800000>;
522 regulator-max-microvolt = <1400000>;
529 regulator-name = "ldo1";
530 regulator-min-microvolt = <1600000>;
531 regulator-max-microvolt = <1900000>;
538 regulator-name = "ldo2";
539 regulator-min-microvolt = <800000>;
540 regulator-max-microvolt = <900000>;
547 regulator-name = "ldo3";
548 regulator-min-microvolt = <1800000>;
549 regulator-max-microvolt = <3300000>;
555 regulator-name = "ldo4";
556 regulator-min-microvolt = <900000>;
557 regulator-max-microvolt = <1800000>;
563 regulator-name = "ldo6";
564 regulator-min-microvolt = <900000>;
565 regulator-max-microvolt = <1800000>;
574 clock-frequency = <400000>;
575 pinctrl-names = "default", "gpio";
576 pinctrl-0 = <&pinctrl_i2c3>;
577 pinctrl-1 = <&pinctrl_i2c3_gpio>;
578 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
579 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
583 pinctrl-names = "default";
584 pinctrl-0 = <&pinctrl_accel>;
585 compatible = "st,lis2de12";
587 st,drdy-int-pin = <1>;
588 interrupt-parent = <&gpio1>;
589 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
594 clock-frequency = <400000>;
595 pinctrl-names = "default", "gpio";
596 pinctrl-0 = <&pinctrl_i2c4>;
597 pinctrl-1 = <&pinctrl_i2c4_gpio>;
598 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
599 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
603 compatible = "nxp,pca9555";
611 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
612 fsl,clkreq-unsupported;
613 clocks = <&pcie0_refclk>;
619 pinctrl-names = "default";
620 pinctrl-0 = <&pinctrl_pcie0>;
621 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
622 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
623 <&clk IMX8MM_CLK_PCIE1_AUX>;
624 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
625 <&clk IMX8MM_CLK_PCIE1_CTRL>;
626 assigned-clock-rates = <10000000>, <250000000>;
627 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
628 <&clk IMX8MM_SYS_PLL2_250M>;
640 /* off-board RS232 */
642 pinctrl-names = "default";
643 pinctrl-0 = <&pinctrl_uart1>;
644 cts-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
645 rts-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
651 pinctrl-names = "default";
652 pinctrl-0 = <&pinctrl_uart2>;
658 disable-over-current;
664 pinctrl-names = "default", "state_100mhz", "state_200mhz";
665 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
666 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
667 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
668 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
670 vmmc-supply = <®_3p3v>;
676 pinctrl-names = "default", "state_100mhz", "state_200mhz";
677 pinctrl-0 = <&pinctrl_usdhc3>;
678 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
679 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
686 pinctrl-names = "default";
687 pinctrl-0 = <&pinctrl_wdog>;
688 fsl,ext-reset-output;
693 pinctrl-names = "default";
694 pinctrl-0 = <&pinctrl_hog>;
696 pinctrl_hog: hoggrp {
698 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
699 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
703 pinctrl_accel: accelgrp {
705 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
709 pinctrl_fec1: fec1grp {
711 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
712 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
713 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
714 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
715 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
716 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
717 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
718 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
719 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
720 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
721 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
722 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
723 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
724 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
725 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
726 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
730 pinctrl_gpio_leds: gpioledsgrp {
732 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000019
733 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000019
734 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000019
735 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000019
739 pinctrl_gsc: gscgrp {
741 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
745 pinctrl_i2c1: i2c1grp {
747 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
748 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
752 pinctrl_i2c1_gpio: i2c1gpiogrp {
754 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
755 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
759 pinctrl_i2c2: i2c2grp {
761 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
762 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
766 pinctrl_i2c2_gpio: i2c2gpiogrp {
768 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
769 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
773 pinctrl_i2c3: i2c3grp {
775 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
776 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
780 pinctrl_i2c3_gpio: i2c3gpiogrp {
782 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
783 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
787 pinctrl_i2c4: i2c4grp {
789 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
790 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
794 pinctrl_i2c4_gpio: i2c4gpiogrp {
796 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
797 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
801 pinctrl_pcie0: pciegrp {
803 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
807 pinctrl_pmic: pmicgrp {
809 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
813 pinctrl_uart1: uart1grp {
815 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
816 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
817 MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x140 /* CTS# in */
818 MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x140 /* RTS# out */
822 pinctrl_uart2: uart2grp {
824 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
825 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
829 pinctrl_usdhc2: usdhc2grp {
831 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
832 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
833 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
834 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
835 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
836 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
840 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
842 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
843 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
844 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
845 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
846 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
847 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
851 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
853 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
854 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
855 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
856 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
857 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
858 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
862 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
864 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
865 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
869 pinctrl_usdhc3: usdhc3grp {
871 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
872 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
873 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
874 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
875 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
876 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
877 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
878 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
879 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
880 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
881 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
885 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
887 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
888 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
889 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
890 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
891 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
892 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
893 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
894 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
895 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
896 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
897 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
901 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
903 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
904 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
905 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
906 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
907 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
908 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
909 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
910 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
911 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
912 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
913 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
917 pinctrl_wdog: wdoggrp {
919 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6