1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2022 Gateworks Corporation
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
13 #include "imx8mm.dtsi"
16 model = "Gateworks Venice GW7904 i.MX8MM board";
17 compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm";
24 device_type = "memory";
25 reg = <0x0 0x40000000 0 0x80000000>;
29 compatible = "gpio-keys";
33 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
40 interrupt-parent = <&gsc>;
47 interrupt-parent = <&gsc>;
54 interrupt-parent = <&gsc>;
59 label = "switch_hold";
61 interrupt-parent = <&gsc>;
67 compatible = "gpio-leds";
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_gpio_leds>;
72 function = LED_FUNCTION_STATUS;
73 color = <LED_COLOR_ID_GREEN>;
75 gpios = <&gpioled 0 GPIO_ACTIVE_LOW>;
76 default-state = "off";
80 function = LED_FUNCTION_STATUS;
81 color = <LED_COLOR_ID_YELLOW>;
83 gpios = <&gpioled 1 GPIO_ACTIVE_LOW>;
84 default-state = "off";
88 function = LED_FUNCTION_STATUS;
89 color = <LED_COLOR_ID_GREEN>;
91 gpios = <&gpioled 2 GPIO_ACTIVE_LOW>;
92 default-state = "off";
96 function = LED_FUNCTION_STATUS;
97 color = <LED_COLOR_ID_YELLOW>;
99 gpios = <&gpioled 3 GPIO_ACTIVE_LOW>;
100 default-state = "off";
104 function = LED_FUNCTION_STATUS;
105 color = <LED_COLOR_ID_GREEN>;
107 gpios = <&gpioled 4 GPIO_ACTIVE_LOW>;
108 default-state = "off";
112 function = LED_FUNCTION_STATUS;
113 color = <LED_COLOR_ID_YELLOW>;
115 gpios = <&gpioled 5 GPIO_ACTIVE_LOW>;
116 default-state = "off";
120 function = LED_FUNCTION_STATUS;
121 color = <LED_COLOR_ID_GREEN>;
123 gpios = <&gpioled 6 GPIO_ACTIVE_LOW>;
124 default-state = "off";
128 function = LED_FUNCTION_STATUS;
129 color = <LED_COLOR_ID_YELLOW>;
131 gpios = <&gpioled 7 GPIO_ACTIVE_LOW>;
132 default-state = "off";
136 function = LED_FUNCTION_STATUS;
137 color = <LED_COLOR_ID_GREEN>;
139 gpios = <&gpioled 8 GPIO_ACTIVE_LOW>;
140 default-state = "off";
144 function = LED_FUNCTION_STATUS;
145 color = <LED_COLOR_ID_YELLOW>;
147 gpios = <&gpioled 9 GPIO_ACTIVE_LOW>;
148 default-state = "off";
152 function = LED_FUNCTION_STATUS;
153 color = <LED_COLOR_ID_GREEN>;
155 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
156 default-state = "off";
160 function = LED_FUNCTION_STATUS;
161 color = <LED_COLOR_ID_RED>;
163 gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
164 default-state = "off";
168 function = LED_FUNCTION_STATUS;
169 color = <LED_COLOR_ID_GREEN>;
171 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
172 default-state = "off";
176 function = LED_FUNCTION_STATUS;
177 color = <LED_COLOR_ID_RED>;
179 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
180 default-state = "off";
184 function = LED_FUNCTION_STATUS;
185 color = <LED_COLOR_ID_GREEN>;
187 gpios = <&gpioled 10 GPIO_ACTIVE_LOW>;
188 default-state = "off";
192 function = LED_FUNCTION_STATUS;
193 color = <LED_COLOR_ID_YELLOW>;
195 gpios = <&gpioled 11 GPIO_ACTIVE_LOW>;
196 default-state = "off";
200 function = LED_FUNCTION_STATUS;
201 color = <LED_COLOR_ID_GREEN>;
203 gpios = <&gpioled 12 GPIO_ACTIVE_LOW>;
204 default-state = "off";
208 function = LED_FUNCTION_STATUS;
209 color = <LED_COLOR_ID_YELLOW>;
211 gpios = <&gpioled 13 GPIO_ACTIVE_LOW>;
212 default-state = "off";
216 function = LED_FUNCTION_STATUS;
217 color = <LED_COLOR_ID_GREEN>;
219 gpios = <&gpioled 14 GPIO_ACTIVE_LOW>;
220 default-state = "off";
224 function = LED_FUNCTION_STATUS;
225 color = <LED_COLOR_ID_YELLOW>;
227 gpios = <&gpioled 15 GPIO_ACTIVE_LOW>;
228 default-state = "off";
232 pcie0_refclk: pcie0-refclk {
233 compatible = "fixed-clock";
235 clock-frequency = <100000000>;
238 reg_3p3v: regulator-3p3v {
239 compatible = "regulator-fixed";
240 regulator-name = "3P3V";
241 regulator-min-microvolt = <3300000>;
242 regulator-max-microvolt = <3300000>;
248 cpu-supply = <&buck2>;
252 cpu-supply = <&buck2>;
256 cpu-supply = <&buck2>;
260 cpu-supply = <&buck2>;
264 operating-points-v2 = <&ddrc_opp_table>;
266 ddrc_opp_table: opp-table {
267 compatible = "operating-points-v2";
270 opp-hz = /bits/ 64 <25000000>;
274 opp-hz = /bits/ 64 <100000000>;
278 opp-hz = /bits/ 64 <750000000>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_fec1>;
286 phy-mode = "rgmii-id";
287 phy-handle = <ðphy0>;
288 local-mac-address = [00 00 00 00 00 00];
292 #address-cells = <1>;
295 ethphy0: ethernet-phy@0 {
296 compatible = "ethernet-phy-ieee802.3-c22";
303 gpio-line-names = "", "", "", "", "", "", "", "",
304 "", "", "", "", "rs232_en#", "", "", "",
305 "", "", "", "", "", "", "", "",
306 "", "", "", "", "", "", "", "";
310 gpio-line-names = "", "", "", "", "", "", "", "",
311 "", "", "", "", "pci_wdis#", "", "", "",
312 "", "", "", "", "", "", "", "",
313 "", "", "", "", "", "", "", "";
317 clock-frequency = <100000>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_i2c1>;
323 compatible = "gw,gsc";
325 pinctrl-0 = <&pinctrl_gsc>;
326 interrupt-parent = <&gpio4>;
327 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
328 interrupt-controller;
329 #interrupt-cells = <1>;
332 compatible = "gw,gsc-adc";
333 #address-cells = <1>;
346 gw,voltage-divider-ohms = <22100 1000>;
347 gw,voltage-offset-microvolt = <700000>;
354 gw,voltage-divider-ohms = <10000 10000>;
361 gw,voltage-divider-ohms = <10000 10000>;
398 gw,voltage-divider-ohms = <10000 10000>;
404 compatible = "nxp,pca9555";
408 interrupt-parent = <&gsc>;
413 compatible = "atmel,24c02";
419 compatible = "atmel,24c02";
425 compatible = "atmel,24c02";
431 compatible = "atmel,24c02";
437 compatible = "dallas,ds1672";
443 clock-frequency = <400000>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&pinctrl_i2c2>;
449 compatible = "rohm,bd71847";
451 pinctrl-names = "default";
452 pinctrl-0 = <&pinctrl_pmic>;
453 interrupt-parent = <&gpio3>;
454 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
455 rohm,reset-snvs-powered;
457 clocks = <&osc_32k 0>;
458 clock-output-names = "clk-32k-out";
461 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
463 regulator-name = "buck1";
464 regulator-min-microvolt = <700000>;
465 regulator-max-microvolt = <1300000>;
468 regulator-ramp-delay = <1250>;
471 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
473 regulator-name = "buck2";
474 regulator-min-microvolt = <700000>;
475 regulator-max-microvolt = <1300000>;
478 regulator-ramp-delay = <1250>;
479 rohm,dvs-run-voltage = <1000000>;
480 rohm,dvs-idle-voltage = <900000>;
483 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
485 regulator-name = "buck3";
486 regulator-min-microvolt = <700000>;
487 regulator-max-microvolt = <1350000>;
494 regulator-name = "buck4";
495 regulator-min-microvolt = <3000000>;
496 regulator-max-microvolt = <3300000>;
503 regulator-name = "buck5";
504 regulator-min-microvolt = <1605000>;
505 regulator-max-microvolt = <1995000>;
512 regulator-name = "buck6";
513 regulator-min-microvolt = <800000>;
514 regulator-max-microvolt = <1400000>;
521 regulator-name = "ldo1";
522 regulator-min-microvolt = <1600000>;
523 regulator-max-microvolt = <1900000>;
530 regulator-name = "ldo2";
531 regulator-min-microvolt = <800000>;
532 regulator-max-microvolt = <900000>;
539 regulator-name = "ldo3";
540 regulator-min-microvolt = <1800000>;
541 regulator-max-microvolt = <3300000>;
547 regulator-name = "ldo4";
548 regulator-min-microvolt = <900000>;
549 regulator-max-microvolt = <1800000>;
555 regulator-name = "ldo6";
556 regulator-min-microvolt = <900000>;
557 regulator-max-microvolt = <1800000>;
566 clock-frequency = <400000>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&pinctrl_i2c3>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&pinctrl_accel>;
574 compatible = "st,lis2de12";
576 st,drdy-int-pin = <1>;
577 interrupt-parent = <&gpio1>;
578 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
579 interrupt-names = "INT1";
584 clock-frequency = <400000>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&pinctrl_i2c4>;
590 compatible = "nxp,pca9555";
598 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
599 fsl,clkreq-unsupported;
600 clocks = <&pcie0_refclk>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&pinctrl_pcie0>;
608 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
609 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
611 clock-names = "pcie", "pcie_aux", "pcie_bus";
612 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
613 <&clk IMX8MM_CLK_PCIE1_CTRL>;
614 assigned-clock-rates = <10000000>, <250000000>;
615 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
616 <&clk IMX8MM_SYS_PLL2_250M>;
628 /* off-board RS232 */
630 pinctrl-names = "default";
631 pinctrl-0 = <&pinctrl_uart1>;
637 pinctrl-names = "default";
638 pinctrl-0 = <&pinctrl_uart2>;
642 /* off-board RS232 */
644 pinctrl-names = "default";
645 pinctrl-0 = <&pinctrl_uart3>;
651 disable-over-current;
657 pinctrl-names = "default", "state_100mhz", "state_200mhz";
658 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
659 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
660 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
661 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
663 vmmc-supply = <®_3p3v>;
669 pinctrl-names = "default", "state_100mhz", "state_200mhz";
670 pinctrl-0 = <&pinctrl_usdhc3>;
671 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
672 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&pinctrl_wdog>;
681 fsl,ext-reset-output;
686 pinctrl-names = "default";
687 pinctrl-0 = <&pinctrl_hog>;
689 pinctrl_hog: hoggrp {
691 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
692 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
696 pinctrl_accel: accelgrp {
698 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
702 pinctrl_fec1: fec1grp {
704 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
705 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
706 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
707 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
708 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
709 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
710 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
711 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
712 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
713 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
714 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
715 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
716 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
717 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
718 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
719 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
723 pinctrl_gpio_leds: gpioledsgrp {
725 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000019
726 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000019
727 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000019
728 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000019
732 pinctrl_gsc: gscgrp {
734 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
738 pinctrl_i2c1: i2c1grp {
740 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
741 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
745 pinctrl_i2c2: i2c2grp {
747 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
748 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
752 pinctrl_i2c3: i2c3grp {
754 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
755 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
759 pinctrl_i2c4: i2c4grp {
761 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
762 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
766 pinctrl_pcie0: pciegrp {
768 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
772 pinctrl_pmic: pmicgrp {
774 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
778 pinctrl_uart1: uart1grp {
780 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
781 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
785 pinctrl_uart2: uart2grp {
787 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
788 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
792 pinctrl_uart3: uart3grp {
794 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
795 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
799 pinctrl_usdhc2: usdhc2grp {
801 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
802 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
803 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
804 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
805 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
806 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
810 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
812 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
813 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
814 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
815 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
816 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
817 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
821 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
823 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
824 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
825 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
826 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
827 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
828 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
832 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
834 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
835 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
839 pinctrl_usdhc3: usdhc3grp {
841 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
842 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
843 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
844 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
845 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
846 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
847 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
848 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
849 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
850 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
851 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
855 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
857 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
858 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
859 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
860 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
861 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
862 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
863 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
864 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
865 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
866 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
867 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
871 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
873 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
874 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
875 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
876 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
877 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
878 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
879 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
880 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
881 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
882 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
883 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
887 pinctrl_wdog: wdoggrp {
889 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6