1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2021 Gateworks Corporation
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h>
14 #include "imx8mm.dtsi"
17 model = "Gateworks Venice GW7902 i.MX8MM board";
18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
31 device_type = "memory";
32 reg = <0x0 0x40000000 0 0x80000000>;
36 compatible = "fixed-clock";
38 clock-frequency = <20000000>;
39 clock-output-names = "can20m";
43 compatible = "gpio-keys";
47 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
54 interrupt-parent = <&gsc>;
61 interrupt-parent = <&gsc>;
68 interrupt-parent = <&gsc>;
75 interrupt-parent = <&gsc>;
80 label = "switch_hold";
82 interrupt-parent = <&gsc>;
88 compatible = "gpio-leds";
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_gpio_leds>;
93 function = LED_FUNCTION_STATUS;
94 color = <LED_COLOR_ID_GREEN>;
96 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
97 default-state = "off";
101 function = LED_FUNCTION_STATUS;
102 color = <LED_COLOR_ID_GREEN>;
104 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
105 default-state = "off";
109 function = LED_FUNCTION_STATUS;
110 color = <LED_COLOR_ID_GREEN>;
112 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
113 default-state = "off";
117 function = LED_FUNCTION_STATUS;
118 color = <LED_COLOR_ID_GREEN>;
120 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
121 default-state = "off";
125 function = LED_FUNCTION_STATUS;
126 color = <LED_COLOR_ID_GREEN>;
128 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
129 default-state = "off";
133 pcie0_refclk: pcie0-refclk {
134 compatible = "fixed-clock";
136 clock-frequency = <100000000>;
140 compatible = "pps-gpio";
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_pps>;
143 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
147 reg_3p3v: regulator-3p3v {
148 compatible = "regulator-fixed";
149 regulator-name = "3P3V";
150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>;
155 reg_usb1_vbus: regulator-usb1 {
156 compatible = "regulator-fixed";
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_reg_usb1>;
159 regulator-name = "usb_usb1_vbus";
160 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
162 regulator-min-microvolt = <5000000>;
163 regulator-max-microvolt = <5000000>;
166 reg_wifi: regulator-wifi {
167 compatible = "regulator-fixed";
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_reg_wl>;
170 regulator-name = "wifi";
171 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
173 startup-delay-us = <100>;
174 regulator-min-microvolt = <3300000>;
175 regulator-max-microvolt = <3300000>;
180 cpu-supply = <&buck2>;
184 cpu-supply = <&buck2>;
188 cpu-supply = <&buck2>;
192 cpu-supply = <&buck2>;
196 operating-points-v2 = <&ddrc_opp_table>;
198 ddrc_opp_table: opp-table {
199 compatible = "operating-points-v2";
202 opp-hz = /bits/ 64 <25000000>;
206 opp-hz = /bits/ 64 <100000000>;
210 opp-hz = /bits/ 64 <750000000>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_spi1>;
218 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
222 compatible = "microchip,mcp2515";
225 interrupt-parent = <&gpio2>;
226 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
227 spi-max-frequency = <10000000>;
231 /* off-board header */
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_spi2>;
235 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_fec1>;
242 phy-mode = "rgmii-id";
243 phy-handle = <ðphy0>;
244 local-mac-address = [00 00 00 00 00 00];
248 #address-cells = <1>;
251 ethphy0: ethernet-phy@0 {
252 compatible = "ethernet-phy-ieee802.3-c22";
254 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
255 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
256 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
257 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
263 gpio-line-names = "", "", "", "", "", "", "", "",
264 "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
265 "", "", "", "", "", "", "", "",
266 "", "", "", "", "", "", "", "";
270 gpio-line-names = "", "", "", "", "", "", "", "",
271 "uart2_en#", "", "", "", "", "", "", "",
272 "", "", "", "", "", "", "", "",
273 "", "", "", "", "", "", "", "";
277 gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
278 "", "", "", "", "", "", "", "",
279 "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "";
284 gpio-line-names = "", "", "", "", "", "", "", "",
285 "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
286 "lte_pwr#", "lte_rst", "lte_int", "",
287 "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
288 "", "uart1_term", "uart1_half", "app_gpio2",
289 "mipi_gpio1", "", "", "";
293 gpio-line-names = "", "", "", "mipi_gpio4",
294 "mipi_gpio3", "mipi_gpio2", "", "",
295 "", "", "", "", "", "", "", "",
296 "", "", "", "", "", "", "", "",
297 "", "", "", "", "", "", "", "";
301 clock-frequency = <100000>;
302 pinctrl-names = "default", "gpio";
303 pinctrl-0 = <&pinctrl_i2c1>;
304 pinctrl-1 = <&pinctrl_i2c1_gpio>;
305 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
306 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
310 compatible = "gw,gsc";
312 pinctrl-0 = <&pinctrl_gsc>;
313 interrupt-parent = <&gpio2>;
314 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
315 interrupt-controller;
316 #interrupt-cells = <1>;
317 #address-cells = <1>;
321 compatible = "gw,gsc-adc";
322 #address-cells = <1>;
341 gw,voltage-divider-ohms = <22100 1000>;
342 gw,voltage-offset-microvolt = <700000>;
349 gw,voltage-divider-ohms = <10000 10000>;
356 gw,voltage-divider-ohms = <10000 10000>;
399 gw,voltage-divider-ohms = <10000 10000>;
406 gw,voltage-divider-ohms = <10000 10000>;
413 gw,voltage-divider-ohms = <10000 10000>;
419 compatible = "nxp,pca9555";
423 interrupt-parent = <&gsc>;
428 compatible = "rohm,bd71847";
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_pmic>;
432 interrupt-parent = <&gpio3>;
433 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
434 rohm,reset-snvs-powered;
437 clock-output-names = "clk-32k-out";
440 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
442 regulator-name = "buck1";
443 regulator-min-microvolt = <700000>;
444 regulator-max-microvolt = <1300000>;
447 regulator-ramp-delay = <1250>;
450 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
452 regulator-name = "buck2";
453 regulator-min-microvolt = <700000>;
454 regulator-max-microvolt = <1300000>;
457 regulator-ramp-delay = <1250>;
458 rohm,dvs-run-voltage = <1000000>;
459 rohm,dvs-idle-voltage = <900000>;
462 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
464 regulator-name = "buck3";
465 regulator-min-microvolt = <700000>;
466 regulator-max-microvolt = <1350000>;
473 regulator-name = "buck4";
474 regulator-min-microvolt = <3000000>;
475 regulator-max-microvolt = <3300000>;
482 regulator-name = "buck5";
483 regulator-min-microvolt = <1605000>;
484 regulator-max-microvolt = <1995000>;
491 regulator-name = "buck6";
492 regulator-min-microvolt = <800000>;
493 regulator-max-microvolt = <1400000>;
500 regulator-name = "ldo1";
501 regulator-min-microvolt = <1600000>;
502 regulator-max-microvolt = <1900000>;
509 regulator-name = "ldo2";
510 regulator-min-microvolt = <800000>;
511 regulator-max-microvolt = <900000>;
518 regulator-name = "ldo3";
519 regulator-min-microvolt = <1800000>;
520 regulator-max-microvolt = <3300000>;
526 regulator-name = "ldo4";
527 regulator-min-microvolt = <900000>;
528 regulator-max-microvolt = <1800000>;
534 regulator-name = "ldo6";
535 regulator-min-microvolt = <900000>;
536 regulator-max-microvolt = <1800000>;
544 compatible = "atmel,24c02";
550 compatible = "atmel,24c02";
556 compatible = "atmel,24c02";
562 compatible = "atmel,24c02";
568 compatible = "dallas,ds1672";
574 clock-frequency = <400000>;
575 pinctrl-names = "default", "gpio";
576 pinctrl-0 = <&pinctrl_i2c2>;
577 pinctrl-1 = <&pinctrl_i2c2_gpio>;
578 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
579 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
583 compatible = "st,lis2de12";
584 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_accel>;
587 st,drdy-int-pin = <1>;
588 interrupt-parent = <&gpio1>;
589 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
593 /* off-board header */
595 clock-frequency = <400000>;
596 pinctrl-names = "default", "gpio";
597 pinctrl-0 = <&pinctrl_i2c3>;
598 pinctrl-1 = <&pinctrl_i2c3_gpio>;
599 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
600 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
604 /* off-board header */
606 clock-frequency = <400000>;
607 pinctrl-names = "default", "gpio";
608 pinctrl-0 = <&pinctrl_i2c4>;
609 pinctrl-1 = <&pinctrl_i2c4_gpio>;
610 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
611 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
616 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
617 fsl,clkreq-unsupported;
618 clocks = <&pcie0_refclk>;
624 pinctrl-names = "default";
625 pinctrl-0 = <&pinctrl_pcie0>;
626 reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
627 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
628 <&clk IMX8MM_CLK_PCIE1_AUX>;
629 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
630 <&clk IMX8MM_CLK_PCIE1_CTRL>;
631 assigned-clock-rates = <10000000>, <250000000>;
632 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
633 <&clk IMX8MM_SYS_PLL2_250M>;
637 reg = <0x0000 0 0 0 0>;
638 #address-cells = <1>;
642 reg = <0x0000 0 0 0 0>;
643 #address-cells = <1>;
646 local-mac-address = [00 00 00 00 00 00];
651 /* off-board header */
653 pinctrl-names = "default";
654 pinctrl-0 = <&pinctrl_sai3>;
655 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
656 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
657 assigned-clock-rates = <24576000>;
661 /* RS232/RS485/RS422 selectable */
663 pinctrl-names = "default";
664 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
665 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
666 cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
672 pinctrl-names = "default";
673 pinctrl-0 = <&pinctrl_uart2>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
681 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
682 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
686 compatible = "brcm,bcm4330-bt";
687 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
691 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
693 pinctrl-names = "default";
694 pinctrl-0 = <&pinctrl_uart4>;
695 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
696 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
697 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
698 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
699 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
705 vbus-supply = <®_usb1_vbus>;
706 disable-over-current;
712 disable-over-current;
718 pinctrl-names = "default", "state_100mhz", "state_200mhz";
719 pinctrl-0 = <&pinctrl_usdhc2>;
720 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
721 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
724 vmmc-supply = <®_wifi>;
725 #address-cells = <1>;
730 compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac";
737 pinctrl-names = "default", "state_100mhz", "state_200mhz";
738 pinctrl-0 = <&pinctrl_usdhc3>;
739 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
740 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
747 pinctrl-names = "default";
748 pinctrl-0 = <&pinctrl_wdog>;
749 fsl,ext-reset-output;
754 pinctrl-names = "default";
755 pinctrl-0 = <&pinctrl_hog>;
757 pinctrl_hog: hoggrp {
759 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
760 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */
761 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
762 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
763 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
764 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */
765 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */
766 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */
767 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
768 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
769 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */
770 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */
771 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
772 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */
773 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
774 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
775 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
776 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
777 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
778 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
782 pinctrl_accel: accelgrp {
784 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
788 pinctrl_fec1: fec1grp {
790 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
791 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
792 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
793 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
794 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
795 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
796 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
797 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
798 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
799 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
800 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
801 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
802 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
803 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
804 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
805 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
809 pinctrl_gsc: gscgrp {
811 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
815 pinctrl_i2c1: i2c1grp {
817 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
818 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
822 pinctrl_i2c1_gpio: i2c1gpiogrp {
824 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
825 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
829 pinctrl_i2c2: i2c2grp {
831 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
832 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
836 pinctrl_i2c2_gpio: i2c2gpiogrp {
838 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
839 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
843 pinctrl_i2c3: i2c3grp {
845 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
846 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
850 pinctrl_i2c3_gpio: i2c3gpiogrp {
852 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
853 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
857 pinctrl_i2c4: i2c4grp {
859 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
860 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
864 pinctrl_i2c4_gpio: i2c4gpiogrp {
866 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
867 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
871 pinctrl_gpio_leds: gpioledgrp {
873 MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
874 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
875 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
876 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
877 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
881 pinctrl_pcie0: pciegrp {
883 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41
887 pinctrl_pmic: pmicgrp {
889 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
893 pinctrl_pps: ppsgrp {
895 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
899 pinctrl_reg_wl: regwlgrp {
901 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
905 pinctrl_reg_usb1: regusb1grp {
907 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
911 pinctrl_sai3: sai3grp {
913 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
914 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
915 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
916 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
917 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
921 pinctrl_spi1: spi1grp {
923 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
924 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
925 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
926 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
927 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
931 pinctrl_spi2: spi2grp {
933 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
934 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
935 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
936 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
940 pinctrl_uart1: uart1grp {
942 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
943 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
944 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */
945 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */
949 pinctrl_uart1_gpio: uart1gpiogrp {
951 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
952 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
953 MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
957 pinctrl_uart2: uart2grp {
959 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
960 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
964 pinctrl_uart3_gpio: uart3_gpiogrp {
966 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
970 pinctrl_uart3: uart3grp {
972 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
973 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
974 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
975 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
979 pinctrl_uart4: uart4grp {
981 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
982 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
983 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */
984 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */
985 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */
986 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */
987 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */
988 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */
989 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */
990 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
994 pinctrl_usdhc2: usdhc2grp {
996 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
997 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
998 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
999 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
1000 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
1001 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
1005 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1007 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
1008 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
1009 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
1010 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
1011 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
1012 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
1016 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1018 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
1019 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
1020 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
1021 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
1022 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
1023 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
1027 pinctrl_usdhc3: usdhc3grp {
1029 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
1030 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
1031 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
1032 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
1033 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
1034 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
1035 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
1036 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
1037 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
1038 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
1039 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
1043 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1045 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
1046 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
1047 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
1048 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
1049 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
1050 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
1051 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
1052 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
1053 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
1054 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
1055 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
1059 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1061 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
1062 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
1063 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
1064 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
1065 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
1066 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
1067 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
1068 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
1069 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
1070 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
1071 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
1075 pinctrl_wdog: wdoggrp {
1077 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6