arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2021 Gateworks Corporation
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/linux-event-codes.h>
  10 #include <dt-bindings/leds/common.h>
  11 #include <dt-bindings/net/ti-dp83867.h>
  12 #include <dt-bindings/phy/phy-imx8-pcie.h>
  13
  14 #include "imx8mm.dtsi"
  15
  16 / {
  17         model = "Gateworks Venice GW7902 i.MX8MM board";
  18         compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
  19
  20         aliases {
  21                 ethernet1 = &eth1;
  22                 usb0 = &usbotg1;
  23                 usb1 = &usbotg2;
  24         };
  25
  26         chosen {
  27                 stdout-path = &uart2;
  28         };
  29
  30         memory@40000000 {
  31                 device_type = "memory";
  32                 reg = <0x0 0x40000000 0 0x80000000>;
  33         };
  34
  35         can20m: can20m {
  36                 compatible = "fixed-clock";
  37                 #clock-cells = <0>;
  38                 clock-frequency = <20000000>;
  39                 clock-output-names = "can20m";
  40         };
  41
  42         gpio-keys {
  43                 compatible = "gpio-keys";
  44
  45                 key-user-pb {
  46                         label = "user_pb";
  47                         gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
  48                         linux,code = <BTN_0>;
  49                 };
  50
  51                 key-user-pb1x {
  52                         label = "user_pb1x";
  53                         linux,code = <BTN_1>;
  54                         interrupt-parent = <&gsc>;
  55                         interrupts = <0>;
  56                 };
  57
  58                 key-erased {
  59                         label = "key_erased";
  60                         linux,code = <BTN_2>;
  61                         interrupt-parent = <&gsc>;
  62                         interrupts = <1>;
  63                 };
  64
  65                 key-eeprom-wp {
  66                         label = "eeprom_wp";
  67                         linux,code = <BTN_3>;
  68                         interrupt-parent = <&gsc>;
  69                         interrupts = <2>;
  70                 };
  71
  72                 key-tamper {
  73                         label = "tamper";
  74                         linux,code = <BTN_4>;
  75                         interrupt-parent = <&gsc>;
  76                         interrupts = <5>;
  77                 };
  78
  79                 switch-hold {
  80                         label = "switch_hold";
  81                         linux,code = <BTN_5>;
  82                         interrupt-parent = <&gsc>;
  83                         interrupts = <7>;
  84                 };
  85         };
  86
  87         led-controller {
  88                 compatible = "gpio-leds";
  89                 pinctrl-names = "default";
  90                 pinctrl-0 = <&pinctrl_gpio_leds>;
  91
  92                 led-0 {
  93                         function = LED_FUNCTION_STATUS;
  94                         color = <LED_COLOR_ID_GREEN>;
  95                         label = "panel1";
  96                         gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
  97                         default-state = "off";
  98                 };
  99
 100                 led-1 {
 101                         function = LED_FUNCTION_STATUS;
 102                         color = <LED_COLOR_ID_GREEN>;
 103                         label = "panel2";
 104                         gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 105                         default-state = "off";
 106                 };
 107
 108                 led-2 {
 109                         function = LED_FUNCTION_STATUS;
 110                         color = <LED_COLOR_ID_GREEN>;
 111                         label = "panel3";
 112                         gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
 113                         default-state = "off";
 114                 };
 115
 116                 led-3 {
 117                         function = LED_FUNCTION_STATUS;
 118                         color = <LED_COLOR_ID_GREEN>;
 119                         label = "panel4";
 120                         gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
 121                         default-state = "off";
 122                 };
 123
 124                 led-4 {
 125                         function = LED_FUNCTION_STATUS;
 126                         color = <LED_COLOR_ID_GREEN>;
 127                         label = "panel5";
 128                         gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
 129                         default-state = "off";
 130                 };
 131         };
 132
 133         pcie0_refclk: pcie0-refclk {
 134                 compatible = "fixed-clock";
 135                 #clock-cells = <0>;
 136                 clock-frequency = <100000000>;
 137         };
 138
 139         pps {
 140                 compatible = "pps-gpio";
 141                 pinctrl-names = "default";
 142                 pinctrl-0 = <&pinctrl_pps>;
 143                 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
 144                 status = "okay";
 145         };
 146
 147         reg_3p3v: regulator-3p3v {
 148                 compatible = "regulator-fixed";
 149                 regulator-name = "3P3V";
 150                 regulator-min-microvolt = <3300000>;
 151                 regulator-max-microvolt = <3300000>;
 152                 regulator-always-on;
 153         };
 154
 155         reg_usb1_vbus: regulator-usb1 {
 156                 compatible = "regulator-fixed";
 157                 pinctrl-names = "default";
 158                 pinctrl-0 = <&pinctrl_reg_usb1>;
 159                 regulator-name = "usb_usb1_vbus";
 160                 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
 161                 enable-active-high;
 162                 regulator-min-microvolt = <5000000>;
 163                 regulator-max-microvolt = <5000000>;
 164         };
 165
 166         reg_wifi: regulator-wifi {
 167                 compatible = "regulator-fixed";
 168                 pinctrl-names = "default";
 169                 pinctrl-0 = <&pinctrl_reg_wl>;
 170                 regulator-name = "wifi";
 171                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
 172                 enable-active-high;
 173                 startup-delay-us = <100>;
 174                 regulator-min-microvolt = <3300000>;
 175                 regulator-max-microvolt = <3300000>;
 176         };
 177 };
 178
 179 &A53_0 {
 180         cpu-supply = <&buck2>;
 181 };
 182
 183 &A53_1 {
 184         cpu-supply = <&buck2>;
 185 };
 186
 187 &A53_2 {
 188         cpu-supply = <&buck2>;
 189 };
 190
 191 &A53_3 {
 192         cpu-supply = <&buck2>;
 193 };
 194
 195 &ddrc {
 196         operating-points-v2 = <&ddrc_opp_table>;
 197
 198         ddrc_opp_table: opp-table {
 199                 compatible = "operating-points-v2";
 200
 201                 opp-25M {
 202                         opp-hz = /bits/ 64 <25000000>;
 203                 };
 204
 205                 opp-100M {
 206                         opp-hz = /bits/ 64 <100000000>;
 207                 };
 208
 209                 opp-750M {
 210                         opp-hz = /bits/ 64 <750000000>;
 211                 };
 212         };
 213 };
 214
 215 &ecspi1 {
 216         pinctrl-names = "default";
 217         pinctrl-0 = <&pinctrl_spi1>;
 218         cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 219         status = "okay";
 220
 221         can@0 {
 222                 compatible = "microchip,mcp2515";
 223                 reg = <0>;
 224                 clocks = <&can20m>;
 225                 interrupt-parent = <&gpio2>;
 226                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 227                 spi-max-frequency = <10000000>;
 228         };
 229 };
 230
 231 /* off-board header */
 232 &ecspi2 {
 233         pinctrl-names = "default";
 234         pinctrl-0 = <&pinctrl_spi2>;
 235         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 236         status = "okay";
 237 };
 238
 239 &fec1 {
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_fec1>;
 242         phy-mode = "rgmii-id";
 243         phy-handle = <&ethphy0>;
 244         local-mac-address = [00 00 00 00 00 00];
 245         status = "okay";
 246
 247         mdio {
 248                 #address-cells = <1>;
 249                 #size-cells = <0>;
 250
 251                 ethphy0: ethernet-phy@0 {
 252                         compatible = "ethernet-phy-ieee802.3-c22";
 253                         reg = <0>;
 254                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 255                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 256                         tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 257                         rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 258                 };
 259         };
 260 };
 261
 262 &gpio1 {
 263         gpio-line-names = "", "", "", "", "", "", "", "",
 264                 "", "", "", "", "", "m2_reset", "", "m2_wdis#",
 265                 "", "", "", "", "", "", "", "",
 266                 "", "", "", "", "", "", "", "";
 267 };
 268
 269 &gpio2 {
 270         gpio-line-names = "", "", "", "", "", "", "", "",
 271                 "uart2_en#", "", "", "", "", "", "", "",
 272                 "", "", "", "", "", "", "", "",
 273                 "", "", "", "", "", "", "", "";
 274 };
 275
 276 &gpio3 {
 277         gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
 278                 "", "", "", "", "", "", "", "",
 279                 "", "", "", "", "", "", "", "",
 280                 "", "", "", "", "", "", "", "";
 281 };
 282
 283 &gpio4 {
 284         gpio-line-names = "", "", "", "", "", "", "", "",
 285                 "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
 286                 "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485",
 287                 "", "uart1_term", "uart1_half", "app_gpio2",
 288                 "mipi_gpio1", "", "", "";
 289 };
 290
 291 &gpio5 {
 292         gpio-line-names = "", "", "", "mipi_gpio4",
 293                 "mipi_gpio3", "mipi_gpio2", "", "",
 294                 "", "", "", "", "", "", "", "",
 295                 "", "", "", "", "", "", "", "",
 296                 "", "", "", "", "", "", "", "";
 297 };
 298
 299 &i2c1 {
 300         clock-frequency = <100000>;
 301         pinctrl-names = "default";
 302         pinctrl-0 = <&pinctrl_i2c1>;
 303         status = "okay";
 304
 305         gsc: gsc@20 {
 306                 compatible = "gw,gsc";
 307                 reg = <0x20>;
 308                 pinctrl-0 = <&pinctrl_gsc>;
 309                 interrupt-parent = <&gpio2>;
 310                 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
 311                 interrupt-controller;
 312                 #interrupt-cells = <1>;
 313
 314                 adc {
 315                         compatible = "gw,gsc-adc";
 316                         #address-cells = <1>;
 317                         #size-cells = <0>;
 318
 319                         channel@6 {
 320                                 gw,mode = <0>;
 321                                 reg = <0x06>;
 322                                 label = "temp";
 323                         };
 324
 325                         channel@8 {
 326                                 gw,mode = <1>;
 327                                 reg = <0x08>;
 328                                 label = "vdd_bat";
 329                         };
 330
 331                         channel@82 {
 332                                 gw,mode = <2>;
 333                                 reg = <0x82>;
 334                                 label = "vin";
 335                                 gw,voltage-divider-ohms = <22100 1000>;
 336                                 gw,voltage-offset-microvolt = <700000>;
 337                         };
 338
 339                         channel@84 {
 340                                 gw,mode = <2>;
 341                                 reg = <0x84>;
 342                                 label = "vin_4p0";
 343                                 gw,voltage-divider-ohms = <10000 10000>;
 344                         };
 345
 346                         channel@86 {
 347                                 gw,mode = <2>;
 348                                 reg = <0x86>;
 349                                 label = "vdd_3p3";
 350                                 gw,voltage-divider-ohms = <10000 10000>;
 351                         };
 352
 353                         channel@88 {
 354                                 gw,mode = <2>;
 355                                 reg = <0x88>;
 356                                 label = "vdd_0p9";
 357                         };
 358
 359                         channel@8c {
 360                                 gw,mode = <2>;
 361                                 reg = <0x8c>;
 362                                 label = "vdd_soc";
 363                         };
 364
 365                         channel@8e {
 366                                 gw,mode = <2>;
 367                                 reg = <0x8e>;
 368                                 label = "vdd_arm";
 369                         };
 370
 371                         channel@90 {
 372                                 gw,mode = <2>;
 373                                 reg = <0x90>;
 374                                 label = "vdd_1p8";
 375                         };
 376
 377                         channel@92 {
 378                                 gw,mode = <2>;
 379                                 reg = <0x92>;
 380                                 label = "vdd_dram";
 381                         };
 382
 383                         channel@98 {
 384                                 gw,mode = <2>;
 385                                 reg = <0x98>;
 386                                 label = "vdd_1p0";
 387                         };
 388
 389                         channel@9a {
 390                                 gw,mode = <2>;
 391                                 reg = <0x9a>;
 392                                 label = "vdd_2p5";
 393                                 gw,voltage-divider-ohms = <10000 10000>;
 394                         };
 395
 396                         channel@9c {
 397                                 gw,mode = <2>;
 398                                 reg = <0x9c>;
 399                                 label = "vdd_5p0";
 400                                 gw,voltage-divider-ohms = <10000 10000>;
 401                         };
 402
 403                         channel@a2 {
 404                                 gw,mode = <2>;
 405                                 reg = <0xa2>;
 406                                 label = "vdd_gsc";
 407                                 gw,voltage-divider-ohms = <10000 10000>;
 408                         };
 409                 };
 410         };
 411
 412         gpio: gpio@23 {
 413                 compatible = "nxp,pca9555";
 414                 reg = <0x23>;
 415                 gpio-controller;
 416                 #gpio-cells = <2>;
 417                 interrupt-parent = <&gsc>;
 418                 interrupts = <4>;
 419         };
 420
 421         pmic@4b {
 422                 compatible = "rohm,bd71847";
 423                 reg = <0x4b>;
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&pinctrl_pmic>;
 426                 interrupt-parent = <&gpio3>;
 427                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 428                 rohm,reset-snvs-powered;
 429                 #clock-cells = <0>;
 430                 clocks = <&osc_32k 0>;
 431                 clock-output-names = "clk-32k-out";
 432
 433                 regulators {
 434                         /* vdd_soc: 0.805-0.900V (typ=0.8V) */
 435                         BUCK1 {
 436                                 regulator-name = "buck1";
 437                                 regulator-min-microvolt = <700000>;
 438                                 regulator-max-microvolt = <1300000>;
 439                                 regulator-boot-on;
 440                                 regulator-always-on;
 441                                 regulator-ramp-delay = <1250>;
 442                         };
 443
 444                         /* vdd_arm: 0.805-1.0V (typ=0.9V) */
 445                         buck2: BUCK2 {
 446                                 regulator-name = "buck2";
 447                                 regulator-min-microvolt = <700000>;
 448                                 regulator-max-microvolt = <1300000>;
 449                                 regulator-boot-on;
 450                                 regulator-always-on;
 451                                 regulator-ramp-delay = <1250>;
 452                                 rohm,dvs-run-voltage = <1000000>;
 453                                 rohm,dvs-idle-voltage = <900000>;
 454                         };
 455
 456                         /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
 457                         BUCK3 {
 458                                 regulator-name = "buck3";
 459                                 regulator-min-microvolt = <700000>;
 460                                 regulator-max-microvolt = <1350000>;
 461                                 regulator-boot-on;
 462                                 regulator-always-on;
 463                         };
 464
 465                         /* vdd_3p3 */
 466                         BUCK4 {
 467                                 regulator-name = "buck4";
 468                                 regulator-min-microvolt = <3000000>;
 469                                 regulator-max-microvolt = <3300000>;
 470                                 regulator-boot-on;
 471                                 regulator-always-on;
 472                         };
 473
 474                         /* vdd_1p8 */
 475                         BUCK5 {
 476                                 regulator-name = "buck5";
 477                                 regulator-min-microvolt = <1605000>;
 478                                 regulator-max-microvolt = <1995000>;
 479                                 regulator-boot-on;
 480                                 regulator-always-on;
 481                         };
 482
 483                         /* vdd_dram */
 484                         BUCK6 {
 485                                 regulator-name = "buck6";
 486                                 regulator-min-microvolt = <800000>;
 487                                 regulator-max-microvolt = <1400000>;
 488                                 regulator-boot-on;
 489                                 regulator-always-on;
 490                         };
 491
 492                         /* nvcc_snvs_1p8 */
 493                         LDO1 {
 494                                 regulator-name = "ldo1";
 495                                 regulator-min-microvolt = <1600000>;
 496                                 regulator-max-microvolt = <1900000>;
 497                                 regulator-boot-on;
 498                                 regulator-always-on;
 499                         };
 500
 501                         /* vdd_snvs_0p8 */
 502                         LDO2 {
 503                                 regulator-name = "ldo2";
 504                                 regulator-min-microvolt = <800000>;
 505                                 regulator-max-microvolt = <900000>;
 506                                 regulator-boot-on;
 507                                 regulator-always-on;
 508                         };
 509
 510                         /* vdda_1p8 */
 511                         LDO3 {
 512                                 regulator-name = "ldo3";
 513                                 regulator-min-microvolt = <1800000>;
 514                                 regulator-max-microvolt = <3300000>;
 515                                 regulator-boot-on;
 516                                 regulator-always-on;
 517                         };
 518
 519                         LDO4 {
 520                                 regulator-name = "ldo4";
 521                                 regulator-min-microvolt = <900000>;
 522                                 regulator-max-microvolt = <1800000>;
 523                                 regulator-boot-on;
 524                                 regulator-always-on;
 525                         };
 526
 527                         LDO6 {
 528                                 regulator-name = "ldo6";
 529                                 regulator-min-microvolt = <900000>;
 530                                 regulator-max-microvolt = <1800000>;
 531                                 regulator-boot-on;
 532                                 regulator-always-on;
 533                         };
 534                 };
 535         };
 536
 537         eeprom@50 {
 538                 compatible = "atmel,24c02";
 539                 reg = <0x50>;
 540                 pagesize = <16>;
 541         };
 542
 543         eeprom@51 {
 544                 compatible = "atmel,24c02";
 545                 reg = <0x51>;
 546                 pagesize = <16>;
 547         };
 548
 549         eeprom@52 {
 550                 compatible = "atmel,24c02";
 551                 reg = <0x52>;
 552                 pagesize = <16>;
 553         };
 554
 555         eeprom@53 {
 556                 compatible = "atmel,24c02";
 557                 reg = <0x53>;
 558                 pagesize = <16>;
 559         };
 560
 561         rtc@68 {
 562                 compatible = "dallas,ds1672";
 563                 reg = <0x68>;
 564         };
 565 };
 566
 567 &i2c2 {
 568         clock-frequency = <400000>;
 569         pinctrl-names = "default";
 570         pinctrl-0 = <&pinctrl_i2c2>;
 571         status = "okay";
 572
 573         accelerometer@19 {
 574                 compatible = "st,lis2de12";
 575                 pinctrl-names = "default";
 576                 pinctrl-0 = <&pinctrl_accel>;
 577                 reg = <0x19>;
 578                 st,drdy-int-pin = <1>;
 579                 interrupt-parent = <&gpio1>;
 580                 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
 581                 interrupt-names = "INT1";
 582         };
 583 };
 584
 585 /* off-board header */
 586 &i2c3 {
 587         clock-frequency = <400000>;
 588         pinctrl-names = "default";
 589         pinctrl-0 = <&pinctrl_i2c3>;
 590         status = "okay";
 591 };
 592
 593 /* off-board header */
 594 &i2c4 {
 595         clock-frequency = <400000>;
 596         pinctrl-names = "default";
 597         pinctrl-0 = <&pinctrl_i2c4>;
 598         status = "okay";
 599 };
 600
 601 &pcie_phy {
 602         fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
 603         fsl,clkreq-unsupported;
 604         clocks = <&pcie0_refclk>;
 605         clock-names = "ref";
 606         status = "okay";
 607 };
 608
 609 &pcie0 {
 610         pinctrl-names = "default";
 611         pinctrl-0 = <&pinctrl_pcie0>;
 612         reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
 613         clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
 614                  <&pcie0_refclk>;
 615         clock-names = "pcie", "pcie_aux", "pcie_bus";
 616         assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 617                           <&clk IMX8MM_CLK_PCIE1_CTRL>;
 618         assigned-clock-rates = <10000000>, <250000000>;
 619         assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 620                                  <&clk IMX8MM_SYS_PLL2_250M>;
 621         status = "okay";
 622
 623         pcie@0,0 {
 624                 reg = <0x0000 0 0 0 0>;
 625                 #address-cells = <1>;
 626                 #size-cells = <0>;
 627
 628                 eth1: pcie@1,0 {
 629                         reg = <0x0000 0 0 0 0>;
 630                         #address-cells = <1>;
 631                         #size-cells = <0>;
 632
 633                         local-mac-address = [00 00 00 00 00 00];
 634                 };
 635         };
 636 };
 637
 638 /* off-board header */
 639 &sai3 {
 640         pinctrl-names = "default";
 641         pinctrl-0 = <&pinctrl_sai3>;
 642         assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
 643         assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
 644         assigned-clock-rates = <24576000>;
 645         status = "okay";
 646 };
 647
 648 /* RS232/RS485/RS422 selectable */
 649 &uart1 {
 650         pinctrl-names = "default";
 651         pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
 652         rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
 653         cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
 654         status = "okay";
 655 };
 656
 657 /* RS232 console */
 658 &uart2 {
 659         pinctrl-names = "default";
 660         pinctrl-0 = <&pinctrl_uart2>;
 661         status = "okay";
 662 };
 663
 664 /* bluetooth HCI */
 665 &uart3 {
 666         pinctrl-names = "default";
 667         pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
 668         rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
 669         cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 670         status = "okay";
 671
 672         bluetooth {
 673                 compatible = "brcm,bcm4330-bt";
 674                 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 675         };
 676 };
 677
 678 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
 679 &uart4 {
 680         pinctrl-names = "default";
 681         pinctrl-0 = <&pinctrl_uart4>;
 682         rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
 683         cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
 684         dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
 685         dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
 686         dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
 687         status = "okay";
 688 };
 689
 690 &usbotg1 {
 691         dr_mode = "host";
 692         vbus-supply = <&reg_usb1_vbus>;
 693         disable-over-current;
 694         status = "okay";
 695 };
 696
 697 &usbotg2 {
 698         dr_mode = "host";
 699         disable-over-current;
 700         status = "okay";
 701 };
 702
 703 /* SDIO WiFi */
 704 &usdhc2 {
 705         pinctrl-names = "default";
 706         pinctrl-0 = <&pinctrl_usdhc2>;
 707         bus-width = <4>;
 708         non-removable;
 709         vmmc-supply = <&reg_wifi>;
 710         status = "okay";
 711 };
 712
 713 /* eMMC */
 714 &usdhc3 {
 715         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 716         pinctrl-0 = <&pinctrl_usdhc3>;
 717         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 718         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 719         bus-width = <8>;
 720         non-removable;
 721         status = "okay";
 722 };
 723
 724 &wdog1 {
 725         pinctrl-names = "default";
 726         pinctrl-0 = <&pinctrl_wdog>;
 727         fsl,ext-reset-output;
 728         status = "okay";
 729 };
 730
 731 &iomuxc {
 732         pinctrl-names = "default";
 733         pinctrl-0 = <&pinctrl_hog>;
 734
 735         pinctrl_hog: hoggrp {
 736                 fsl,pins = <
 737                         MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1       0x40000159 /* M2_GDIS# */
 738                         MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13      0x40000041 /* M2_RESET */
 739                         MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7      0x40000119 /* M2_OFF# */
 740                         MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x40000159 /* M2_WDIS# */
 741                         MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14       0x40000041 /* AMP GPIO1 */
 742                         MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12       0x40000041 /* AMP GPIO2 */
 743                         MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11        0x40000041 /* AMP GPIO3 */
 744                         MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20       0x40000041 /* AMP_GPIO4 */
 745                         MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x40000041 /* APP GPIO1 */
 746                         MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27       0x40000041 /* APP GPIO2 */
 747                         MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8        0x40000041 /* UART2_EN# */
 748                         MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28       0x40000041 /* MIPI_GPIO1 */
 749                         MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5    0x40000041 /* MIPI_GPIO2 */
 750                         MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4         0x40000041 /* MIPI_GPIO3/PWM2 */
 751                         MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3         0x40000041 /* MIPI_GPIO4/PWM3 */
 752                 >;
 753         };
 754
 755         pinctrl_accel: accelgrp {
 756                 fsl,pins = <
 757                         MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x159
 758                 >;
 759         };
 760
 761         pinctrl_fec1: fec1grp {
 762                 fsl,pins = <
 763                         MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 764                         MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 765                         MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 766                         MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 767                         MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 768                         MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 769                         MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 770                         MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 771                         MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 772                         MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 773                         MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 774                         MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 775                         MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 776                         MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 777                         MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10              0x19 /* RST# */
 778                         MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11              0x19 /* IRQ# */
 779                         MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN    0x141
 780                         MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT   0x141
 781                 >;
 782         };
 783
 784         pinctrl_gsc: gscgrp {
 785                 fsl,pins = <
 786                         MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6        0x40
 787                 >;
 788         };
 789
 790         pinctrl_i2c1: i2c1grp {
 791                 fsl,pins = <
 792                         MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 793                         MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 794                 >;
 795         };
 796
 797         pinctrl_i2c2: i2c2grp {
 798                 fsl,pins = <
 799                         MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c3
 800                         MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c3
 801                 >;
 802         };
 803
 804         pinctrl_i2c3: i2c3grp {
 805                 fsl,pins = <
 806                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 807                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 808                 >;
 809         };
 810
 811         pinctrl_i2c4: i2c4grp {
 812                 fsl,pins = <
 813                         MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL          0x400001c3
 814                         MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA          0x400001c3
 815                 >;
 816         };
 817
 818         pinctrl_gpio_leds: gpioledgrp {
 819                 fsl,pins = <
 820                         MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21       0x19
 821                         MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23       0x19
 822                         MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22       0x19
 823                         MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20        0x19
 824                         MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25       0x19
 825                 >;
 826         };
 827
 828         pinctrl_pcie0: pciegrp {
 829                 fsl,pins = <
 830                         MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5        0x41
 831                 >;
 832         };
 833
 834         pinctrl_pmic: pmicgrp {
 835                 fsl,pins = <
 836                         MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8      0x41
 837                 >;
 838         };
 839
 840         pinctrl_pps: ppsgrp {
 841                 fsl,pins = <
 842                         MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24       0x141 /* PPS */
 843                 >;
 844         };
 845
 846         pinctrl_reg_wl: regwlgrp {
 847                 fsl,pins = <
 848                         MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41 /* WLAN_WLON */
 849                 >;
 850         };
 851
 852         pinctrl_reg_usb1: regusb1grp {
 853                 fsl,pins = <
 854                         MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7        0x41
 855                 >;
 856         };
 857
 858         pinctrl_sai3: sai3grp {
 859                 fsl,pins = <
 860                         MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
 861                         MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0     0xd6
 862                         MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
 863                         MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
 864                         MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
 865                 >;
 866         };
 867
 868         pinctrl_spi1: spi1grp {
 869                 fsl,pins = <
 870                         MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK    0x82
 871                         MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI    0x82
 872                         MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO    0x82
 873                         MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9       0x40
 874                         MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3        0x140 /* CAN_IRQ# */
 875                 >;
 876         };
 877
 878         pinctrl_spi2: spi2grp {
 879                 fsl,pins = <
 880                         MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0x82
 881                         MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0x82
 882                         MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0x82
 883                         MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0x40 /* SS0 */
 884                 >;
 885         };
 886
 887         pinctrl_uart1: uart1grp {
 888                 fsl,pins = <
 889                         MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 890                         MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 891                         MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10       0x140 /* RTS */
 892                         MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24       0x140 /* CTS */
 893                 >;
 894         };
 895
 896         pinctrl_uart1_gpio: uart1gpiogrp {
 897                 fsl,pins = <
 898                         MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26       0x40000110 /* HALF */
 899                         MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25        0x40000110 /* TERM */
 900                         MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23       0x40000110 /* RS485 */
 901                 >;
 902         };
 903
 904         pinctrl_uart2: uart2grp {
 905                 fsl,pins = <
 906                         MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
 907                         MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
 908                 >;
 909         };
 910
 911         pinctrl_uart3_gpio: uart3_gpiogrp {
 912                 fsl,pins = <
 913                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12        0x41 /* BT_EN# */
 914                 >;
 915         };
 916
 917         pinctrl_uart3: uart3grp {
 918                 fsl,pins = <
 919                         MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX     0x140
 920                         MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX     0x140
 921                         MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0          0x140 /* CTS */
 922                         MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1          0x140 /* RTS */
 923                 >;
 924         };
 925
 926         pinctrl_uart4: uart4grp {
 927                 fsl,pins = <
 928                         MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX     0x140
 929                         MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX     0x140
 930                         MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1         0x140 /* CTS */
 931                         MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2        0x140 /* RTS */
 932                         MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3        0x140 /* DTR */
 933                         MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4        0x140 /* DSR */
 934                         MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6        0x140 /* DCD */
 935                         MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7        0x140 /* RI */
 936                         MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0        0x140 /* GNSS_PPS */
 937                         MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6       0x141 /* GNSS_GASP */
 938                 >;
 939         };
 940
 941         pinctrl_usdhc2: usdhc2grp {
 942                 fsl,pins = <
 943                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 944                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 945                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 946                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 947                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 948                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 949                 >;
 950         };
 951
 952         pinctrl_usdhc3: usdhc3grp {
 953                 fsl,pins = <
 954                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x190
 955                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d0
 956                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d0
 957                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d0
 958                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d0
 959                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d0
 960                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d0
 961                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d0
 962                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d0
 963                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d0
 964                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x190
 965                 >;
 966         };
 967
 968         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 969                 fsl,pins = <
 970                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x194
 971                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d4
 972                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d4
 973                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d4
 974                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d4
 975                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d4
 976                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d4
 977                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d4
 978                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d4
 979                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d4
 980                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x194
 981                 >;
 982         };
 983
 984         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 985                 fsl,pins = <
 986                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x196
 987                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d6
 988                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d6
 989                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d6
 990                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d6
 991                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d6
 992                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d6
 993                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d6
 994                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d6
 995                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d6
 996                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x196
 997                 >;
 998         };
 999
1000         pinctrl_wdog: wdoggrp {
1001                 fsl,pins = <
1002                         MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0xc6
1003                 >;
1004         };
1005 };