1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2020 Gateworks Corporation
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
13 #include "imx8mm.dtsi"
16 model = "Gateworks Venice GW7901 i.MX8MM board";
17 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
34 device_type = "memory";
35 reg = <0x0 0x40000000 0 0x80000000>;
39 compatible = "gpio-keys";
43 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
50 interrupt-parent = <&gsc>;
57 interrupt-parent = <&gsc>;
64 interrupt-parent = <&gsc>;
71 interrupt-parent = <&gsc>;
76 label = "switch_hold";
78 interrupt-parent = <&gsc>;
84 compatible = "gpio-leds";
87 function = LED_FUNCTION_STATUS;
88 color = <LED_COLOR_ID_RED>;
90 gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>;
91 default-state = "off";
95 function = LED_FUNCTION_STATUS;
96 color = <LED_COLOR_ID_GREEN>;
98 gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>;
99 default-state = "off";
103 function = LED_FUNCTION_STATUS;
104 color = <LED_COLOR_ID_RED>;
106 gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>;
107 default-state = "off";
111 function = LED_FUNCTION_STATUS;
112 color = <LED_COLOR_ID_GREEN>;
114 gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>;
115 default-state = "off";
119 function = LED_FUNCTION_STATUS;
120 color = <LED_COLOR_ID_RED>;
122 gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>;
123 default-state = "off";
127 function = LED_FUNCTION_STATUS;
128 color = <LED_COLOR_ID_GREEN>;
130 gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>;
131 default-state = "off";
135 function = LED_FUNCTION_STATUS;
136 color = <LED_COLOR_ID_RED>;
138 gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>;
139 default-state = "off";
143 function = LED_FUNCTION_STATUS;
144 color = <LED_COLOR_ID_GREEN>;
146 gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
147 default-state = "off";
151 function = LED_FUNCTION_STATUS;
152 color = <LED_COLOR_ID_RED>;
154 gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>;
155 default-state = "off";
159 function = LED_FUNCTION_STATUS;
160 color = <LED_COLOR_ID_GREEN>;
162 gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>;
163 default-state = "off";
167 function = LED_FUNCTION_STATUS;
168 color = <LED_COLOR_ID_RED>;
170 gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>;
171 default-state = "off";
175 function = LED_FUNCTION_STATUS;
176 color = <LED_COLOR_ID_GREEN>;
178 gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>;
179 default-state = "off";
183 pcie0_refclk: pcie0-refclk {
184 compatible = "fixed-clock";
186 clock-frequency = <100000000>;
189 reg_3p3v: regulator-3p3v {
190 compatible = "regulator-fixed";
191 regulator-name = "3P3V";
192 regulator-min-microvolt = <3300000>;
193 regulator-max-microvolt = <3300000>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_reg_ioexp>;
199 compatible = "regulator-fixed";
200 regulator-name = "ioexp";
201 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
203 startup-delay-us = <100>;
204 regulator-min-microvolt = <3300000>;
205 regulator-max-microvolt = <3300000>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_reg_isouart>;
212 compatible = "regulator-fixed";
213 regulator-name = "iso_uart";
214 gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
215 startup-delay-us = <100>;
216 regulator-min-microvolt = <3300000>;
217 regulator-max-microvolt = <3300000>;
221 reg_usb2_vbus: regulator-usb2 {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_reg_usb2>;
224 compatible = "regulator-fixed";
225 regulator-name = "usb_usb2_vbus";
226 gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
228 regulator-min-microvolt = <5000000>;
229 regulator-max-microvolt = <5000000>;
232 reg_wifi: regulator-wifi {
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_reg_wl>;
235 compatible = "regulator-fixed";
236 regulator-name = "wifi";
237 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
239 startup-delay-us = <100>;
240 regulator-min-microvolt = <3300000>;
241 regulator-max-microvolt = <3300000>;
246 operating-points-v2 = <&ddrc_opp_table>;
248 ddrc_opp_table: opp-table {
249 compatible = "operating-points-v2";
252 opp-hz = /bits/ 64 <25000000>;
256 opp-hz = /bits/ 64 <100000000>;
260 opp-hz = /bits/ 64 <750000000>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_spi1>;
272 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
276 compatible = "jedec,spi-nor";
278 spi-max-frequency = <40000000>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_fec1>;
286 phy-mode = "rgmii-id";
287 local-mac-address = [00 00 00 00 00 00];
297 gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#",
298 "", "uart1_rs232#", "dig1_in", "dig1_out",
299 "", "", "", "", "", "", "", "",
300 "", "", "", "", "", "", "", "",
301 "", "", "", "", "", "", "", "";
305 gpio-line-names = "", "", "", "",
306 "", "", "uart3_rs232#", "uart3_rs422#",
307 "uart3_rs485#", "", "", "", "", "", "", "",
308 "", "", "", "", "", "", "", "",
309 "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";
313 gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "",
314 "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "",
315 "", "", "", "", "", "", "", "",
316 "", "", "", "", "", "", "", "";
328 clock-frequency = <100000>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_i2c1>;
334 compatible = "gw,gsc";
336 pinctrl-0 = <&pinctrl_gsc>;
337 interrupt-parent = <&gpio4>;
338 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
339 interrupt-controller;
340 #interrupt-cells = <1>;
343 compatible = "gw,gsc-adc";
344 #address-cells = <1>;
363 gw,voltage-divider-ohms = <22100 1000>;
370 gw,voltage-divider-ohms = <22100 1000>;
377 gw,voltage-divider-ohms = <22100 1000>;
384 gw,voltage-divider-ohms = <10000 10000>;
391 gw,voltage-divider-ohms = <10000 10000>;
434 gw,voltage-divider-ohms = <10000 10000>;
440 compatible = "nxp,pca9555";
444 interrupt-parent = <&gsc>;
449 compatible = "atmel,24c02";
455 compatible = "atmel,24c02";
461 compatible = "atmel,24c02";
467 compatible = "atmel,24c02";
473 compatible = "dallas,ds1672";
479 clock-frequency = <400000>;
480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_i2c2>;
485 compatible = "rohm,bd71847";
487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_pmic>;
489 interrupt-parent = <&gpio3>;
490 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
491 rohm,reset-snvs-powered;
493 clocks = <&osc_32k 0>;
494 clock-output-names = "clk-32k-out";
497 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
499 regulator-name = "buck1";
500 regulator-min-microvolt = <700000>;
501 regulator-max-microvolt = <1300000>;
504 regulator-ramp-delay = <1250>;
507 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
509 regulator-name = "buck2";
510 regulator-min-microvolt = <700000>;
511 regulator-max-microvolt = <1300000>;
514 regulator-ramp-delay = <1250>;
515 rohm,dvs-run-voltage = <1000000>;
516 rohm,dvs-idle-voltage = <900000>;
519 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
521 regulator-name = "buck3";
522 regulator-min-microvolt = <700000>;
523 regulator-max-microvolt = <1350000>;
530 regulator-name = "buck4";
531 regulator-min-microvolt = <3000000>;
532 regulator-max-microvolt = <3300000>;
539 regulator-name = "buck5";
540 regulator-min-microvolt = <1605000>;
541 regulator-max-microvolt = <1995000>;
548 regulator-name = "buck6";
549 regulator-min-microvolt = <800000>;
550 regulator-max-microvolt = <1400000>;
557 regulator-name = "ldo1";
558 regulator-min-microvolt = <1600000>;
559 regulator-max-microvolt = <1900000>;
566 regulator-name = "ldo2";
567 regulator-min-microvolt = <800000>;
568 regulator-max-microvolt = <900000>;
575 regulator-name = "ldo3";
576 regulator-min-microvolt = <1800000>;
577 regulator-max-microvolt = <3300000>;
583 regulator-name = "ldo4";
584 regulator-min-microvolt = <900000>;
585 regulator-max-microvolt = <1800000>;
591 regulator-name = "ldo6";
592 regulator-min-microvolt = <900000>;
593 regulator-max-microvolt = <1800000>;
602 clock-frequency = <400000>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&pinctrl_i2c3>;
608 compatible = "nxp,pca9555";
615 compatible = "microchip,ksz9897";
617 pinctrl-0 = <&pinctrl_ksz>;
618 interrupt-parent = <&gpio4>;
619 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
620 phy-mode = "rgmii-id";
623 #address-cells = <1>;
629 phy-mode = "internal";
630 local-mac-address = [00 00 00 00 00 00];
636 phy-mode = "internal";
637 local-mac-address = [00 00 00 00 00 00];
643 phy-mode = "internal";
644 local-mac-address = [00 00 00 00 00 00];
650 phy-mode = "internal";
651 local-mac-address = [00 00 00 00 00 00];
658 phy-mode = "rgmii-id";
669 compatible = "atmel,atecc508a";
675 clock-frequency = <400000>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&pinctrl_i2c4>;
682 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
683 fsl,clkreq-unsupported;
684 clocks = <&pcie0_refclk>;
690 pinctrl-names = "default";
691 pinctrl-0 = <&pinctrl_pcie0>;
692 reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
693 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
695 clock-names = "pcie", "pcie_aux", "pcie_bus";
696 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
697 <&clk IMX8MM_CLK_PCIE1_CTRL>;
698 assigned-clock-rates = <10000000>, <250000000>;
699 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
700 <&clk IMX8MM_SYS_PLL2_250M>;
717 pinctrl-names = "default";
718 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
719 rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
720 cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
721 dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
722 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
723 dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
729 pinctrl-names = "default";
730 pinctrl-0 = <&pinctrl_uart2>;
735 pinctrl-names = "default";
736 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
737 cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
738 rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
743 pinctrl-names = "default";
744 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
745 cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
746 rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
752 disable-over-current;
758 vbus-supply = <®_usb2_vbus>;
759 over-current-active-low;
765 pinctrl-names = "default";
766 pinctrl-0 = <&pinctrl_usdhc1>;
769 vmmc-supply = <®_wifi>;
775 pinctrl-names = "default", "state_100mhz", "state_200mhz";
776 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
777 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
778 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
779 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
781 vmmc-supply = <®_3p3v>;
787 pinctrl-names = "default", "state_100mhz", "state_200mhz";
788 pinctrl-0 = <&pinctrl_usdhc3>;
789 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
790 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
797 pinctrl-names = "default";
798 pinctrl-0 = <&pinctrl_wdog>;
799 fsl,ext-reset-output;
804 pinctrl-names = "default";
805 pinctrl-0 = <&pinctrl_hog>;
807 pinctrl_hog: hoggrp {
809 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */
810 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */
811 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */
812 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */
813 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */
814 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */
815 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */
819 pinctrl_fec1: fec1grp {
821 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
822 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
823 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
824 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
825 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
826 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
827 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
828 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
829 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
830 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
831 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
832 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
833 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
834 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
835 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */
836 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */
840 pinctrl_gsc: gscgrp {
842 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159
846 pinctrl_i2c1: i2c1grp {
848 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
849 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
853 pinctrl_i2c2: i2c2grp {
855 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
856 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
860 pinctrl_i2c3: i2c3grp {
862 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
863 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
867 pinctrl_i2c4: i2c4grp {
869 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
870 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
874 pinctrl_ksz: kszgrp {
876 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41
877 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */
881 pinctrl_pcie0: pciegrp {
883 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */
884 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41
888 pinctrl_pmic: pmicgrp {
890 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
894 pinctrl_reg_isouart: regisouartgrp {
896 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041
900 pinctrl_reg_ioexp: regioexpgrp {
902 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041
906 pinctrl_reg_wl: regwlgrp {
908 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041
912 pinctrl_reg_usb2: regusb1grp {
914 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41
915 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140
916 MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140
920 pinctrl_spi1: spi1grp {
922 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
923 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
924 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
925 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
929 pinctrl_uart1: uart1grp {
931 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
932 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
933 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
934 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140
935 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140
936 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140
937 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140
941 pinctrl_uart1_gpio: uart1gpiogrp {
943 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */
944 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */
945 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */
949 pinctrl_uart2: uart2grp {
951 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
952 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
956 pinctrl_uart3: uart3grp {
958 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
959 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
960 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140
961 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140
965 pinctrl_uart3_gpio: uart3gpiogrp {
967 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */
968 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */
969 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */
973 pinctrl_uart4: uart4grp {
975 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
976 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
977 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140
978 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140
982 pinctrl_uart4_gpio: uart4gpiogrp {
985 MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */
986 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */
987 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */
991 pinctrl_usdhc1: usdhc1grp {
993 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
994 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
995 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
996 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
997 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
998 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
1002 pinctrl_usdhc2: usdhc2grp {
1004 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
1005 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
1006 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
1007 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
1008 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
1009 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
1013 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1015 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
1016 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
1017 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
1018 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
1019 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
1020 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
1024 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1026 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
1027 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
1028 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
1029 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
1030 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
1031 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
1035 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
1037 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
1038 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
1042 pinctrl_usdhc3: usdhc3grp {
1044 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
1045 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
1046 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
1047 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
1048 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
1049 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
1050 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
1051 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
1052 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
1053 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
1054 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
1058 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1060 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
1061 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
1062 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
1063 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
1064 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
1065 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
1066 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
1067 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
1068 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
1069 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
1070 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
1074 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1076 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
1077 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
1078 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
1079 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
1080 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
1081 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
1082 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
1083 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
1084 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
1085 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
1086 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
1090 pinctrl_wdog: wdoggrp {
1092 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6