arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2020 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/leds/common.h>
   8 #include <dt-bindings/phy/phy-imx8-pcie.h>
   9
  10 / {
  11         aliases {
  12                 ethernet1 = &eth1;
  13                 usb0 = &usbotg1;
  14                 usb1 = &usbotg2;
  15         };
  16
  17         led-controller {
  18                 compatible = "gpio-leds";
  19                 pinctrl-names = "default";
  20                 pinctrl-0 = <&pinctrl_gpio_leds>;
  21
  22                 led-0 {
  23                         function = LED_FUNCTION_STATUS;
  24                         color = <LED_COLOR_ID_GREEN>;
  25                         gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
  26                         default-state = "on";
  27                         linux,default-trigger = "heartbeat";
  28                 };
  29
  30                 led-1 {
  31                         function = LED_FUNCTION_STATUS;
  32                         color = <LED_COLOR_ID_RED>;
  33                         gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
  34                         default-state = "off";
  35                 };
  36         };
  37
  38         pcie0_refclk: pcie0-refclk {
  39                 compatible = "fixed-clock";
  40                 #clock-cells = <0>;
  41                 clock-frequency = <100000000>;
  42         };
  43
  44         pps {
  45                 compatible = "pps-gpio";
  46                 pinctrl-names = "default";
  47                 pinctrl-0 = <&pinctrl_pps>;
  48                 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
  49                 status = "okay";
  50         };
  51
  52         reg_1p8v: regulator-1p8v {
  53                 compatible = "regulator-fixed";
  54                 regulator-name = "1P8V";
  55                 regulator-min-microvolt = <1800000>;
  56                 regulator-max-microvolt = <1800000>;
  57                 regulator-always-on;
  58         };
  59
  60         reg_3p3v: regulator-3p3v {
  61                 compatible = "regulator-fixed";
  62                 regulator-name = "3P3V";
  63                 regulator-min-microvolt = <3300000>;
  64                 regulator-max-microvolt = <3300000>;
  65                 regulator-always-on;
  66         };
  67
  68         reg_usb_otg1_vbus: regulator-usb-otg1 {
  69                 pinctrl-names = "default";
  70                 pinctrl-0 = <&pinctrl_reg_usb1_en>;
  71                 compatible = "regulator-fixed";
  72                 regulator-name = "usb_otg1_vbus";
  73                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  74                 enable-active-high;
  75                 regulator-min-microvolt = <5000000>;
  76                 regulator-max-microvolt = <5000000>;
  77         };
  78
  79         reg_usb_otg2_vbus: regulator-usb-otg2 {
  80                 pinctrl-names = "default";
  81                 pinctrl-0 = <&pinctrl_reg_usb2_en>;
  82                 compatible = "regulator-fixed";
  83                 regulator-name = "usb_otg2_vbus";
  84                 gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
  85                 enable-active-high;
  86                 regulator-min-microvolt = <5000000>;
  87                 regulator-max-microvolt = <5000000>;
  88         };
  89
  90         reg_wifi_en: regulator-wifi-en {
  91                 pinctrl-names = "default";
  92                 pinctrl-0 = <&pinctrl_reg_wl>;
  93                 compatible = "regulator-fixed";
  94                 regulator-name = "wl";
  95                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  96                 startup-delay-us = <100>;
  97                 enable-active-high;
  98                 regulator-min-microvolt = <3300000>;
  99                 regulator-max-microvolt = <3300000>;
 100         };
 101 };
 102
 103 /* off-board header */
 104 &ecspi2 {
 105         pinctrl-names = "default";
 106         pinctrl-0 = <&pinctrl_spi2>;
 107         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
 108                    <&gpio1 10 GPIO_ACTIVE_LOW>;
 109         status = "okay";
 110
 111         tpm@1 {
 112                 compatible = "tcg,tpm_tis-spi";
 113                 reg = <0x1>;
 114                 spi-max-frequency = <36000000>;
 115         };
 116 };
 117
 118 &gpio1 {
 119         gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
 120                 "", "", "pci_usb_sel", "dio0",
 121                 "", "dio1", "", "", "", "", "", "",
 122                 "", "", "", "", "", "", "", "",
 123                 "", "", "", "", "", "", "", "";
 124 };
 125
 126 &gpio4 {
 127         gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
 128                 "mipi_gpio1", "", "", "pci_wdis#",
 129                 "", "", "", "", "", "", "", "",
 130                 "", "", "", "", "", "", "", "",
 131                 "", "", "", "", "", "", "", "";
 132 };
 133
 134 &i2c2 {
 135         clock-frequency = <400000>;
 136         pinctrl-names = "default";
 137         pinctrl-0 = <&pinctrl_i2c2>;
 138         status = "okay";
 139
 140         accelerometer@19 {
 141                 pinctrl-names = "default";
 142                 pinctrl-0 = <&pinctrl_accel>;
 143                 compatible = "st,lis2de12";
 144                 reg = <0x19>;
 145                 st,drdy-int-pin = <1>;
 146                 interrupt-parent = <&gpio4>;
 147                 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
 148         };
 149 };
 150
 151 /* off-board header */
 152 &i2c3 {
 153         clock-frequency = <400000>;
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&pinctrl_i2c3>;
 156         status = "okay";
 157 };
 158
 159 &pcie_phy {
 160         fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
 161         fsl,clkreq-unsupported;
 162         clocks = <&pcie0_refclk>;
 163         clock-names = "ref";
 164         status = "okay";
 165 };
 166
 167 &pcie0 {
 168         pinctrl-names = "default";
 169         pinctrl-0 = <&pinctrl_pcie0>;
 170         reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
 171         clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
 172                  <&clk IMX8MM_CLK_PCIE1_AUX>;
 173         assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 174                           <&clk IMX8MM_CLK_PCIE1_CTRL>;
 175         assigned-clock-rates = <10000000>, <250000000>;
 176         assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 177                                  <&clk IMX8MM_SYS_PLL2_250M>;
 178         status = "okay";
 179
 180         pcie@0,0 {
 181                 reg = <0x0000 0 0 0 0>;
 182                 #address-cells = <1>;
 183                 #size-cells = <0>;
 184
 185                 pcie@1,0 {
 186                         reg = <0x0000 0 0 0 0>;
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189
 190                         pcie@2,4 {
 191                                 reg = <0x2000 0 0 0 0>;
 192                                 #address-cells = <1>;
 193                                 #size-cells = <0>;
 194
 195                                 eth1: pcie@6,0 {
 196                                         reg = <0x0000 0 0 0 0>;
 197                                         #address-cells = <1>;
 198                                         #size-cells = <0>;
 199
 200                                         local-mac-address = [00 00 00 00 00 00];
 201                                 };
 202                         };
 203                 };
 204         };
 205 };
 206
 207 /* off-board header */
 208 &sai3 {
 209         pinctrl-names = "default";
 210         pinctrl-0 = <&pinctrl_sai3>;
 211         assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
 212         assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
 213         assigned-clock-rates = <24576000>;
 214         status = "okay";
 215 };
 216
 217 /* GPS */
 218 &uart1 {
 219         pinctrl-names = "default";
 220         pinctrl-0 = <&pinctrl_uart1>;
 221         status = "okay";
 222 };
 223
 224 /* bluetooth HCI */
 225 &uart3 {
 226         pinctrl-names = "default";
 227         pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
 228         cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
 229         rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 230         status = "okay";
 231
 232         bluetooth {
 233                 compatible = "brcm,bcm4330-bt";
 234                 shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
 235         };
 236 };
 237
 238 /* RS232 */
 239 &uart4 {
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_uart4>;
 242         status = "okay";
 243 };
 244
 245 &usbotg1 {
 246         dr_mode = "otg";
 247         over-current-active-low;
 248         vbus-supply = <&reg_usb_otg1_vbus>;
 249         status = "okay";
 250 };
 251
 252 &usbotg2 {
 253         dr_mode = "host";
 254         disable-over-current;
 255         vbus-supply = <&reg_usb_otg2_vbus>;
 256         status = "okay";
 257 };
 258
 259 /* SDIO WiFi */
 260 &usdhc1 {
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&pinctrl_usdhc1>;
 263         bus-width = <4>;
 264         non-removable;
 265         vmmc-supply = <&reg_wifi_en>;
 266         status = "okay";
 267 };
 268
 269 /* microSD */
 270 &usdhc2 {
 271         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 272         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 273         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 274         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 275         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 276         bus-width = <4>;
 277         vmmc-supply = <&reg_3p3v>;
 278         status = "okay";
 279 };
 280
 281 &iomuxc {
 282         pinctrl-names = "default";
 283         pinctrl-0 = <&pinctrl_hog>;
 284
 285         pinctrl_hog: hoggrp {
 286                 fsl,pins = <
 287                         MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3         0x40000041 /* PLUG_TEST */
 288                         MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6       0x40000041 /* PCI_USBSEL */
 289                         MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7        0x40000041 /* PCIE_WDIS# */
 290                         MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7       0x40000041 /* DIO0 */
 291                         MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9       0x40000041 /* DIO1 */
 292                         MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0       0x40000104 /* RS485_TERM */
 293                         MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0        0x40000104 /* RS485 */
 294                         MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2        0x40000104 /* RS485_HALF */
 295                 >;
 296         };
 297
 298         pinctrl_accel: accelgrp {
 299                 fsl,pins = <
 300                         MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5        0x159
 301                 >;
 302         };
 303
 304         pinctrl_bten: btengrp {
 305                 fsl,pins = <
 306                         MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x41
 307                 >;
 308         };
 309
 310         pinctrl_gpio_leds: gpioledgrp {
 311                 fsl,pins = <
 312                         MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5    0x19
 313                         MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4         0x19
 314                 >;
 315         };
 316
 317         pinctrl_i2c3: i2c3grp {
 318                 fsl,pins = <
 319                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 320                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 321                 >;
 322         };
 323
 324         pinctrl_pcie0: pcie0grp {
 325                 fsl,pins = <
 326                         MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6        0x41
 327                 >;
 328         };
 329
 330         pinctrl_pps: ppsgrp {
 331                 fsl,pins = <
 332                         MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x41
 333                 >;
 334         };
 335
 336         pinctrl_reg_wl: regwlgrp {
 337                 fsl,pins = <
 338                         MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x41
 339                 >;
 340         };
 341
 342         pinctrl_reg_usb1_en: regusb1grp {
 343                 fsl,pins = <
 344                         MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x41
 345                         MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC     0x41
 346                 >;
 347         };
 348
 349         pinctrl_reg_usb2_en: regusb2grp {
 350                 fsl,pins = <
 351                         MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8       0x41
 352                 >;
 353         };
 354
 355         pinctrl_sai3: sai3grp {
 356                 fsl,pins = <
 357                         MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
 358                         MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
 359                         MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
 360                         MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
 361                         MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0     0xd6
 362                 >;
 363         };
 364
 365         pinctrl_spi2: spi2grp {
 366                 fsl,pins = <
 367                         MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
 368                         MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0xd6
 369                         MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0xd6
 370                         MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0xd6
 371                         MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10      0xd6
 372                 >;
 373         };
 374
 375         pinctrl_uart1: uart1grp {
 376                 fsl,pins = <
 377                         MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 378                         MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 379                 >;
 380         };
 381
 382         pinctrl_uart3: uart3grp {
 383                 fsl,pins = <
 384                         MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX     0x140
 385                         MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX     0x140
 386                         MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8      0x140
 387                         MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9       0x140
 388                 >;
 389         };
 390
 391         pinctrl_uart4: uart4grp {
 392                 fsl,pins = <
 393                         MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX     0x140
 394                         MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX     0x140
 395                 >;
 396         };
 397
 398         pinctrl_usdhc1: usdhc1grp {
 399                 fsl,pins = <
 400                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
 401                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
 402                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
 403                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
 404                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
 405                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
 406                 >;
 407         };
 408
 409         pinctrl_usdhc2: usdhc2grp {
 410                 fsl,pins = <
 411                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 412                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 413                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 414                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 415                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 416                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 417                 >;
 418         };
 419
 420         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 421                 fsl,pins = <
 422                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 423                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 424                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 425                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 426                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 427                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 428                 >;
 429         };
 430
 431         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 432                 fsl,pins = <
 433                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 434                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 435                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 436                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 437                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 438                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 439                 >;
 440         };
 441
 442         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 443                 fsl,pins = <
 444                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12        0x1c4
 445                         MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
 446                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 447                 >;
 448         };
 449 };