1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2020 Gateworks Corporation
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
18 compatible = "gpio-leds";
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio_leds>;
23 function = LED_FUNCTION_STATUS;
24 color = <LED_COLOR_ID_GREEN>;
25 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
27 linux,default-trigger = "heartbeat";
31 function = LED_FUNCTION_STATUS;
32 color = <LED_COLOR_ID_RED>;
33 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
34 default-state = "off";
38 pcie0_refclk: pcie0-refclk {
39 compatible = "fixed-clock";
41 clock-frequency = <100000000>;
45 compatible = "pps-gpio";
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_pps>;
48 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
52 reg_3p3v: regulator-3p3v {
53 compatible = "regulator-fixed";
54 regulator-name = "3P3V";
55 regulator-min-microvolt = <3300000>;
56 regulator-max-microvolt = <3300000>;
60 reg_usb_otg1_vbus: regulator-usb-otg1 {
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_reg_usb1_en>;
63 compatible = "regulator-fixed";
64 regulator-name = "usb_otg1_vbus";
65 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>;
71 reg_usb_otg2_vbus: regulator-usb-otg2 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_reg_usb2_en>;
74 compatible = "regulator-fixed";
75 regulator-name = "usb_otg2_vbus";
76 gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
78 regulator-min-microvolt = <5000000>;
79 regulator-max-microvolt = <5000000>;
83 /* off-board header */
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_spi2>;
87 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
92 gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
93 "", "", "pci_usb_sel", "dio0",
94 "", "dio1", "", "", "", "", "", "",
95 "", "", "", "", "", "", "", "",
96 "", "", "", "", "", "", "", "";
100 gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
101 "mipi_gpio1", "", "", "pci_wdis#",
102 "", "", "", "", "", "", "", "",
103 "", "", "", "", "", "", "", "",
104 "", "", "", "", "", "", "", "";
108 clock-frequency = <400000>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_i2c2>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_accel>;
116 compatible = "st,lis2de12";
118 st,drdy-int-pin = <1>;
119 interrupt-parent = <&gpio4>;
120 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
124 /* off-board header */
126 clock-frequency = <400000>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_i2c3>;
133 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
134 fsl,clkreq-unsupported;
135 clocks = <&pcie0_refclk>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_pcie0>;
143 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
144 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
145 <&clk IMX8MM_CLK_PCIE1_AUX>;
146 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
147 <&clk IMX8MM_CLK_PCIE1_CTRL>;
148 assigned-clock-rates = <10000000>, <250000000>;
149 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
150 <&clk IMX8MM_SYS_PLL2_250M>;
154 reg = <0x0000 0 0 0 0>;
155 #address-cells = <1>;
159 reg = <0x0000 0 0 0 0>;
160 #address-cells = <1>;
164 reg = <0x1800 0 0 0 0>;
165 #address-cells = <1>;
169 reg = <0x0000 0 0 0 0>;
170 #address-cells = <1>;
173 local-mac-address = [00 00 00 00 00 00];
180 /* off-board header */
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_sai3>;
184 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
185 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
186 assigned-clock-rates = <24576000>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_uart1>;
197 /* off-board header */
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_uart3>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_uart4>;
213 over-current-active-low;
214 vbus-supply = <®_usb_otg1_vbus>;
220 disable-over-current;
221 vbus-supply = <®_usb_otg2_vbus>;
227 pinctrl-names = "default", "state_100mhz", "state_200mhz";
228 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
229 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
230 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
231 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
233 vmmc-supply = <®_3p3v>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_hog>;
241 pinctrl_hog: hoggrp {
243 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
244 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
245 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
246 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
247 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
248 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
249 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
250 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
254 pinctrl_accel: accelgrp {
256 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
260 pinctrl_gpio_leds: gpioledgrp {
262 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
263 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
267 pinctrl_i2c3: i2c3grp {
269 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
270 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
274 pinctrl_pcie0: pcie0grp {
276 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
280 pinctrl_pps: ppsgrp {
282 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
286 pinctrl_reg_usb1_en: regusb1grp {
288 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
289 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
293 pinctrl_reg_usb2_en: regusb2grp {
295 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
299 pinctrl_sai3: sai3grp {
301 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
302 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
303 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
304 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
305 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
309 pinctrl_spi2: spi2grp {
311 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
312 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
313 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
314 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
318 pinctrl_uart1: uart1grp {
320 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
321 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
325 pinctrl_uart3: uart3grp {
327 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
328 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
332 pinctrl_uart4: uart4grp {
334 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
335 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
339 pinctrl_usdhc1: usdhc1grp {
341 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
342 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
343 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
344 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
345 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
346 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
350 pinctrl_usdhc2: usdhc2grp {
352 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
353 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
354 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
355 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
356 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
357 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
361 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
363 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
364 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
365 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
366 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
367 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
368 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
372 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
374 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
375 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
376 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
377 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
378 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
379 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
383 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
385 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
386 MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
387 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0