arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2020 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/leds/common.h>
   8 #include <dt-bindings/phy/phy-imx8-pcie.h>
   9
  10 / {
  11         aliases {
  12                 ethernet1 = &eth1;
  13                 usb0 = &usbotg1;
  14                 usb1 = &usbotg2;
  15         };
  16
  17         led-controller {
  18                 compatible = "gpio-leds";
  19                 pinctrl-names = "default";
  20                 pinctrl-0 = <&pinctrl_gpio_leds>;
  21
  22                 led-0 {
  23                         function = LED_FUNCTION_STATUS;
  24                         color = <LED_COLOR_ID_GREEN>;
  25                         gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
  26                         default-state = "on";
  27                         linux,default-trigger = "heartbeat";
  28                 };
  29
  30                 led-1 {
  31                         function = LED_FUNCTION_STATUS;
  32                         color = <LED_COLOR_ID_RED>;
  33                         gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
  34                         default-state = "off";
  35                 };
  36         };
  37
  38         pcie0_refclk: pcie0-refclk {
  39                 compatible = "fixed-clock";
  40                 #clock-cells = <0>;
  41                 clock-frequency = <100000000>;
  42         };
  43
  44         pps {
  45                 compatible = "pps-gpio";
  46                 pinctrl-names = "default";
  47                 pinctrl-0 = <&pinctrl_pps>;
  48                 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
  49                 status = "okay";
  50         };
  51
  52         reg_3p3v: regulator-3p3v {
  53                 compatible = "regulator-fixed";
  54                 regulator-name = "3P3V";
  55                 regulator-min-microvolt = <3300000>;
  56                 regulator-max-microvolt = <3300000>;
  57                 regulator-always-on;
  58         };
  59
  60         reg_usb_otg1_vbus: regulator-usb-otg1 {
  61                 pinctrl-names = "default";
  62                 pinctrl-0 = <&pinctrl_reg_usb1_en>;
  63                 compatible = "regulator-fixed";
  64                 regulator-name = "usb_otg1_vbus";
  65                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  66                 enable-active-high;
  67                 regulator-min-microvolt = <5000000>;
  68                 regulator-max-microvolt = <5000000>;
  69         };
  70
  71         reg_usb_otg2_vbus: regulator-usb-otg2 {
  72                 pinctrl-names = "default";
  73                 pinctrl-0 = <&pinctrl_reg_usb2_en>;
  74                 compatible = "regulator-fixed";
  75                 regulator-name = "usb_otg2_vbus";
  76                 gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
  77                 enable-active-high;
  78                 regulator-min-microvolt = <5000000>;
  79                 regulator-max-microvolt = <5000000>;
  80         };
  81 };
  82
  83 /* off-board header */
  84 &ecspi2 {
  85         pinctrl-names = "default";
  86         pinctrl-0 = <&pinctrl_spi2>;
  87         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
  88         status = "okay";
  89 };
  90
  91 &gpio1 {
  92         gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
  93                 "", "", "pci_usb_sel", "dio0",
  94                 "", "dio1", "", "", "", "", "", "",
  95                 "", "", "", "", "", "", "", "",
  96                 "", "", "", "", "", "", "", "";
  97 };
  98
  99 &gpio4 {
 100         gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
 101                 "mipi_gpio1", "", "", "pci_wdis#",
 102                 "", "", "", "", "", "", "", "",
 103                 "", "", "", "", "", "", "", "",
 104                 "", "", "", "", "", "", "", "";
 105 };
 106
 107 &i2c2 {
 108         clock-frequency = <400000>;
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&pinctrl_i2c2>;
 111         status = "okay";
 112
 113         accelerometer@19 {
 114                 pinctrl-names = "default";
 115                 pinctrl-0 = <&pinctrl_accel>;
 116                 compatible = "st,lis2de12";
 117                 reg = <0x19>;
 118                 st,drdy-int-pin = <1>;
 119                 interrupt-parent = <&gpio4>;
 120                 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
 121         };
 122 };
 123
 124 /* off-board header */
 125 &i2c3 {
 126         clock-frequency = <400000>;
 127         pinctrl-names = "default";
 128         pinctrl-0 = <&pinctrl_i2c3>;
 129         status = "okay";
 130 };
 131
 132 &pcie_phy {
 133         fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
 134         fsl,clkreq-unsupported;
 135         clocks = <&pcie0_refclk>;
 136         clock-names = "ref";
 137         status = "okay";
 138 };
 139
 140 &pcie0 {
 141         pinctrl-names = "default";
 142         pinctrl-0 = <&pinctrl_pcie0>;
 143         reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
 144         clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
 145                  <&clk IMX8MM_CLK_PCIE1_AUX>;
 146         assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 147                           <&clk IMX8MM_CLK_PCIE1_CTRL>;
 148         assigned-clock-rates = <10000000>, <250000000>;
 149         assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 150                                  <&clk IMX8MM_SYS_PLL2_250M>;
 151         status = "okay";
 152
 153         pcie@0,0 {
 154                 reg = <0x0000 0 0 0 0>;
 155                 #address-cells = <1>;
 156                 #size-cells = <0>;
 157
 158                 pcie@1,0 {
 159                         reg = <0x0000 0 0 0 0>;
 160                         #address-cells = <1>;
 161                         #size-cells = <0>;
 162
 163                         pcie@2,3 {
 164                                 reg = <0x1800 0 0 0 0>;
 165                                 #address-cells = <1>;
 166                                 #size-cells = <0>;
 167
 168                                 eth1: pcie@5,0 {
 169                                         reg = <0x0000 0 0 0 0>;
 170                                         #address-cells = <1>;
 171                                         #size-cells = <0>;
 172
 173                                         local-mac-address = [00 00 00 00 00 00];
 174                                 };
 175                         };
 176                 };
 177         };
 178 };
 179
 180 /* off-board header */
 181 &sai3 {
 182         pinctrl-names = "default";
 183         pinctrl-0 = <&pinctrl_sai3>;
 184         assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
 185         assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
 186         assigned-clock-rates = <24576000>;
 187         status = "okay";
 188 };
 189
 190 /* GPS */
 191 &uart1 {
 192         pinctrl-names = "default";
 193         pinctrl-0 = <&pinctrl_uart1>;
 194         status = "okay";
 195 };
 196
 197 /* off-board header */
 198 &uart3 {
 199         pinctrl-names = "default";
 200         pinctrl-0 = <&pinctrl_uart3>;
 201         status = "okay";
 202 };
 203
 204 /* RS232 */
 205 &uart4 {
 206         pinctrl-names = "default";
 207         pinctrl-0 = <&pinctrl_uart4>;
 208         status = "okay";
 209 };
 210
 211 &usbotg1 {
 212         dr_mode = "otg";
 213         over-current-active-low;
 214         vbus-supply = <&reg_usb_otg1_vbus>;
 215         status = "okay";
 216 };
 217
 218 &usbotg2 {
 219         dr_mode = "host";
 220         disable-over-current;
 221         vbus-supply = <&reg_usb_otg2_vbus>;
 222         status = "okay";
 223 };
 224
 225 /* microSD */
 226 &usdhc2 {
 227         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 228         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 229         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 230         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 231         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 232         bus-width = <4>;
 233         vmmc-supply = <&reg_3p3v>;
 234         status = "okay";
 235 };
 236
 237 &iomuxc {
 238         pinctrl-names = "default";
 239         pinctrl-0 = <&pinctrl_hog>;
 240
 241         pinctrl_hog: hoggrp {
 242                 fsl,pins = <
 243                         MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3         0x40000041 /* PLUG_TEST */
 244                         MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6       0x40000041 /* PCI_USBSEL */
 245                         MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7        0x40000041 /* PCIE_WDIS# */
 246                         MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7       0x40000041 /* DIO0 */
 247                         MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9       0x40000041 /* DIO1 */
 248                         MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0       0x40000104 /* RS485_TERM */
 249                         MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0        0x40000104 /* RS485 */
 250                         MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2        0x40000104 /* RS485_HALF */
 251                 >;
 252         };
 253
 254         pinctrl_accel: accelgrp {
 255                 fsl,pins = <
 256                         MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5        0x159
 257                 >;
 258         };
 259
 260         pinctrl_gpio_leds: gpioledgrp {
 261                 fsl,pins = <
 262                         MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5    0x19
 263                         MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4         0x19
 264                 >;
 265         };
 266
 267         pinctrl_i2c3: i2c3grp {
 268                 fsl,pins = <
 269                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 270                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 271                 >;
 272         };
 273
 274         pinctrl_pcie0: pcie0grp {
 275                 fsl,pins = <
 276                         MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6        0x41
 277                 >;
 278         };
 279
 280         pinctrl_pps: ppsgrp {
 281                 fsl,pins = <
 282                         MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x41
 283                 >;
 284         };
 285
 286         pinctrl_reg_usb1_en: regusb1grp {
 287                 fsl,pins = <
 288                         MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x41
 289                         MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC     0x41
 290                 >;
 291         };
 292
 293         pinctrl_reg_usb2_en: regusb2grp {
 294                 fsl,pins = <
 295                         MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8       0x41
 296                 >;
 297         };
 298
 299         pinctrl_sai3: sai3grp {
 300                 fsl,pins = <
 301                         MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
 302                         MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
 303                         MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
 304                         MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
 305                         MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0     0xd6
 306                 >;
 307         };
 308
 309         pinctrl_spi2: spi2grp {
 310                 fsl,pins = <
 311                         MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
 312                         MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0xd6
 313                         MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0xd6
 314                         MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0xd6
 315                 >;
 316         };
 317
 318         pinctrl_uart1: uart1grp {
 319                 fsl,pins = <
 320                         MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 321                         MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 322                 >;
 323         };
 324
 325         pinctrl_uart3: uart3grp {
 326                 fsl,pins = <
 327                         MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX     0x140
 328                         MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX     0x140
 329                 >;
 330         };
 331
 332         pinctrl_uart4: uart4grp {
 333                 fsl,pins = <
 334                         MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX     0x140
 335                         MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX     0x140
 336                 >;
 337         };
 338
 339         pinctrl_usdhc1: usdhc1grp {
 340                 fsl,pins = <
 341                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
 342                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
 343                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
 344                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
 345                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
 346                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
 347                 >;
 348         };
 349
 350         pinctrl_usdhc2: usdhc2grp {
 351                 fsl,pins = <
 352                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 353                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 354                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 355                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 356                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 357                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 358                 >;
 359         };
 360
 361         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 362                 fsl,pins = <
 363                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 364                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 365                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 366                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 367                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 368                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 369                 >;
 370         };
 371
 372         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 373                 fsl,pins = <
 374                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 375                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 376                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 377                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 378                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 379                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 380                 >;
 381         };
 382
 383         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 384                 fsl,pins = <
 385                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12        0x1c4
 386                         MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
 387                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 388                 >;
 389         };
 390 };