1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2020 Gateworks Corporation
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/net/ti-dp83867.h>
12 device_type = "memory";
13 reg = <0x0 0x40000000 0 0x80000000>;
17 compatible = "gpio-keys";
21 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
28 interrupt-parent = <&gsc>;
35 interrupt-parent = <&gsc>;
42 interrupt-parent = <&gsc>;
49 interrupt-parent = <&gsc>;
54 label = "switch_hold";
56 interrupt-parent = <&gsc>;
63 cpu-supply = <&buck3_reg>;
67 cpu-supply = <&buck3_reg>;
71 cpu-supply = <&buck3_reg>;
75 cpu-supply = <&buck3_reg>;
79 operating-points-v2 = <&ddrc_opp_table>;
81 ddrc_opp_table: opp-table {
82 compatible = "operating-points-v2";
85 opp-hz = /bits/ 64 <25000000>;
89 opp-hz = /bits/ 64 <100000000>;
93 opp-hz = /bits/ 64 <750000000>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_fec1>;
101 phy-mode = "rgmii-id";
102 phy-handle = <ðphy0>;
106 #address-cells = <1>;
109 ethphy0: ethernet-phy@0 {
110 compatible = "ethernet-phy-ieee802.3-c22";
112 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
113 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
114 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
115 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
121 clock-frequency = <100000>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_i2c1>;
127 compatible = "gw,gsc";
129 pinctrl-0 = <&pinctrl_gsc>;
130 interrupt-parent = <&gpio2>;
131 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
132 interrupt-controller;
133 #interrupt-cells = <1>;
134 #address-cells = <1>;
138 compatible = "gw,gsc-adc";
139 #address-cells = <1>;
164 gw,voltage-divider-ohms = <22100 1000>;
171 gw,voltage-divider-ohms = <10000 10000>;
178 gw,voltage-divider-ohms = <10000 10000>;
203 gw,voltage-divider-ohms = <10000 10000>;
210 gw,voltage-divider-ohms = <10000 10000>;
229 gw,voltage-divider-ohms = <10000 10000>;
234 #address-cells = <1>;
236 compatible = "gw,gsc-fan";
242 compatible = "nxp,pca9555";
246 interrupt-parent = <&gsc>;
251 compatible = "atmel,24c02";
257 compatible = "atmel,24c02";
263 compatible = "atmel,24c02";
269 compatible = "atmel,24c02";
275 compatible = "dallas,ds1672";
280 compatible = "mps,mp5416";
284 /* vdd_0p95: DRAM/GPU/VPU */
286 regulator-name = "buck1";
287 regulator-min-microvolt = <800000>;
288 regulator-max-microvolt = <1000000>;
289 regulator-min-microamp = <3800000>;
290 regulator-max-microamp = <6800000>;
297 regulator-name = "buck2";
298 regulator-min-microvolt = <800000>;
299 regulator-max-microvolt = <900000>;
300 regulator-min-microamp = <2200000>;
301 regulator-max-microamp = <5200000>;
308 regulator-name = "buck3";
309 regulator-min-microvolt = <800000>;
310 regulator-max-microvolt = <1000000>;
311 regulator-min-microamp = <3800000>;
312 regulator-max-microamp = <6800000>;
318 regulator-name = "buck4";
319 regulator-min-microvolt = <1800000>;
320 regulator-max-microvolt = <1800000>;
321 regulator-min-microamp = <2200000>;
322 regulator-max-microamp = <5200000>;
329 regulator-name = "ldo1";
330 regulator-min-microvolt = <1800000>;
331 regulator-max-microvolt = <1800000>;
338 regulator-name = "ldo2";
339 regulator-min-microvolt = <800000>;
340 regulator-max-microvolt = <800000>;
347 regulator-name = "ldo3";
348 regulator-min-microvolt = <900000>;
349 regulator-max-microvolt = <900000>;
356 regulator-name = "ldo4";
357 regulator-min-microvolt = <1800000>;
358 regulator-max-microvolt = <1800000>;
367 clock-frequency = <400000>;
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_i2c2>;
373 compatible = "atmel,24c32";
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_uart2>;
388 pinctrl-names = "default", "state_100mhz", "state_200mhz";
389 pinctrl-0 = <&pinctrl_usdhc3>;
390 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
391 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_wdog>;
400 fsl,ext-reset-output;
405 pinctrl_fec1: fec1grp {
407 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
408 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
409 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
410 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
411 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
412 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
413 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
414 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
415 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
416 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
417 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
418 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
419 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
420 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
421 MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19
425 pinctrl_gsc: gscgrp {
427 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159
431 pinctrl_i2c1: i2c1grp {
433 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
434 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
438 pinctrl_i2c2: i2c2grp {
440 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
441 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
445 pinctrl_uart2: uart2grp {
447 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
448 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
452 pinctrl_usdhc3: usdhc3grp {
454 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
455 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
456 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
457 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
458 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
459 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
460 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
461 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
462 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
463 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
464 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
468 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
470 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
471 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
472 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
473 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
474 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
475 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
476 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
477 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
478 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
479 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
480 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
484 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
486 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
487 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
488 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
489 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
490 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
491 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
492 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
493 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
494 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
495 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
496 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
500 pinctrl_wdog: wdoggrp {
502 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6