1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2020-2021 TQ-Systems GmbH
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 model = "TQ-Systems GmbH i.MX8MM TQMa8MxML";
11 compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
14 device_type = "memory";
15 /* our minimum RAM config will be 1024 MiB */
16 reg = <0x00000000 0x40000000 0 0x40000000>;
19 /* e-MMC IO, needed for HS modes */
20 reg_vcc1v8: regulator-vcc1v8 {
21 compatible = "regulator-fixed";
22 regulator-name = "TQMA8MXML_VCC1V8";
23 regulator-min-microvolt = <1800000>;
24 regulator-max-microvolt = <1800000>;
27 /* identical to buck4_reg, but should never change */
28 reg_vcc3v3: regulator-vcc3v3 {
29 compatible = "regulator-fixed";
30 regulator-name = "TQMA8MXML_VCC3V3";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
40 /* global autoconfigured region for contiguous allocations */
42 compatible = "shared-dma-pool";
45 size = <0 0x28000000>;
46 /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
47 alloc-ranges = <0 0x40000000 0 0x78000000>;
54 cpu-supply = <&buck2_reg>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_flexspi>;
63 compatible = "jedec,spi-nor";
67 spi-max-frequency = <84000000>;
68 spi-tx-bus-width = <1>;
69 spi-rx-bus-width = <4>;
82 clock-frequency = <100000>;
83 pinctrl-names = "default", "gpio";
84 pinctrl-0 = <&pinctrl_i2c1>;
85 pinctrl-1 = <&pinctrl_i2c1_gpio>;
86 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
87 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
90 sensor0: temperature-sensor@1b {
91 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
96 compatible = "nxp,pca9450a";
99 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
100 pinctrl-0 = <&pinctrl_pmic>;
101 pinctrl-names = "default";
102 interrupt-parent = <&gpio1>;
103 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
106 /* V_0V85_SOC: 0.85 */
108 regulator-name = "BUCK1";
109 regulator-min-microvolt = <850000>;
110 regulator-max-microvolt = <850000>;
113 regulator-ramp-delay = <3125>;
118 regulator-name = "BUCK2";
119 regulator-min-microvolt = <850000>;
120 regulator-max-microvolt = <1000000>;
123 nxp,dvs-run-voltage = <950000>;
124 nxp,dvs-standby-voltage = <850000>;
125 regulator-ramp-delay = <3125>;
128 /* V_0V85_GPU / DRAM / VPU */
130 regulator-name = "BUCK3";
131 regulator-min-microvolt = <850000>;
132 regulator-max-microvolt = <950000>;
135 regulator-ramp-delay = <3125>;
138 /* VCC3V3 -> VMMC, ... must not be changed */
140 regulator-name = "BUCK4";
141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <3300000>;
147 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
149 regulator-name = "BUCK5";
150 regulator-min-microvolt = <1800000>;
151 regulator-max-microvolt = <1800000>;
156 /* V_1V1 -> RAM, ... must not be changed */
158 regulator-name = "BUCK6";
159 regulator-min-microvolt = <1100000>;
160 regulator-max-microvolt = <1100000>;
167 regulator-name = "LDO1";
168 regulator-min-microvolt = <1800000>;
169 regulator-max-microvolt = <1800000>;
176 regulator-name = "LDO2";
177 regulator-min-microvolt = <800000>;
178 regulator-max-microvolt = <850000>;
185 regulator-name = "LDO3";
186 regulator-min-microvolt = <1800000>;
187 regulator-max-microvolt = <1800000>;
194 regulator-name = "LDO4";
195 regulator-min-microvolt = <900000>;
196 regulator-max-microvolt = <900000>;
201 /* VCC SD IO - switched using SD2 VSELECT */
203 regulator-name = "LDO5";
204 regulator-min-microvolt = <1800000>;
205 regulator-max-microvolt = <3300000>;
212 compatible = "nxp,pcf85063a";
214 quartz-load-femtofarads = <7000>;
218 compatible = "nxp,se97b", "atmel,24c02";
222 vcc-supply = <®_vcc3v3>;
226 compatible = "atmel,24c64";
229 vcc-supply = <®_vcc3v3>;
234 vddcore-supply = <&ldo4_reg>;
235 vddio-supply = <&ldo3_reg>;
239 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
240 fsl,clkreq-unsupported;
244 pinctrl-names = "default", "state_100mhz", "state_200mhz";
245 pinctrl-0 = <&pinctrl_usdhc3>;
246 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
247 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
252 vmmc-supply = <®_vcc3v3>;
253 vqmmc-supply = <®_vcc1v8>;
259 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR
260 * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO.
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_wdog>;
265 fsl,ext-reset-output;
270 pinctrl_flexspi: flexspigrp {
271 fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82>,
272 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>,
273 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>,
274 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>,
275 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>,
276 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>;
279 pinctrl_i2c1: i2c1grp {
280 fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000004>,
281 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000004>;
284 pinctrl_i2c1_gpio: i2c1gpiogrp {
285 fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000004>,
286 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000004>;
289 pinctrl_pmic: pmicgrp {
290 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>;
293 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
294 fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>;
297 pinctrl_usdhc3: usdhc3grp {
298 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>,
299 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
300 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
301 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
302 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
303 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
304 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
305 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
306 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
307 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
308 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
309 /* option USDHC3_RESET_B not defined, only in RM */
310 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
313 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
314 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>,
315 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
316 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
317 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
318 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
319 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
320 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
321 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
322 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
323 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
324 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
325 /* option USDHC3_RESET_B not defined, only in RM */
326 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
329 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
330 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>,
331 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
332 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
333 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
334 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
335 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
336 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
337 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
338 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
339 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
340 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
341 /* option USDHC3_RESET_B not defined, only in RM */
342 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
345 pinctrl_wdog: wdoggrp {
346 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>;