arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts

   1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
   2 /*
   3  * Copyright 2020-2021 TQ-Systems GmbH
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "imx8mm-tqma8mqml.dtsi"
   9 #include "mba8mx.dtsi"
  10
  11 / {
  12         model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx";
  13         compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
  14
  15         aliases {
  16                 eeprom0 = &eeprom3;
  17                 mmc0 = &usdhc3;
  18                 mmc1 = &usdhc2;
  19                 mmc2 = &usdhc1;
  20                 rtc0 = &pcf85063;
  21                 rtc1 = &snvs_rtc;
  22         };
  23
  24         reg_usdhc2_vmmc: regulator-vmmc {
  25                 compatible = "regulator-fixed";
  26                 pinctrl-names = "default";
  27                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  28                 regulator-name = "VSD_3V3";
  29                 regulator-min-microvolt = <3300000>;
  30                 regulator-max-microvolt = <3300000>;
  31                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  32                 enable-active-high;
  33                 startup-delay-us = <100>;
  34                 off-on-delay-us = <12000>;
  35         };
  36
  37         connector {
  38                 compatible = "gpio-usb-b-connector", "usb-b-connector";
  39                 type = "micro";
  40                 label = "X19";
  41                 pinctrl-names = "default";
  42                 pinctrl-0 = <&pinctrl_usb1_connector>;
  43                 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
  44
  45                 ports {
  46                         #address-cells = <1>;
  47                         #size-cells = <0>;
  48
  49                         port@0 {
  50                                 reg = <0>;
  51                                 usb_dr_connector: endpoint {
  52                                         remote-endpoint = <&usb1_drd_sw>;
  53                                 };
  54                         };
  55                 };
  56         };
  57 };
  58
  59 &i2c1 {
  60         expander2: gpio@27 {
  61                 compatible = "nxp,pca9555";
  62                 reg = <0x27>;
  63                 gpio-controller;
  64                 #gpio-cells = <2>;
  65                 vcc-supply = <&reg_vcc_3v3>;
  66                 pinctrl-names = "default";
  67                 pinctrl-0 = <&pinctrl_expander>;
  68                 interrupt-parent = <&gpio1>;
  69                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
  70                 interrupt-controller;
  71                 #interrupt-cells = <2>;
  72         };
  73 };
  74
  75 &pcie_phy {
  76         clocks = <&pcie0_refclk>;
  77         status = "okay";
  78 };
  79
  80 &pcie0 {
  81         reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
  82         clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
  83                  <&clk IMX8MM_CLK_PCIE1_AUX>;
  84         assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
  85                                 <&clk IMX8MM_CLK_PCIE1_CTRL>;
  86         assigned-clock-rates = <10000000>, <250000000>;
  87         assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
  88                                 <&clk IMX8MM_SYS_PLL2_250M>;
  89         status = "okay";
  90 };
  91
  92 &sai3 {
  93         assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
  94         assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  95         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
  96         clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
  97                 <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
  98                 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
  99                 <&clk IMX8MM_AUDIO_PLL2_OUT>;
 100 };
 101
 102 &tlv320aic3x04 {
 103         clock-names = "mclk";
 104         clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
 105 };
 106
 107 &uart1 {
 108         assigned-clocks = <&clk IMX8MM_CLK_UART1>;
 109         assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
 110 };
 111
 112 &uart2 {
 113         assigned-clocks = <&clk IMX8MM_CLK_UART2>;
 114         assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
 115 };
 116
 117 &usbotg1 {
 118         pinctrl-names = "default";
 119         pinctrl-0 = <&pinctrl_usbotg1>;
 120         dr_mode = "otg";
 121         srp-disable;
 122         hnp-disable;
 123         adp-disable;
 124         power-active-high;
 125         over-current-active-low;
 126         usb-role-switch;
 127         status = "okay";
 128
 129         port {
 130                 usb1_drd_sw: endpoint {
 131                         remote-endpoint = <&usb_dr_connector>;
 132                 };
 133         };
 134 };
 135
 136 &usbotg2 {
 137         dr_mode = "host";
 138         disable-over-current;
 139         vbus-supply = <&reg_hub_vbus>;
 140         status = "okay";
 141 };
 142
 143 &iomuxc {
 144         pinctrl_ecspi1: ecspi1grp {
 145                 fsl,pins = <MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK        0x00000006>,
 146                            <MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI        0x00000006>,
 147                            <MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO        0x00000006>,
 148                            <MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9           0x00000006>;
 149         };
 150
 151         pinctrl_ecspi2: ecspi2grp {
 152                 fsl,pins = <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK        0x00000006>,
 153                            <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI        0x00000006>,
 154                            <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO        0x00000006>,
 155                            <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13          0x00000006>;
 156         };
 157
 158         pinctrl_expander: expandergrp {
 159                 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9           0x94>;
 160         };
 161
 162         pinctrl_fec1: fec1grp {
 163                 fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC             0x40000002>,
 164                            <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO           0x40000002>,
 165                            <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3       0x14>,
 166                            <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2       0x14>,
 167                            <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1       0x14>,
 168                            <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0       0x14>,
 169                            <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3       0x90>,
 170                            <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2       0x90>,
 171                            <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1       0x90>,
 172                            <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0       0x90>,
 173                            <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC       0x14>,
 174                            <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC       0x90>,
 175                            <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90>,
 176                            <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14>;
 177         };
 178
 179         pinctrl_gpiobutton: gpiobuttongrp {
 180                 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5           0x84>,
 181                            <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7           0x84>,
 182                            <MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0              0x84>;
 183         };
 184
 185         pinctrl_gpioled: gpioledgrp {
 186                 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0           0x84>,
 187                            <MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14            0x84>;
 188         };
 189
 190         pinctrl_i2c2: i2c2grp {
 191                 fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL              0x40000004>,
 192                            <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA              0x40000004>;
 193         };
 194
 195         pinctrl_i2c2_gpio: i2c2gpiogrp {
 196                 fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16            0x40000004>,
 197                            <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17            0x40000004>;
 198         };
 199
 200         pinctrl_i2c3: i2c3grp {
 201                 fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL              0x40000004>,
 202                            <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA              0x40000004>;
 203         };
 204
 205         pinctrl_i2c3_gpio: i2c3gpiogrp {
 206                 fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18            0x40000004>,
 207                            <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19            0x40000004>;
 208         };
 209
 210         pinctrl_pwm3: pwm3grp {
 211                 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT            0x14>;
 212         };
 213
 214         pinctrl_pwm4: pwm4grp {
 215                 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT            0x14>;
 216         };
 217
 218         pinctrl_sai3: sai3grp {
 219                 fsl,pins = <MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK            0x94>,
 220                            <MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK          0x94>,
 221                            <MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC         0x94>,
 222                            <MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0         0x94>,
 223                            <MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC         0x94>,
 224                            <MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0         0x94>,
 225                            <MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK          0x94>;
 226         };
 227
 228         pinctrl_uart1: uart1grp {
 229                 fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX         0x16>,
 230                            <MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX         0x16>;
 231         };
 232
 233         pinctrl_uart2: uart2grp {
 234                 fsl,pins = <MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX         0x16>,
 235                            <MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX         0x16>;
 236         };
 237
 238         pinctrl_uart3: uart3grp {
 239                 fsl,pins = <MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX         0x16>,
 240                            <MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX         0x16>;
 241         };
 242
 243         pinctrl_uart4: uart4grp {
 244                 fsl,pins = <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX         0x16>,
 245                            <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX         0x16>;
 246         };
 247
 248         pinctrl_usbotg1: usbotg1grp {
 249                 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR        0x84>,
 250                            <MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC         0x84>;
 251         };
 252
 253         pinctrl_usb1_connector: usb1-connectorgrp {
 254                 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10          0x1c0>;
 255         };
 256
 257         pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
 258                 fsl,pins = <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12            0x84>;
 259         };
 260
 261         pinctrl_usdhc2: usdhc2grp {
 262                 fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK             0x1d4>,
 263                            <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD             0x1d4>,
 264                            <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0         0x1d4>,
 265                            <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1         0x1d4>,
 266                            <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2         0x1d4>,
 267                            <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3         0x1d4>,
 268                            <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0x84>;
 269         };
 270
 271         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 272                 fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK             0x1d4>,
 273                            <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD             0x1d4>,
 274                            <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0         0x1d4>,
 275                            <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1         0x1d4>,
 276                            <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2         0x1d4>,
 277                            <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3         0x1d4>,
 278                            <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0x84>;
 279         };
 280
 281         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 282                 fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK             0x1d4>,
 283                            <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD             0x1d4>,
 284                            <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0         0x1d4>,
 285                            <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1         0x1d4>,
 286                            <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2         0x1d4>,
 287                            <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3         0x1d4>,
 288                            <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0x84>;
 289         };
 290 };