1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
8 #include <dt-bindings/net/ti-dp83867.h>
11 model = "PHYTEC phyCORE-i.MX8MM";
12 compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
20 device_type = "memory";
21 reg = <0x0 0x40000000 0 0x80000000>;
24 reg_vdd_3v3_s: regulator-vdd-3v3-s {
25 compatible = "regulator-fixed";
28 regulator-max-microvolt = <3300000>;
29 regulator-min-microvolt = <3300000>;
30 regulator-name = "VDD_3V3_S";
35 cpu-supply = <®_vdd_arm>;
39 cpu-supply = <®_vdd_arm>;
43 cpu-supply = <®_vdd_arm>;
47 cpu-supply = <®_vdd_arm>;
51 operating-points-v2 = <&ddrc_opp_table>;
53 ddrc_opp_table: opp-table {
54 compatible = "operating-points-v2";
57 opp-hz = /bits/ 64 <25000000>;
61 opp-hz = /bits/ 64 <100000000>;
65 opp-hz = /bits/ 64 <750000000>;
73 phy-mode = "rgmii-id";
74 phy-handle = <ðphy0>;
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_fec1>;
83 ethphy0: ethernet-phy@0 {
84 compatible = "ethernet-phy-ieee802.3-c22";
85 enet-phy-lane-no-swap;
86 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
87 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
88 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
89 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
91 reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
92 reset-assert-us = <1000>;
93 reset-deassert-us = <1000>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_flexspi0>;
105 #address-cells = <1>;
107 compatible = "jedec,spi-nor";
109 spi-max-frequency = <80000000>;
110 spi-rx-bus-width = <4>;
111 spi-tx-bus-width = <1>;
116 gpio-line-names = "", "", "WDOG_INT", "X_RTC_INT",
117 "", "", "", "RESET_ETHPHY",
118 "", "", "nENABLE_FLATLINK";
123 clock-frequency = <400000>;
124 pinctrl-names = "default","gpio";
125 pinctrl-0 = <&pinctrl_i2c1>;
126 pinctrl-1 = <&pinctrl_i2c1_gpio>;
127 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
128 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
132 compatible = "nxp,pf8121a";
139 regulator-max-microvolt = <3300000>;
140 regulator-min-microvolt = <3300000>;
141 regulator-name = "NVCC_SD1 (LDO1)";
143 regulator-state-mem {
144 regulator-off-in-suspend;
151 regulator-max-microvolt = <3300000>;
152 regulator-min-microvolt = <1800000>;
153 regulator-name = "NVCC_SD2 (LDO2)";
155 regulator-state-mem {
156 regulator-off-in-suspend;
163 regulator-max-microvolt = <2500000>;
164 regulator-min-microvolt = <1500000>;
165 regulator-name = "VCC_ENET_2V5 (LDO3)";
167 regulator-state-mem {
168 regulator-off-in-suspend;
175 regulator-max-microvolt = <1800000>;
176 regulator-min-microvolt = <1500000>;
177 regulator-name = "VDDA_1V8 (LDO4)";
179 regulator-state-mem {
180 regulator-on-in-suspend;
181 regulator-suspend-min-microvolt = <1500000>;
182 regulator-suspend-max-microvolt = <1500000>;
186 reg_soc_vdda_phy: buck1 {
189 regulator-max-microvolt = <900000>;
190 regulator-min-microvolt = <400000>;
191 regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)";
193 regulator-state-mem {
194 regulator-on-in-suspend;
195 regulator-suspend-min-microvolt = <400000>;
196 regulator-suspend-max-microvolt = <400000>;
200 reg_vdd_gpu_dram: buck2 {
203 regulator-max-microvolt = <1000000>;
204 regulator-min-microvolt = <1000000>;
205 regulator-name = "VDD_GPU_DRAM (BUCK2)";
207 regulator-state-mem {
208 regulator-on-in-suspend;
209 regulator-suspend-max-microvolt = <1000000>;
210 regulator-suspend-min-microvolt = <1000000>;
217 regulator-max-microvolt = <1000000>;
218 regulator-min-microvolt = <400000>;
219 regulator-name = "VDD_VPU (BUCK3)";
221 regulator-state-mem {
222 regulator-off-in-suspend;
226 reg_vdd_mipi: buck4 {
229 regulator-max-microvolt = <1050000>;
230 regulator-min-microvolt = <900000>;
231 regulator-name = "VDD_MIPI_0P9 (BUCK4)";
233 regulator-state-mem {
234 regulator-off-in-suspend;
241 regulator-max-microvolt = <1050000>;
242 regulator-min-microvolt = <400000>;
243 regulator-name = "VDD_ARM (BUCK5)";
245 regulator-state-mem {
246 regulator-off-in-suspend;
253 regulator-max-microvolt = <1800000>;
254 regulator-min-microvolt = <1800000>;
255 regulator-name = "VDD_1V8 (BUCK6)";
257 regulator-state-mem {
258 regulator-on-in-suspend;
259 regulator-suspend-max-microvolt = <1800000>;
260 regulator-suspend-min-microvolt = <1800000>;
264 reg_nvcc_dram: buck7 {
267 regulator-max-microvolt = <1100000>;
268 regulator-min-microvolt = <1100000>;
269 regulator-name = "NVCC_DRAM_1P1V (BUCK7)";
275 regulator-max-microvolt = <1800000>;
276 regulator-min-microvolt = <1800000>;
277 regulator-name = "NVCC_SNVS_1P8 (VSNVS)";
282 sn65dsi83: bridge@2d {
283 compatible = "ti,sn65dsi83";
284 enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_sn65dsi83>;
292 compatible = "atmel,24c32";
295 vcc-supply = <®_vdd_3v3_s>;
299 compatible = "microcrystal,rv3028";
300 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
301 interrupt-parent = <&gpio1>;
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_rtc>;
310 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
311 assigned-clock-rates = <400000000>;
313 keep-power-in-suspend;
314 pinctrl-names = "default", "state_100mhz", "state_200mhz";
315 pinctrl-0 = <&pinctrl_usdhc3>;
316 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
317 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
324 fsl,ext-reset-output;
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_wdog>;
331 pinctrl_fec1: fec1grp {
333 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2
334 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2
335 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
336 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
337 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
338 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
339 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
340 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
341 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16
342 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16
343 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16
344 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16
345 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16
346 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16
347 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10
351 pinctrl_flexspi0: flexspi0grp {
353 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
354 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
355 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
356 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
357 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
358 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
362 pinctrl_i2c1: i2c1grp {
364 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0
365 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0
369 pinctrl_i2c1_gpio: i2c1gpiogrp {
371 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0
372 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0
376 pinctrl_rtc: rtcgrp {
378 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
382 pinctrl_sn65dsi83: sn65dsi83grp {
384 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0
388 pinctrl_usdhc3: usdhc3grp {
390 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
391 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
392 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
393 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
394 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
395 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
396 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
397 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
398 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
399 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
400 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
404 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
406 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
407 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
408 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
409 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
410 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
411 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
412 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
413 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
414 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
415 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
416 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
420 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
422 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
423 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
424 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
425 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
426 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
427 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
428 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
429 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
430 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
431 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
432 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
436 pinctrl_wdog: wdoggrp {
438 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26