1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include "imx8mm-phycore-som.dtsi"
15 model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
16 compatible = "phytec,imx8mm-phyboard-polis-rdk",
17 "phytec,imx8mm-phycore-som", "fsl,imx8mm";
23 bt_osc_32k: bt-lp-clock {
24 compatible = "fixed-clock";
25 clock-frequency = <32768>;
26 clock-output-names = "bt_osc_32k";
30 can_osc_40m: can-clock {
31 compatible = "fixed-clock";
32 clock-frequency = <40000000>;
33 clock-output-names = "can_osc_40m";
38 compatible = "gpio-fan";
39 gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
40 gpio-fan,speed-map = <0 0
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_fan>;
48 compatible = "gpio-leds";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_leds>;
53 color = <LED_COLOR_ID_RED>;
54 function = LED_FUNCTION_DISK;
55 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
56 linux,default-trigger = "mmc2";
60 color = <LED_COLOR_ID_BLUE>;
61 function = LED_FUNCTION_DISK;
62 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
63 linux,default-trigger = "mmc1";
67 color = <LED_COLOR_ID_GREEN>;
68 function = LED_FUNCTION_CPU;
69 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
70 linux,default-trigger = "heartbeat";
74 usdhc1_pwrseq: pwr-seq {
75 compatible = "mmc-pwrseq-simple";
76 post-power-on-delay-ms = <100>;
77 power-off-delay-us = <60>;
78 reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
81 reg_can_en: regulator-can-en {
82 compatible = "regulator-fixed";
83 gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_can_en>;
86 regulator-max-microvolt = <3300000>;
87 regulator-min-microvolt = <3300000>;
88 regulator-name = "CAN_EN";
89 startup-delay-us = <20>;
92 reg_usb_otg1_vbus: regulator-usb-otg1 {
93 compatible = "regulator-fixed";
94 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_usbotg1pwrgrp>;
98 regulator-name = "usb_otg1_vbus";
99 regulator-max-microvolt = <5000000>;
100 regulator-min-microvolt = <5000000>;
103 reg_usdhc2_vmmc: regulator-usdhc2 {
104 compatible = "regulator-fixed";
105 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
107 off-on-delay-us = <20000>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
110 regulator-max-microvolt = <3300000>;
111 regulator-min-microvolt = <3300000>;
112 regulator-name = "VSD_3V3";
115 reg_vcc_3v3: regulator-vcc-3v3 {
116 compatible = "regulator-fixed";
117 regulator-max-microvolt = <3300000>;
118 regulator-min-microvolt = <3300000>;
119 regulator-name = "VCC_3V3";
123 /* SPI - CAN MCP251XFD */
125 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_ecspi1>;
131 compatible = "microchip,mcp251xfd";
132 clocks = <&can_osc_40m>;
133 interrupt-parent = <&gpio1>;
134 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_can_int>;
138 spi-max-frequency = <20000000>;
139 xceiver-supply = <®_can_en>;
144 gpio-line-names = "", "LED_RED", "WDOG_INT", "X_RTC_INT",
145 "", "", "", "RESET_ETHPHY",
146 "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
147 "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";
151 gpio-line-names = "", "", "", "",
152 "", "", "BT_REG_ON", "WL_REG_ON",
153 "BT_DEV_WAKE", "BT_HOST_WAKE", "", "",
154 "X_SD2_CD_B", "", "", "",
155 "", "", "", "SD2_RESET_B";
159 gpio-line-names = "", "", "", "",
161 "FAN", "miniPCIe_nPERST", "", "",
166 gpio-line-names = "", "", "", "",
173 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
174 <&clk IMX8MM_CLK_PCIE1_CTRL>;
175 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
176 <&clk IMX8MM_SYS_PLL2_250M>;
177 assigned-clock-rates = <10000000>, <250000000>;
178 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
179 <&clk IMX8MM_CLK_PCIE1_PHY>;
180 clock-names = "pcie", "pcie_aux", "pcie_bus";
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_pcie>;
183 reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
188 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
189 fsl,clkreq-unsupported;
190 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
191 fsl,tx-deemph-gen1 = <0x2d>;
192 fsl,tx-deemph-gen2 = <0xf>;
197 trickle-resistor-ohms = <3000>;
204 /* UART - RS232/RS485 */
206 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
207 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_uart1>;
214 /* UART - Sterling-LWB Bluetooth */
216 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
217 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_uart2_bt>;
225 compatible = "brcm,bcm43438-bt";
226 clocks = <&bt_osc_32k>;
228 device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
229 interrupt-names = "host-wakeup";
230 interrupt-parent = <&gpio2>;
231 interrupts = <9 IRQ_TYPE_EDGE_BOTH>;
232 max-speed = <2000000>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_bt>;
235 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
236 vddio-supply = <®_vcc_3v3>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_uart3>;
251 over-current-active-low;
252 samsung,picophy-pre-emp-curr-control = <3>;
253 samsung,picophy-dc-vol-level-adjust = <7>;
255 vbus-supply = <®_usb_otg1_vbus>;
260 disable-over-current;
262 samsung,picophy-pre-emp-curr-control = <3>;
263 samsung,picophy-dc-vol-level-adjust = <7>;
267 /* SDIO - Sterling-LWB Wifi */
269 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
270 assigned-clock-rates = <200000000>;
272 mmc-pwrseq = <&usdhc1_pwrseq>;
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
277 #address-cells = <1>;
282 compatible = "brcm,bcm4329-fmac";
289 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
290 assigned-clock-rates = <200000000>;
292 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
294 pinctrl-names = "default", "state_100mhz", "state_200mhz";
295 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
296 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
297 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
298 vmmc-supply = <®_usdhc2_vmmc>;
299 vqmmc-supply = <®_nvcc_sd2>;
306 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00
307 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00
308 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00
312 pinctrl_can_en: can-engrp {
314 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
318 pinctrl_can_int: can-intgrp {
320 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
324 pinctrl_ecspi1: ecspi1grp {
326 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80
327 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80
328 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80
329 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
333 pinctrl_fan: fan0grp {
335 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16
339 pinctrl_leds: leds1grp {
341 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
342 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
343 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
347 pinctrl_pcie: pciegrp {
349 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00
350 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
351 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12
355 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
357 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
361 pinctrl_uart1: uart1grp {
363 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00
364 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00
365 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00
366 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00
370 pinctrl_uart2_bt: uart2btgrp {
372 MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00
373 MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00
374 MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00
375 MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00
379 pinctrl_uart3: uart3grp {
381 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
382 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
386 pinctrl_usbotg1pwrgrp: usbotg1pwrgrp {
388 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
392 pinctrl_usdhc1: usdhc1grp {
394 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
395 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
396 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
397 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
398 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
399 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
403 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
405 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
409 pinctrl_usdhc2: usdhc2grp {
411 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
412 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
413 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
414 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
415 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
416 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
417 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
421 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
423 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
424 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
425 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
426 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
427 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
428 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
429 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
433 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
435 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
436 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
437 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
438 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
439 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
440 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
441 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
445 pinctrl_wlan: wlangrp {
447 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00