1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright 2021-2022 Marek Vasut <marex@denx.de>
8 #include "imx8mm-verdin.dtsi"
11 model = "MENLO MX8MM EMBEDDED DEVICE";
12 compatible = "menlo,mx8menlo",
13 "toradex,verdin-imx8mm-nonwifi",
14 "toradex,verdin-imx8mm",
17 /delete-node/ gpio-keys;
20 compatible = "gpio-leds";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_led>;
26 gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
27 linux,default-trigger = "mmc0";
32 gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
33 linux,default-trigger = "heartbeat";
38 compatible = "gpio-beeper";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_beeper>;
41 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
44 /* Fixed clock dedicated to SPI CAN on carrier board */
45 clk_xtal20: clk-xtal20 {
46 compatible = "fixed-clock";
48 clock-frequency = <20000000>;
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_ecspi1>;
57 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
60 /* CAN controller on the baseboard */
62 compatible = "microchip,mcp2518fd";
63 clocks = <&clk_xtal20>;
64 interrupt-parent = <&gpio1>;
65 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
67 spi-max-frequency = <2000000>;
73 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
74 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>;
78 compatible = "menlo,m53cpld";
80 spi-max-frequency = <25000000>;
84 compatible = "menlo,m53cpld";
86 spi-max-frequency = <25000000>;
104 #address-cells = <1>;
106 compatible = "jedec,spi-nor";
107 spi-max-frequency = <66000000>;
108 spi-rx-bus-width = <4>;
109 spi-tx-bus-width = <4>;
144 "", "", "DISP_reset", "KBD_intI",
151 * CPLD_D[n] is ARM_CPLD[n] in schematic
152 * CPLD_int is SA_INTERRUPT in schematic
153 * CPLD_reset is RESET_SOFT in schematic
156 "CPLD_D[6]", "CPLD_int", "CPLD_reset", "",
157 "", "CPLD_D[7]", "", "",
158 "", "", "", "CPLD_D[5]",
159 "CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]",
160 "CPLD_D[0]", "", "", "",
162 "", "", "", "KBD_intK",
191 /* None of this is present on the SoM. */
192 /delete-node/ bridge@2c;
193 /delete-node/ hdmi@48;
194 /delete-node/ touch@4a;
195 /delete-node/ sensor@4f;
196 /delete-node/ eeprom@50;
197 /delete-node/ eeprom@57;
201 pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>,
202 <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
204 pinctrl_beeper: beepergrp {
206 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1c4
210 pinctrl_ecspi1: ecspi1grp {
212 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x4
213 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x4
214 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1c4
215 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x1c4
219 pinctrl_led: ledgrp {
221 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4
222 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4
226 pinctrl_uart4_rts: uart4rtsgrp {
229 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184
237 MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x1c4
244 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4
246 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4
248 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4
250 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4
252 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4
254 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x184
256 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x184
258 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x184
260 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x184
262 MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x184
264 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x184
266 MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x184
268 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x184
270 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4
272 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x1c4
274 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x1c4
276 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x1c4
283 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4
285 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4
287 MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x1c4
289 MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x1c4
294 /delete-property/ enable-active-high;
295 gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
299 /delete-property/ enable-active-high;
300 gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
317 pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>;
318 linux,rs485-enabled-at-boot-time;
319 rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
324 dr_mode = "peripheral";