1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright (C) 2022 Kontron Electronics GmbH
6 #include <dt-bindings/interrupt-controller/irq.h>
10 model = "Kontron OSM-S i.MX8MM (N802X SOM)";
11 compatible = "kontron,imx8mm-osm-s", "fsl,imx8mm";
14 device_type = "memory";
16 * There are multiple SoM flavors with different DDR sizes.
17 * The smallest is 1GB. For larger sizes the bootloader will
18 * update the reg property.
20 reg = <0x0 0x40000000 0 0x80000000>;
29 cpu-supply = <®_vdd_arm>;
33 cpu-supply = <®_vdd_arm>;
37 cpu-supply = <®_vdd_arm>;
41 cpu-supply = <®_vdd_arm>;
45 operating-points-v2 = <&ddrc_opp_table>;
47 ddrc_opp_table: opp-table {
48 compatible = "operating-points-v2";
51 opp-hz = /bits/ 64 <100000000>;
55 opp-hz = /bits/ 64 <750000000>;
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_ecspi1>;
63 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
67 compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
68 spi-max-frequency = <80000000>;
72 compatible = "fixed-partitions";
83 reg = <0x1e0000 0x10000>;
87 label = "env_redundant";
88 reg = <0x1f0000 0x10000>;
95 clock-frequency = <400000>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_i2c1>;
101 compatible = "nxp,pca9450a";
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_pmic>;
105 interrupt-parent = <&gpio1>;
106 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
110 regulator-name = "+0V8_VDD_SOC (BUCK1)";
111 regulator-min-microvolt = <800000>;
112 regulator-max-microvolt = <850000>;
115 regulator-ramp-delay = <3125>;
116 nxp,dvs-run-voltage = <850000>;
117 nxp,dvs-standby-voltage = <800000>;
121 regulator-name = "+0V9_VDD_ARM (BUCK2)";
122 regulator-min-microvolt = <850000>;
123 regulator-max-microvolt = <950000>;
126 regulator-ramp-delay = <3125>;
127 nxp,dvs-run-voltage = <950000>;
128 nxp,dvs-standby-voltage = <850000>;
131 reg_vdd_dram: BUCK3 {
132 regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)";
133 regulator-min-microvolt = <850000>;
134 regulator-max-microvolt = <950000>;
140 regulator-name = "+3V3 (BUCK4)";
141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <3300000>;
148 regulator-name = "+1V8 (BUCK5)";
149 regulator-min-microvolt = <1800000>;
150 regulator-max-microvolt = <1800000>;
155 reg_nvcc_dram: BUCK6 {
156 regulator-name = "+1V1_NVCC_DRAM (BUCK6)";
157 regulator-min-microvolt = <1100000>;
158 regulator-max-microvolt = <1100000>;
163 reg_nvcc_snvs: LDO1 {
164 regulator-name = "+1V8_NVCC_SNVS (LDO1)";
165 regulator-min-microvolt = <1800000>;
166 regulator-max-microvolt = <1800000>;
172 regulator-name = "+0V8_VDD_SNVS (LDO2)";
173 regulator-min-microvolt = <800000>;
174 regulator-max-microvolt = <900000>;
180 regulator-name = "+1V8_VDDA (LDO3)";
181 regulator-min-microvolt = <1800000>;
182 regulator-max-microvolt = <1800000>;
188 regulator-name = "+0V9_VDD_PHY (LDO4)";
189 regulator-min-microvolt = <900000>;
190 regulator-max-microvolt = <900000>;
196 regulator-name = "NVCC_SD (LDO5)";
197 regulator-min-microvolt = <1800000>;
198 regulator-max-microvolt = <3300000>;
204 compatible = "microcrystal,rv3028";
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_rtc>;
208 interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_LOW>;
209 trickle-diode-disable;
213 &uart3 { /* console */
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_uart3>;
220 pinctrl-names = "default", "state_100mhz", "state_200mhz";
221 pinctrl-0 = <&pinctrl_usdhc1>;
222 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
223 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
224 vmmc-supply = <®_vdd_3v3>;
225 vqmmc-supply = <®_vdd_1v8>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_wdog>;
234 fsl,ext-reset-output;
239 pinctrl_ecspi1: ecspi1grp {
241 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
242 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
243 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
244 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
248 pinctrl_i2c1: i2c1grp {
250 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083
251 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083
255 pinctrl_pmic: pmicgrp {
257 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
261 pinctrl_rtc: rtcgrp {
263 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19
267 pinctrl_uart3: uart3grp {
269 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
270 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
274 pinctrl_usdhc1: usdhc1grp {
276 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
277 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
278 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
279 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
280 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
281 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
282 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
283 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
284 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
285 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
286 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
287 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
291 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
293 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
294 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
295 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
296 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
297 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
298 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
299 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
300 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
301 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
302 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
303 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
304 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
308 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
310 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
311 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
312 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
313 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
314 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
315 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
316 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
317 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
318 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
319 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
320 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
321 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
325 pinctrl_wdog: wdoggrp {
327 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6