arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2018 Bang & Olufsen
   4  */
   5
   6 #include "imx8mm.dtsi"
   7 #include <dt-bindings/phy/phy-imx8-pcie.h>
   8
   9 / {
  10         reg_modem: regulator-modem {
  11                 compatible = "regulator-fixed";
  12                 pinctrl-names = "default";
  13                 pinctrl-0 = <&pinctrl_modem_regulator>;
  14                 regulator-min-microvolt = <3300000>;
  15                 regulator-max-microvolt = <3300000>;
  16                 regulator-name = "epdev_on";
  17                 gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  18                 enable-active-high;
  19                 regulator-always-on;
  20         };
  21
  22         reg_3v3_out: regulator-3v3-out {
  23                 compatible = "regulator-fixed";
  24                 regulator-name = "3V3_OUT";
  25                 regulator-min-microvolt = <3300000>;
  26                 regulator-max-microvolt = <3300000>;
  27         };
  28 };
  29
  30 &cpu_alert0 {
  31         temperature = <95000>;
  32 };
  33
  34 &cpu_crit0 {
  35         temperature = <105000>;
  36 };
  37
  38 &ddrc {
  39         operating-points-v2 = <&ddrc_opp_table>;
  40
  41         ddrc_opp_table: opp-table {
  42                 compatible = "operating-points-v2";
  43
  44                 opp-25000000 {
  45                         opp-hz = /bits/ 64 <25000000>;
  46                 };
  47
  48                 opp-100000000 {
  49                         opp-hz = /bits/ 64 <100000000>;
  50                 };
  51
  52                 opp-600000000 {
  53                         opp-hz = /bits/ 64 <600000000>;
  54                 };
  55         };
  56 };
  57
  58 &i2c1 {
  59         clock-frequency = <100000>;
  60         pinctrl-names = "default", "gpio";
  61         pinctrl-0 = <&pinctrl_i2c1>;
  62         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  63         scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  64         sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  65         status = "okay";
  66
  67         pmic@4b {
  68                 compatible = "rohm,bd71847";
  69                 reg = <0x4b>;
  70                 pinctrl-0 = <&pinctrl_pmic>;
  71                 interrupt-parent = <&gpio1>;
  72                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
  73                 rohm,reset-snvs-powered;
  74
  75                 regulators {
  76                         buck1_reg: BUCK1 {
  77                                 regulator-name = "buck1";
  78                                 regulator-min-microvolt = <700000>;
  79                                 regulator-max-microvolt = <1300000>;
  80                                 regulator-boot-on;
  81                                 regulator-always-on;
  82                                 regulator-ramp-delay = <1250>;
  83                                 rohm,dvs-run-voltage = <850000>;
  84                                 rohm,dvs-idle-voltage = <850000>;
  85                                 rohm,dvs-suspend-voltage = <850000>;
  86                         };
  87
  88                         buck2_reg: BUCK2 {
  89                                 regulator-name = "buck2";
  90                                 regulator-min-microvolt = <700000>;
  91                                 regulator-max-microvolt = <1300000>;
  92                                 regulator-boot-on;
  93                                 regulator-always-on;
  94                                 regulator-ramp-delay = <1250>;
  95                                 rohm,dvs-run-voltage = <1000000>;
  96                                 rohm,dvs-idle-voltage = <900000>;
  97                         };
  98
  99                         buck3_reg: BUCK3 {
 100                                 // buck5 in datasheet
 101                                 regulator-name = "buck3";
 102                                 regulator-min-microvolt = <700000>;
 103                                 regulator-max-microvolt = <1350000>;
 104                                 regulator-boot-on;
 105                                 regulator-always-on;
 106                         };
 107
 108                         buck4_reg: BUCK4 {
 109                                 // buck6 in datasheet
 110                                 regulator-name = "buck4";
 111                                 regulator-min-microvolt = <3000000>;
 112                                 regulator-max-microvolt = <3300000>;
 113                                 regulator-boot-on;
 114                                 regulator-always-on;
 115                         };
 116
 117                         buck5_reg: BUCK5 {
 118                                 // buck7 in datasheet
 119                                 regulator-name = "buck5";
 120                                 regulator-min-microvolt = <1605000>;
 121                                 regulator-max-microvolt = <1995000>;
 122                                 regulator-boot-on;
 123                                 regulator-always-on;
 124                         };
 125
 126                         buck6_reg: BUCK6 {
 127                                 // buck8 in datasheet
 128                                 regulator-name = "buck6";
 129                                 regulator-min-microvolt = <800000>;
 130                                 regulator-max-microvolt = <1400000>;
 131                                 regulator-boot-on;
 132                                 regulator-always-on;
 133                         };
 134
 135                         ldo1_reg: LDO1 {
 136                                 regulator-name = "ldo1";
 137                                 regulator-min-microvolt = <1800000>;
 138                                 regulator-max-microvolt = <3300000>;
 139                                 regulator-boot-on;
 140                                 regulator-always-on;
 141                         };
 142
 143                         ldo2_reg: LDO2 {
 144                                 regulator-name = "ldo2";
 145                                 regulator-min-microvolt = <800000>;
 146                                 regulator-max-microvolt = <900000>;
 147                                 regulator-boot-on;
 148                                 regulator-always-on;
 149                         };
 150
 151                         ldo3_reg: LDO3 {
 152                                 regulator-name = "ldo3";
 153                                 regulator-min-microvolt = <1800000>;
 154                                 regulator-max-microvolt = <3300000>;
 155                                 regulator-boot-on;
 156                                 regulator-always-on;
 157                         };
 158
 159                         ldo4_reg: LDO4 {
 160                                 regulator-name = "ldo4";
 161                                 regulator-min-microvolt = <900000>;
 162                                 regulator-max-microvolt = <1800000>;
 163                                 regulator-boot-on;
 164                                 regulator-always-on;
 165                         };
 166
 167                         ldo5_reg: LDO5 {
 168                                 regulator-name = "ldo5";
 169                                 regulator-min-microvolt = <1800000>;
 170                                 regulator-max-microvolt = <3300000>;
 171                         };
 172
 173                         ldo6_reg: LDO6 {
 174                                 regulator-name = "ldo6";
 175                                 regulator-min-microvolt = <900000>;
 176                                 regulator-max-microvolt = <1800000>;
 177                                 regulator-boot-on;
 178                                 regulator-always-on;
 179                         };
 180                 };
 181         };
 182 };
 183
 184 &i2c2 {
 185         clock-frequency = <100000>;
 186         pinctrl-names = "default", "gpio";
 187         pinctrl-0 = <&pinctrl_i2c2>;
 188         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 189         scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 190         sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 191         status = "okay";
 192 };
 193
 194 &i2c3 {
 195         pinctrl-names = "default", "gpio";
 196         pinctrl-0 = <&pinctrl_i2c3>;
 197         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 198         scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 199         sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 200 };
 201
 202 &pcie_phy {
 203         fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
 204         fsl,tx-deemph-gen1 = <0x2d>;
 205         fsl,tx-deemph-gen2 = <0xf>;
 206         status = "okay";
 207 };
 208
 209 &pcie0 {
 210         pinctrl-names = "default";
 211         pinctrl-0 = <&pinctrl_pcie0>;
 212         reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
 213         fsl,max-link-speed = <1>;
 214         assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>;
 215         assigned-clock-rates = <10000000>, <250000000>;
 216         assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>;
 217         status = "okay";
 218 };
 219
 220 &uart1 { /* BT */
 221         pinctrl-names = "default";
 222         pinctrl-0 = <&pinctrl_uart1>;
 223         assigned-clocks = <&clk IMX8MM_CLK_UART1>;
 224         assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
 225         uart-has-rtscts;
 226         status = "okay";
 227
 228         bluetooth {
 229                 compatible = "brcm,bcm4349-bt";
 230                 pinctrl-names = "default";
 231                 pinctrl-0 = <&pinctrl_modem_bt>;
 232                 device-wakeup-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
 233                 host-wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
 234                 shutdown-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
 235                 vbat-supply = <&reg_3v3_out>;
 236                 vddio-supply = <&reg_3v3_out>;
 237                 clocks = <&osc_32k>;
 238                 max-speed = <3000000>;
 239                 clock-names = "extclk";
 240         };
 241 };
 242
 243 &uart2 { /* console */
 244         pinctrl-names = "default";
 245         pinctrl-0 = <&pinctrl_uart2>;
 246 };
 247
 248 &usdhc1 {
 249         pinctrl-names = "default";
 250         pinctrl-0 = <&pinctrl_usdhc1>;
 251         bus-width = <8>;
 252         no-sd;
 253         no-sdio;
 254         non-removable;
 255         status = "okay";
 256 };
 257
 258 &usdhc2 {
 259         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 260         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 261         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 262         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 263         bus-width = <4>;
 264 };
 265
 266 &wdog1 {
 267         pinctrl-names = "default";
 268         pinctrl-0 = <&pinctrl_wdog>;
 269         fsl,ext-reset-output;
 270         status = "okay";
 271 };
 272
 273 &A53_0 {
 274         cpu-supply = <&buck2_reg>;
 275 };
 276
 277 &A53_1 {
 278         cpu-supply = <&buck2_reg>;
 279 };
 280
 281 &A53_2 {
 282         cpu-supply = <&buck2_reg>;
 283 };
 284
 285 &A53_3 {
 286         cpu-supply = <&buck2_reg>;
 287 };
 288
 289 /delete-node/ &sec_jr1; /* Job ring in use by OP-TEE */
 290
 291 &iomuxc {
 292         pinctrl_i2c1: i2c1-grp {
 293                 fsl,pins = <
 294                         MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL  0x400001c3
 295                         MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA  0x400001c3
 296                 >;
 297         };
 298
 299         pinctrl_i2c1_gpio: i2c1-gpio-grp {
 300                 fsl,pins = <
 301                         MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14        0x400001c3
 302                         MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15        0x400001c3
 303                 >;
 304         };
 305
 306         pinctrl_i2c2: i2c2-grp {
 307                 fsl,pins = <
 308                         MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL  0x400001c3
 309                         MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA  0x400001c3
 310                 >;
 311         };
 312
 313         pinctrl_i2c2_gpio: i2c2-gpio-grp {
 314                 fsl,pins = <
 315                         MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16        0x400001c3
 316                         MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17        0x400001c3
 317                 >;
 318         };
 319
 320         pinctrl_i2c3: i2c3-grp {
 321                 fsl,pins = <
 322                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 323                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 324                 >;
 325         };
 326
 327         pinctrl_i2c3_gpio: i2c3-gpio-grp {
 328                 fsl,pins = <
 329                         MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18        0x400001c3
 330                         MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19        0x400001c3
 331                 >;
 332         };
 333
 334         pinctrl_pcie0: pcie0-grp {
 335                 fsl,pins = <
 336                         MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B    0x61
 337                         MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21        0x6
 338                 >;
 339         };
 340
 341         pinctrl_modem_bt: modem-bt-grp {
 342                 fsl,pins = <
 343                         MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5                 0x19
 344                         MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3               0x19
 345                         MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4               0x19
 346                         MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15               0x19
 347                         MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K      0x141
 348                 >;
 349         };
 350
 351         pinctrl_modem_regulator: modem-reg-grp {
 352                 fsl,pins = <
 353                         MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16    0x41
 354                 >;
 355         };
 356
 357         pinctrl_pmic: pmic-irq-grp {
 358                 fsl,pins = <
 359                         MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x41
 360                 >;
 361         };
 362
 363         pinctrl_uart1: uart1-grp {
 364                 fsl,pins = <
 365                         MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 366                         MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 367                         MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B  0x140
 368                         MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B  0x140
 369                 >;
 370         };
 371
 372         pinctrl_uart2: uart2-grp {
 373                 fsl,pins = <
 374                         MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
 375                         MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
 376                 >;
 377         };
 378
 379         pinctrl_usdhc1: usdhc1-grp {
 380                 fsl,pins = <
 381                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x40000190
 382                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
 383                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
 384                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
 385                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
 386                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
 387                         MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4     0x1d0
 388                         MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5     0x1d0
 389                         MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6     0x1d0
 390                         MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7     0x1d0
 391                         MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE   0x190
 392                         MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d0
 393                 >;
 394         };
 395
 396         pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
 397                 fsl,pins = <
 398                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x40000194
 399                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4
 400                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4
 401                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4
 402                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4
 403                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4
 404                         MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4     0x1d4
 405                         MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5     0x1d4
 406                         MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6     0x1d4
 407                         MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7     0x1d4
 408                         MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE   0x194
 409                         MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d4
 410                 >;
 411         };
 412
 413         pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
 414                 fsl,pins = <
 415                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x40000196
 416                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6
 417                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6
 418                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6
 419                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6
 420                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6
 421                         MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4     0x1d6
 422                         MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5     0x1d6
 423                         MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6     0x1d6
 424                         MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7     0x1d6
 425                         MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE   0x196
 426                         MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d6
 427                 >;
 428         };
 429
 430         pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
 431                 fsl,pins = <
 432                         MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x1d0
 433                 >;
 434         };
 435
 436         pinctrl_usdhc2: usdhc2-grp {
 437                 fsl,pins = <
 438                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 439                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 440                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 441                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 442                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 443                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 444                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 445                 >;
 446         };
 447
 448         pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
 449                 fsl,pins = <
 450                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 451                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 452                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 453                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 454                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 455                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 456                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 457                 >;
 458         };
 459
 460         pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
 461                 fsl,pins = <
 462                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 463                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 464                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 465                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 466                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 467                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 468                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 469                 >;
 470         };
 471
 472         pinctrl_wdog: wdog-grp {
 473                 fsl,pins = <
 474                         MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0xc6
 475                 >;
 476         };
 477 };