1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 NXP
4 * Copyright (c) 2019 Engicam srl
5 * Copyright (c) 2020 Amarula Solutions(India)
9 compatible = "engicam,icore-mx8mm", "fsl,imx8mm";
13 cpu-supply = <®_buck4>;
17 cpu-supply = <®_buck4>;
21 cpu-supply = <®_buck4>;
25 cpu-supply = <®_buck4>;
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_fec1>;
31 phy-mode = "rgmii-id";
32 phy-handle = <ðphy>;
38 ethphy: ethernet-phy@3 {
39 compatible = "ethernet-phy-ieee802.3-c22";
41 reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
42 reset-assert-us = <10000>;
48 clock-frequency = <400000>;
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_i2c1>;
54 compatible = "nxp,pf8121a";
59 regulator-min-microvolt = <1500000>;
60 regulator-max-microvolt = <5000000>;
66 regulator-min-microvolt = <1500000>;
67 regulator-max-microvolt = <5000000>;
73 regulator-min-microvolt = <1500000>;
74 regulator-max-microvolt = <5000000>;
80 regulator-min-microvolt = <1500000>;
81 regulator-max-microvolt = <5000000>;
87 regulator-min-microvolt = <400000>;
88 regulator-max-microvolt = <1800000>;
94 regulator-min-microvolt = <400000>;
95 regulator-max-microvolt = <1800000>;
101 regulator-min-microvolt = <400000>;
102 regulator-max-microvolt = <1800000>;
108 regulator-min-microvolt = <400000>;
109 regulator-max-microvolt = <1800000>;
115 regulator-min-microvolt = <400000>;
116 regulator-max-microvolt = <1800000>;
122 regulator-min-microvolt = <400000>;
123 regulator-max-microvolt = <1800000>;
129 regulator-min-microvolt = <3300000>;
130 regulator-max-microvolt = <3300000>;
136 regulator-min-microvolt = <1800000>;
137 regulator-max-microvolt = <3300000>;
146 pinctrl_fec1: fec1grp {
148 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
149 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
150 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
151 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
152 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
153 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
154 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
155 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
156 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
157 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
158 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
159 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
160 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
161 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
162 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19
166 pinctrl_i2c1: i2c1grp {
168 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
169 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
173 pinctrl_usdhc3: usdhc3grp {
175 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
176 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
177 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
178 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
179 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
180 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
181 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
182 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
183 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
184 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
185 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
186 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
190 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
192 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
193 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
194 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
195 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
196 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
197 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
198 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
199 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
200 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
201 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
202 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
206 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
208 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
209 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
210 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
211 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
212 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
213 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
214 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
215 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
216 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
217 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
218 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
225 pinctrl-names = "default", "state_100mhz", "state_200mhz";
226 pinctrl-0 = <&pinctrl_usdhc3>;
227 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
228 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;