1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 #include <dt-bindings/usb/pd.h>
10 #include "imx8mm.dtsi"
18 device_type = "memory";
19 reg = <0x0 0x40000000 0 0x80000000>;
23 compatible = "hdmi-connector";
28 hdmi_connector_in: endpoint {
29 remote-endpoint = <&adv7535_out>;
35 compatible = "gpio-leds";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_gpio_led>;
41 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
46 pcie0_refclk: pcie0-refclk {
47 compatible = "fixed-clock";
49 clock-frequency = <100000000>;
52 reg_pcie0: regulator-pcie {
53 compatible = "regulator-fixed";
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_pcie0_reg>;
56 regulator-name = "MPCIE_3V3";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
63 reg_usdhc2_vmmc: regulator-usdhc2 {
64 compatible = "regulator-fixed";
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
67 regulator-name = "VSD_3V3";
68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <3300000>;
70 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
71 off-on-delay-us = <20000>;
75 reg_vddext_3v3: regulator-vddext-3v3 {
76 compatible = "regulator-fixed";
77 regulator-name = "VDDEXT_3V3";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
82 backlight: backlight {
83 compatible = "pwm-backlight";
84 pwms = <&pwm1 0 5000000 0>;
85 brightness-levels = <0 255>;
86 num-interpolated-steps = <255>;
87 default-brightness-level = <250>;
91 compatible = "gpio-ir-receiver";
92 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_ir>;
95 linux,autosuspend-period = <125>;
98 audio_codec_bt_sco: audio-codec-bt-sco {
99 compatible = "linux,bt-sco";
100 #sound-dai-cells = <1>;
103 wm8524: audio-codec {
104 #sound-dai-cells = <0>;
105 compatible = "wlf,wm8524";
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_gpio_wlf>;
108 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
112 compatible = "simple-audio-card";
113 simple-audio-card,name = "bt-sco-audio";
114 simple-audio-card,format = "dsp_a";
115 simple-audio-card,bitclock-inversion;
116 simple-audio-card,frame-master = <&btcpu>;
117 simple-audio-card,bitclock-master = <&btcpu>;
119 btcpu: simple-audio-card,cpu {
121 dai-tdm-slot-num = <2>;
122 dai-tdm-slot-width = <16>;
125 simple-audio-card,codec {
126 sound-dai = <&audio_codec_bt_sco 1>;
131 compatible = "simple-audio-card";
132 simple-audio-card,name = "wm8524-audio";
133 simple-audio-card,format = "i2s";
134 simple-audio-card,frame-master = <&cpudai>;
135 simple-audio-card,bitclock-master = <&cpudai>;
136 simple-audio-card,widgets =
137 "Line", "Left Line Out Jack",
138 "Line", "Right Line Out Jack";
139 simple-audio-card,routing =
140 "Left Line Out Jack", "LINEVOUTL",
141 "Right Line Out Jack", "LINEVOUTR";
143 cpudai: simple-audio-card,cpu {
145 dai-tdm-slot-num = <2>;
146 dai-tdm-slot-width = <32>;
149 simple-audio-card,codec {
150 sound-dai = <&wm8524>;
151 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
157 cpu-supply = <&buck2_reg>;
161 cpu-supply = <&buck2_reg>;
165 cpu-supply = <&buck2_reg>;
169 cpu-supply = <&buck2_reg>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_fec1>;
175 phy-mode = "rgmii-id";
176 phy-handle = <ðphy0>;
181 #address-cells = <1>;
184 ethphy0: ethernet-phy@0 {
185 compatible = "ethernet-phy-ieee802.3-c22";
187 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
188 reset-assert-us = <10000>;
189 qca,disable-smarteee;
190 vddio-supply = <&vddio>;
192 vddio: vddio-regulator {
193 regulator-min-microvolt = <1800000>;
194 regulator-max-microvolt = <1800000>;
201 clock-frequency = <400000>;
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_i2c1>;
207 compatible = "rohm,bd71847";
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_pmic>;
211 interrupt-parent = <&gpio1>;
212 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
213 rohm,reset-snvs-powered;
217 clock-output-names = "clk-32k-out";
221 regulator-name = "buck1";
222 regulator-min-microvolt = <700000>;
223 regulator-max-microvolt = <1300000>;
226 regulator-ramp-delay = <1250>;
230 regulator-name = "buck2";
231 regulator-min-microvolt = <700000>;
232 regulator-max-microvolt = <1300000>;
235 regulator-ramp-delay = <1250>;
236 rohm,dvs-run-voltage = <1000000>;
237 rohm,dvs-idle-voltage = <900000>;
241 // BUCK5 in datasheet
242 regulator-name = "buck3";
243 regulator-min-microvolt = <700000>;
244 regulator-max-microvolt = <1350000>;
250 // BUCK6 in datasheet
251 regulator-name = "buck4";
252 regulator-min-microvolt = <3000000>;
253 regulator-max-microvolt = <3300000>;
259 // BUCK7 in datasheet
260 regulator-name = "buck5";
261 regulator-min-microvolt = <1605000>;
262 regulator-max-microvolt = <1995000>;
268 // BUCK8 in datasheet
269 regulator-name = "buck6";
270 regulator-min-microvolt = <800000>;
271 regulator-max-microvolt = <1400000>;
277 regulator-name = "ldo1";
278 regulator-min-microvolt = <1600000>;
279 regulator-max-microvolt = <3300000>;
285 regulator-name = "ldo2";
286 regulator-min-microvolt = <800000>;
287 regulator-max-microvolt = <900000>;
293 regulator-name = "ldo3";
294 regulator-min-microvolt = <1800000>;
295 regulator-max-microvolt = <3300000>;
301 regulator-name = "ldo4";
302 regulator-min-microvolt = <900000>;
303 regulator-max-microvolt = <1800000>;
309 regulator-name = "ldo6";
310 regulator-min-microvolt = <900000>;
311 regulator-max-microvolt = <1800000>;
320 clock-frequency = <400000>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_i2c2>;
326 compatible = "adi,adv7535";
328 interrupt-parent = <&gpio1>;
329 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
331 avdd-supply = <&buck5_reg>;
332 dvdd-supply = <&buck5_reg>;
333 pvdd-supply = <&buck5_reg>;
334 a2vdd-supply = <&buck5_reg>;
335 v3p3-supply = <®_vddext_3v3>;
336 v1p2-supply = <&buck5_reg>;
339 #address-cells = <1>;
345 adv7535_in: endpoint {
346 remote-endpoint = <&dsi_out>;
353 adv7535_out: endpoint {
354 remote-endpoint = <&hdmi_connector_in>;
362 compatible = "nxp,ptn5110";
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_typec1>;
366 interrupt-parent = <&gpio2>;
371 typec1_dr_sw: endpoint {
372 remote-endpoint = <&usb1_drd_sw>;
376 typec1_con: connector {
377 compatible = "usb-c-connector";
381 try-power-role = "sink";
382 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
383 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
384 PDO_VAR(5000, 20000, 3000)>;
385 op-sink-microwatt = <15000000>;
397 clock-frequency = <400000>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_i2c3>;
403 compatible = "nxp,pca6416";
407 vcc-supply = <&buck4_reg>;
411 compatible = "ovti,ov5640";
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_camera>;
415 clocks = <&clk IMX8MM_CLK_CLKO1>;
416 clock-names = "xclk";
417 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
418 assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
419 assigned-clock-rates = <24000000>;
420 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
421 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
424 ov5640_to_mipi_csi2: endpoint {
425 remote-endpoint = <&imx8mm_mipi_csi_in>;
442 imx8mm_mipi_csi_in: endpoint {
443 remote-endpoint = <&ov5640_to_mipi_csi2>;
451 samsung,esc-clock-frequency = <10000000>;
459 remote-endpoint = <&adv7535_in>;
460 data-lanes = <1 2 3 4>;
467 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
468 fsl,tx-deemph-gen1 = <0x2d>;
469 fsl,tx-deemph-gen2 = <0xf>;
470 clocks = <&pcie0_refclk>;
475 pinctrl-names = "default";
476 pinctrl-0 = <&pinctrl_pcie0>;
477 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
478 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
479 <&clk IMX8MM_CLK_PCIE1_AUX>;
480 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
481 <&clk IMX8MM_CLK_PCIE1_CTRL>;
482 assigned-clock-rates = <10000000>, <250000000>;
483 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
484 <&clk IMX8MM_SYS_PLL2_250M>;
485 vpcie-supply = <®_pcie0>;
490 #sound-dai-cells = <0>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&pinctrl_sai2>;
493 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
494 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
495 assigned-clock-rates = <24576000>;
500 pinctrl-names = "default";
501 pinctrl-0 = <&pinctrl_sai3>;
502 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
503 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
504 assigned-clock-rates = <24576000>;
512 &uart2 { /* console */
513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_uart2>;
528 disable-over-current;
529 samsung,picophy-pre-emp-curr-control = <3>;
530 samsung,picophy-dc-vol-level-adjust = <7>;
534 usb1_drd_sw: endpoint {
535 remote-endpoint = <&typec1_dr_sw>;
541 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
542 assigned-clock-rates = <200000000>;
543 pinctrl-names = "default", "state_100mhz", "state_200mhz";
544 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
545 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
546 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
547 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
549 vmmc-supply = <®_usdhc2_vmmc>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&pinctrl_wdog>;
556 fsl,ext-reset-output;
561 pinctrl-names = "default";
562 pinctrl-0 = <&pinctrl_backlight>;
567 pinctrl_fec1: fec1grp {
569 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
570 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
571 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
572 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
573 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
574 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
575 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
576 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
577 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
578 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
579 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
580 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
581 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
582 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
583 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
587 pinctrl_gpio_led: gpioledgrp {
589 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
595 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
599 pinctrl_gpio_wlf: gpiowlfgrp {
601 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
605 pinctrl_i2c1: i2c1grp {
607 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
608 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
612 pinctrl_i2c2: i2c2grp {
614 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
615 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
619 pinctrl_i2c3: i2c3grp {
621 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
622 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
626 pinctrl_pcie0: pcie0grp {
628 MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
629 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
633 pinctrl_pcie0_reg: pcie0reggrp {
635 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
639 pinctrl_pmic: pmicirqgrp {
641 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
645 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
647 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
651 pinctrl_sai2: sai2grp {
653 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
654 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
655 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
656 MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
660 pinctrl_sai3: sai3grp {
662 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
663 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
664 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
665 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
669 pinctrl_typec1: typec1grp {
671 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
675 pinctrl_uart2: uart2grp {
677 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
678 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
682 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
684 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
688 pinctrl_usdhc2: usdhc2grp {
690 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
691 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
692 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
693 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
694 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
695 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
696 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
700 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
702 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
703 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
704 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
705 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
706 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
707 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
708 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
712 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
714 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
715 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
716 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
717 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
718 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
719 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
720 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
724 pinctrl_wdog: wdoggrp {
726 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
730 pinctrl_backlight: backlightgrp {
732 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
736 pinctrl_camera: cameragrp {
738 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
739 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
740 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59