1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2022 Marek Vasut <marex@denx.de>
8 #include <dt-bindings/net/qca-ar803x.h>
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include "imx8mm.dtsi"
13 model = "Data Modul i.MX8M Mini eDM SBC";
14 compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm";
26 device_type = "memory";
27 /* There are 1/2/4 GiB options, adjusted by bootloader. */
28 reg = <0x0 0x40000000 0 0x40000000>;
31 backlight: backlight {
32 compatible = "pwm-backlight";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_panel_backlight>;
35 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
36 default-brightness-level = <7>;
37 enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
38 pwms = <&pwm1 0 5000000 0>;
39 /* Disabled by default, unless display board plugged in. */
43 clk_xtal25: clk-xtal25 {
44 compatible = "fixed-clock";
46 clock-frequency = <25000000>;
49 clk_xtal32k: clk-xtal32k {
50 compatible = "fixed-clock";
52 clock-frequency = <32768>;
56 backlight = <&backlight>;
57 power-supply = <®_panel_vcc>;
58 /* Disabled by default, unless display board plugged in. */
62 reg_panel_vcc: regulator-panel-vcc {
63 compatible = "regulator-fixed";
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_panel_vcc_reg>;
66 regulator-name = "PANEL_VCC";
67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>;
71 /* Disabled by default, unless display board plugged in. */
75 reg_usdhc2_vcc: regulator-usdhc2-vcc {
76 compatible = "regulator-fixed";
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>;
79 regulator-name = "V_3V3_SD";
80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>;
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_watchdog_gpio>;
90 compatible = "linux,wdt-gpio";
92 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
94 /* Reset triggers in 2..3 seconds */
95 hw_margin_ms = <1500>;
96 /* Disabled by default */
102 cpu-supply = <&buck2_reg>;
106 cpu-supply = <&buck2_reg>;
110 cpu-supply = <&buck2_reg>;
114 cpu-supply = <&buck2_reg>;
118 operating-points-v2 = <&ddrc_opp_table>;
120 ddrc_opp_table: opp-table {
121 compatible = "operating-points-v2";
124 opp-hz = /bits/ 64 <25000000>;
128 opp-hz = /bits/ 64 <100000000>;
132 opp-hz = /bits/ 64 <750000000>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_ecspi1>;
140 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
143 flash@0 { /* W25Q128FVSI */
144 compatible = "jedec,spi-nor";
146 spi-max-frequency = <50000000>;
151 &ecspi2 { /* Feature connector SPI */
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_ecspi2>;
154 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
155 /* Disabled by default, unless feature board plugged in. */
159 &ecspi3 { /* Display connector SPI */
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_ecspi3>;
162 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
163 /* Disabled by default, unless display board plugged in. */
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_fec1>;
170 phy-mode = "rgmii-id";
171 phy-handle = <&fec1_phy>;
172 phy-supply = <&buck4_reg>;
177 #address-cells = <1>;
180 /* Atheros AR8031 PHY */
181 fec1_phy: ethernet-phy@0 {
182 compatible = "ethernet-phy-ieee802.3-c22";
185 * Dedicated ENET_WOL# signal is unused, the PHY
186 * can wake the SoC up via INT signal as well.
188 interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>;
189 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
190 reset-assert-us = <10000>;
191 reset-deassert-us = <10000>;
192 qca,keep-pll-enabled;
193 vddio-supply = <&vddio>;
195 vddio: vddio-regulator {
196 regulator-name = "VDDIO";
197 regulator-min-microvolt = <1800000>;
198 regulator-max-microvolt = <1800000>;
201 vddh: vddh-regulator {
202 regulator-name = "VDDH";
210 "", "ENET_RST#", "WDOG_B#", "PMIC_INT#",
211 "", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#",
212 "WDOG_KICK#", "M2-B_PCIE_CLKREQ#",
213 "USB1_OTG_ID_3V3", "ENET_WOL#",
214 "", "", "", "ENET_INT#",
215 "", "", "", "", "", "", "", "",
216 "", "", "", "", "", "", "", "";
221 "MEMCFG2", "MEMCFG1", "DSI_RESET_1V8#", "DSI_IRQ_1V8#",
222 "M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#",
223 "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", "GRAPHICS_PRSNT_1V8#",
224 "MEMCFG0", "WDOG_EN",
225 "M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#",
227 "", "", "", "SD2_RESET#", "", "", "", "",
228 "", "", "", "", "", "", "", "";
233 "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
234 "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
235 "CSI_PD_1V8", "CSI_RESET_1V8#", "", "",
237 "", "", "", "M2-B_WAKE_WWAN_1V8#",
238 "M2-B_RESET_1V8#", "", "", "",
239 "", "", "", "", "", "", "", "";
244 "NC0", "NC1", "BOOTCFG0", "BOOTCFG1",
245 "BOOTCFG2", "BOOTCFG3", "BOOTCFG4", "BOOTCFG5",
246 "BOOTCFG6", "BOOTCFG7", "NC10", "NC11",
247 "BOOTCFG8", "BOOTCFG9", "BOOTCFG10", "BOOTCFG11",
248 "BOOTCFG12", "BOOTCFG13", "BOOTCFG14", "BOOTCFG15",
250 "", "CAN_INT#", "CAN_RST#", "GPIO4_IO27",
251 "DIS_USB_DN2", "", "", "";
256 "", "DIS_USB_DN1", "USBHUB_RESET#", "GPIO5_IO03",
257 "GPIO5_IO04", "", "", "",
258 "", "SPI1_CS#", "", "",
259 "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
260 "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
261 "I2C4_SCL_3V3", "I2C4_SDA_3V3", "", "",
262 "", "SPI3_CS#", "", "", "", "", "", "";
266 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
267 clock-frequency = <100000>;
268 pinctrl-names = "default", "gpio";
269 pinctrl-0 = <&pinctrl_i2c1>;
270 pinctrl-1 = <&pinctrl_i2c1_gpio>;
271 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
272 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
276 compatible = "rohm,bd71847";
279 clocks = <&clk_xtal32k>;
280 clock-output-names = "clk-32k-out";
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_pmic>;
283 interrupt-parent = <&gpio1>;
284 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
285 rohm,reset-snvs-powered;
288 * i.MX 8M Mini Data Sheet for Consumer Products
289 * 3.1.3 Operating ranges
295 regulator-name = "buck1";
296 regulator-min-microvolt = <850000>;
297 regulator-max-microvolt = <850000>;
300 regulator-ramp-delay = <1250>;
305 regulator-name = "buck2";
306 regulator-min-microvolt = <850000>;
307 regulator-max-microvolt = <1050000>;
310 regulator-ramp-delay = <1250>;
311 rohm,dvs-run-voltage = <1000000>;
312 rohm,dvs-idle-voltage = <950000>;
315 /* VDD_DRAM, BUCK5 */
317 regulator-name = "buck3";
318 /* 1.5 GHz DDR bus clock */
319 regulator-min-microvolt = <900000>;
320 regulator-max-microvolt = <1000000>;
327 regulator-name = "buck4";
328 regulator-min-microvolt = <3300000>;
329 regulator-max-microvolt = <3300000>;
336 regulator-name = "buck5";
337 regulator-min-microvolt = <1800000>;
338 regulator-max-microvolt = <1800000>;
343 /* 1V1_NVCC_DRAM, BUCK8 */
345 regulator-name = "buck6";
346 regulator-min-microvolt = <1100000>;
347 regulator-max-microvolt = <1100000>;
354 regulator-name = "ldo1";
355 regulator-min-microvolt = <1800000>;
356 regulator-max-microvolt = <1800000>;
363 regulator-name = "ldo2";
364 regulator-min-microvolt = <800000>;
365 regulator-max-microvolt = <800000>;
372 regulator-name = "ldo3";
373 regulator-min-microvolt = <1800000>;
374 regulator-max-microvolt = <1800000>;
381 regulator-name = "ldo4";
382 regulator-min-microvolt = <900000>;
383 regulator-max-microvolt = <900000>;
390 regulator-name = "ldo6";
391 regulator-min-microvolt = <1200000>;
392 regulator-max-microvolt = <1200000>;
401 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
402 clock-frequency = <100000>;
403 pinctrl-names = "default", "gpio";
404 pinctrl-0 = <&pinctrl_i2c2>;
405 pinctrl-1 = <&pinctrl_i2c2_gpio>;
406 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
407 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&pinctrl_usb_hub>;
413 compatible = "microchip,usb2514bi";
415 individual-port-switching;
416 reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
421 compatible = "atmel,24c32";
427 pinctrl-names = "default";
428 pinctrl-0 = <&pinctrl_rtc>;
429 compatible = "st,m41t62";
431 interrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>;
435 compatible = "renesas,9fgv0241";
437 clocks = <&clk_xtal25>;
442 &i2c3 { /* Display connector I2C */
443 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
444 clock-frequency = <320000>;
445 pinctrl-names = "default", "gpio";
446 pinctrl-0 = <&pinctrl_i2c3>;
447 pinctrl-1 = <&pinctrl_i2c3_gpio>;
448 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
449 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
453 &i2c4 { /* Feature connector I2C */
454 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
455 clock-frequency = <320000>;
456 pinctrl-names = "default", "gpio";
457 pinctrl-0 = <&pinctrl_i2c4>;
458 pinctrl-1 = <&pinctrl_i2c4_gpio>;
459 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
460 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
467 <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
468 <&pinctrl_panel_expansion>;
470 pinctrl_ecspi1: ecspi1-grp {
472 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x44
473 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x44
474 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x44
475 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
479 pinctrl_ecspi2: ecspi2-grp {
481 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x44
482 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x44
483 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x44
484 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40
488 pinctrl_ecspi3: ecspi3-grp {
490 MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x44
491 MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x44
492 MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x44
493 MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40
497 pinctrl_fec1: fec1-grp {
499 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
500 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
501 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
502 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
503 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
504 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
505 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
506 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
507 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
508 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
509 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
510 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
511 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
512 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
514 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x6
516 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000090
518 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000090
522 pinctrl_hog_feature: hog-feature-grp {
525 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000006
527 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000006
529 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000006
532 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000090
534 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x26
538 pinctrl_hog_panel: hog-panel-grp {
540 /* GRAPHICS_GPIO0_1V8 */
541 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x26
545 pinctrl_hog_misc: hog-misc-grp {
548 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000000
550 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0
552 MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0
555 MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x0
557 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x0
560 MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x100
561 /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
562 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0
563 /* GRAPHICS_PRSNT_1V8# */
564 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x40000000
566 /* CLK_CCM_CLKO1_3V3 */
567 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x10
571 pinctrl_hog_sbc: hog-sbc-grp {
573 /* MEMCFG[0..2] straps */
574 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000140
575 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000140
576 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000140
578 /* BOOT_CFG[0..15] straps */
579 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000000
580 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000000
581 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000000
582 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000000
583 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000000
584 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000000
585 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000000
586 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x40000000
587 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000000
588 MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x40000000
589 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000000
590 MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x40000000
591 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000000
592 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000000
593 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000000
594 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x40000000
596 /* Not connected pins */
597 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x0
598 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x0
599 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x0
600 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x0
601 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x0
605 pinctrl_i2c1: i2c1-grp {
607 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000084
608 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000084
612 pinctrl_i2c1_gpio: i2c1-gpio-grp {
614 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x84
615 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x84
619 pinctrl_i2c2: i2c2-grp {
621 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000084
622 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000084
626 pinctrl_i2c2_gpio: i2c2-gpio-grp {
628 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x84
629 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x84
633 pinctrl_i2c3: i2c3-grp {
635 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000084
636 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000084
640 pinctrl_i2c3_gpio: i2c3-gpio-grp {
642 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x84
643 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x84
647 pinctrl_i2c4: i2c4-grp {
649 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000084
650 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000084
654 pinctrl_i2c4_gpio: i2c4-gpio-grp {
656 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x84
657 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x84
661 pinctrl_panel_backlight: panel-backlight-grp {
664 MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x104
668 pinctrl_panel_expansion: panel-expansion-grp {
671 MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x2
673 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x40000090
677 pinctrl_panel_vcc_reg: panel-vcc-grp {
680 MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x104
684 pinctrl_panel_pwm: panel-pwm-grp {
687 MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x12
691 pinctrl_pcie0: pcie-grp {
693 /* M2-B_RESET_1V8# */
694 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x102
696 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x2
697 /* M2-B_FULL_CARD_PWROFF_1V8# */
698 MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x102
699 /* M2-B_W_DISABLE1_WWAN_1V8# */
700 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x102
701 /* M2-B_W_DISABLE2_GPS_1V8# */
702 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x102
704 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x14
705 /* M2-B_WAKE_WWAN_1V8# */
706 MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x40000140
707 /* M2-B_PCIE_WAKE# */
708 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000140
709 /* M2-B_PCIE_CLKREQ# */
710 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000140
714 pinctrl_pmic: pmic-grp {
716 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000090
720 pinctrl_rtc: rtc-grp {
723 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000090
727 pinctrl_sai5: sai5-grp {
729 MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x100
730 MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0
731 MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x100
732 MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x100
733 MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x100
737 pinctrl_uart1: uart1-grp {
739 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x90
740 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x90
741 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x50
742 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x50
746 pinctrl_uart2: uart2-grp {
748 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x50
749 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x90
750 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x50
751 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x90
755 pinctrl_uart3: uart3-grp {
757 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
758 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
762 pinctrl_uart4: uart4-grp {
764 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x40
765 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x40
769 pinctrl_usb_hub: usb-hub-grp {
772 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x4
776 pinctrl_usb_otg1: usb-otg1-grp {
778 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000000
779 MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x4
780 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x40000090
784 pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp {
786 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x4
790 pinctrl_usdhc2: usdhc2-grp {
792 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
793 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
794 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
795 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
796 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
797 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
798 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
799 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
800 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
804 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
806 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
807 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
808 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
809 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
810 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
811 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
812 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
813 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
814 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
818 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
820 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
821 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
822 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
823 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
824 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
825 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
826 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
827 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
828 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
832 pinctrl_usdhc3: usdhc3-grp {
834 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
835 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
836 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
837 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
838 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
839 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
840 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
841 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
842 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
843 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
844 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
845 MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
849 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
851 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
852 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
853 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
854 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
855 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
856 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
857 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
858 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
859 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
860 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
861 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
862 MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
866 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
868 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
869 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
870 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
871 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
872 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
873 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
874 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
875 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
876 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
877 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
878 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
879 MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
883 pinctrl_watchdog_gpio: watchdog-gpio-grp {
886 MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x26
887 /* WDOG_EN -- ungate WDT RESET# signal propagation */
888 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x6
889 /* WDOG_KICK# / WDI */
890 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x26
896 fsl,clkreq-unsupported; /* CLKREQ_B is not connected to suitable input */
897 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
898 fsl,tx-deemph-gen1 = <0x2d>;
899 fsl,tx-deemph-gen2 = <0xf>;
900 clocks = <&pcieclk 0>;
905 pinctrl-names = "default";
906 pinctrl-0 = <&pinctrl_pcie0>;
907 reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
908 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 0>,
909 <&clk IMX8MM_CLK_PCIE1_AUX>;
910 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
911 <&clk IMX8MM_CLK_PCIE1_CTRL>;
912 assigned-clock-rates = <10000000>, <250000000>;
913 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
914 <&clk IMX8MM_SYS_PLL2_250M>;
919 pinctrl-names = "default";
920 pinctrl-0 = <&pinctrl_panel_pwm>;
921 /* Disabled by default, unless display board plugged in. */
926 pinctrl-names = "default";
927 pinctrl-0 = <&pinctrl_sai5>;
928 fsl,sai-mclk-direction-output;
929 /* Input into codec PLL */
930 assigned-clocks = <&clk IMX8MM_CLK_SAI5>;
931 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;
932 assigned-clock-rates = <22579200>;
933 /* Disabled by default, unless display board plugged in. */
942 pinctrl-names = "default";
943 pinctrl-0 = <&pinctrl_uart1>;
949 pinctrl-names = "default";
950 pinctrl-0 = <&pinctrl_uart2>;
954 &uart3 { /* A53 Debug */
955 pinctrl-names = "default";
956 pinctrl-0 = <&pinctrl_uart3>;
960 &uart4 { /* M4 Debug */
961 pinctrl-names = "default";
962 pinctrl-0 = <&pinctrl_uart4>;
963 /* UART4 is reserved for CM and RDC blocks CA access to UART4. */
968 pinctrl-names = "default";
969 pinctrl-0 = <&pinctrl_usb_otg1>;
975 disable-over-current;
980 &usdhc2 { /* MicroSD */
981 assigned-clocks = <&clk IMX8MM_CLK_USDHC2_ROOT>;
982 pinctrl-names = "default", "state_100mhz", "state_200mhz";
983 pinctrl-0 = <&pinctrl_usdhc2>;
984 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
985 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
987 vmmc-supply = <®_usdhc2_vcc>;
992 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
993 assigned-clock-rates = <400000000>;
994 pinctrl-names = "default", "state_100mhz", "state_200mhz";
995 pinctrl-0 = <&pinctrl_usdhc3>;
996 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
997 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
1000 vmmc-supply = <&buck4_reg>;
1001 vqmmc-supply = <&buck5_reg>;