arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2022 Marek Vasut <marex@denx.de>
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/net/qca-ar803x.h>
   9 #include <dt-bindings/phy/phy-imx8-pcie.h>
  10 #include "imx8mm.dtsi"
  11
  12 / {
  13         model = "Data Modul i.MX8M Mini eDM SBC";
  14         compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm";
  15
  16         aliases {
  17                 rtc0 = &rtc;
  18                 rtc1 = &snvs_rtc;
  19         };
  20
  21         chosen {
  22                 stdout-path = &uart3;
  23         };
  24
  25         memory@40000000 {
  26                 device_type = "memory";
  27                 /* There are 1/2/4 GiB options, adjusted by bootloader. */
  28                 reg = <0x0 0x40000000 0 0x40000000>;
  29         };
  30
  31         backlight: backlight {
  32                 compatible = "pwm-backlight";
  33                 pinctrl-names = "default";
  34                 pinctrl-0 = <&pinctrl_panel_backlight>;
  35                 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
  36                 default-brightness-level = <7>;
  37                 enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
  38                 pwms = <&pwm1 0 5000000 0>;
  39                 /* Disabled by default, unless display board plugged in. */
  40                 status = "disabled";
  41         };
  42
  43         clk_xtal25: clk-xtal25 {
  44                 compatible = "fixed-clock";
  45                 #clock-cells = <0>;
  46                 clock-frequency = <25000000>;
  47         };
  48
  49         panel: panel {
  50                 backlight = <&backlight>;
  51                 power-supply = <&reg_panel_vcc>;
  52                 /* Disabled by default, unless display board plugged in. */
  53                 status = "disabled";
  54         };
  55
  56         reg_panel_vcc: regulator-panel-vcc {
  57                 compatible = "regulator-fixed";
  58                 pinctrl-names = "default";
  59                 pinctrl-0 = <&pinctrl_panel_vcc_reg>;
  60                 regulator-name = "PANEL_VCC";
  61                 regulator-min-microvolt = <5000000>;
  62                 regulator-max-microvolt = <5000000>;
  63                 gpio = <&gpio3 6 0>;
  64                 enable-active-high;
  65                 /* Disabled by default, unless display board plugged in. */
  66                 status = "disabled";
  67         };
  68
  69         reg_usdhc2_vcc: regulator-usdhc2-vcc {
  70                 compatible = "regulator-fixed";
  71                 pinctrl-names = "default";
  72                 pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>;
  73                 regulator-name = "V_3V3_SD";
  74                 regulator-min-microvolt = <3300000>;
  75                 regulator-max-microvolt = <3300000>;
  76                 gpio = <&gpio2 19 0>;
  77                 enable-active-high;
  78         };
  79
  80         watchdog-gpio {
  81                 /* TPS3813 */
  82                 pinctrl-names = "default";
  83                 pinctrl-0 = <&pinctrl_watchdog_gpio>;
  84                 compatible = "linux,wdt-gpio";
  85                 always-enabled;
  86                 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
  87                 hw_algo = "level";
  88                 /* Reset triggers in 2..3 seconds */
  89                 hw_margin_ms = <1500>;
  90                 /* Disabled by default */
  91                 status = "disabled";
  92         };
  93 };
  94
  95 &A53_0 {
  96         cpu-supply = <&buck2_reg>;
  97 };
  98
  99 &A53_1 {
 100         cpu-supply = <&buck2_reg>;
 101 };
 102
 103 &A53_2 {
 104         cpu-supply = <&buck2_reg>;
 105 };
 106
 107 &A53_3 {
 108         cpu-supply = <&buck2_reg>;
 109 };
 110
 111 &ddrc {
 112         operating-points-v2 = <&ddrc_opp_table>;
 113
 114         ddrc_opp_table: opp-table {
 115                 compatible = "operating-points-v2";
 116
 117                 opp-25M {
 118                         opp-hz = /bits/ 64 <25000000>;
 119                 };
 120
 121                 opp-100M {
 122                         opp-hz = /bits/ 64 <100000000>;
 123                 };
 124
 125                 opp-750M {
 126                         opp-hz = /bits/ 64 <750000000>;
 127                 };
 128         };
 129 };
 130
 131 &ecspi1 {
 132         pinctrl-names = "default";
 133         pinctrl-0 = <&pinctrl_ecspi1>;
 134         cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 135         status = "okay";
 136
 137         flash@0 {       /* W25Q128FVSI */
 138                 compatible = "jedec,spi-nor";
 139                 m25p,fast-read;
 140                 spi-max-frequency = <50000000>;
 141                 reg = <0>;
 142         };
 143 };
 144
 145 &ecspi2 {       /* Feature connector SPI */
 146         pinctrl-names = "default";
 147         pinctrl-0 = <&pinctrl_ecspi2>;
 148         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 149         /* Disabled by default, unless feature board plugged in. */
 150         status = "disabled";
 151 };
 152
 153 &ecspi3 {       /* Display connector SPI */
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&pinctrl_ecspi3>;
 156         cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
 157         /* Disabled by default, unless display board plugged in. */
 158         status = "disabled";
 159 };
 160
 161 &fec1 {
 162         pinctrl-names = "default";
 163         pinctrl-0 = <&pinctrl_fec1>;
 164         phy-mode = "rgmii-id";
 165         phy-handle = <&fec1_phy>;
 166         phy-supply = <&buck4_reg>;
 167         fsl,magic-packet;
 168         status = "okay";
 169
 170         mdio {
 171                 #address-cells = <1>;
 172                 #size-cells = <0>;
 173
 174                 /* Atheros AR8031 PHY */
 175                 fec1_phy: ethernet-phy@0 {
 176                         compatible = "ethernet-phy-ieee802.3-c22";
 177                         reg = <0>;
 178                         /*
 179                          * Dedicated ENET_WOL# signal is unused, the PHY
 180                          * can wake the SoC up via INT signal as well.
 181                          */
 182                         interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>;
 183                         reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 184                         reset-assert-us = <10000>;
 185                         reset-deassert-us = <10000>;
 186                         qca,clk-out-frequency = <125000000>;
 187                         qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
 188                         qca,keep-pll-enabled;
 189                         vddio-supply = <&vddio>;
 190
 191                         vddio: vddio-regulator {
 192                                 regulator-name = "VDDIO";
 193                                 regulator-min-microvolt = <1800000>;
 194                                 regulator-max-microvolt = <1800000>;
 195                         };
 196
 197                         vddh: vddh-regulator {
 198                                 regulator-name = "VDDH";
 199                         };
 200                 };
 201         };
 202 };
 203
 204 &gpio1 {
 205         gpio-line-names =
 206                 "", "ENET_RST#", "WDOG_B#", "PMIC_INT#",
 207                 "", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#",
 208                 "WDOG_KICK#", "M2-B_PCIE_CLKREQ#",
 209                 "USB1_OTG_ID_3V3", "ENET_WOL#",
 210                 "", "", "", "ENET_INT#",
 211                 "", "", "", "", "", "", "", "",
 212                 "", "", "", "", "", "", "", "";
 213 };
 214
 215 &gpio2 {
 216         gpio-line-names =
 217                 "MEMCFG2", "MEMCFG1", "DSI_RESET_1V8#", "DSI_IRQ_1V8#",
 218                 "M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#",
 219                 "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", "GRAPHICS_PRSNT_1V8#",
 220                 "MEMCFG0", "WDOG_EN",
 221                 "M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#",
 222                 "", "", "", "",
 223                 "", "", "", "SD2_RESET#", "", "", "", "",
 224                 "", "", "", "", "", "", "", "";
 225 };
 226
 227 &gpio3 {
 228         gpio-line-names =
 229                 "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
 230                 "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
 231                 "CSI_PD_1V8", "CSI_RESET_1V8#", "", "",
 232                 "", "", "", "",
 233                 "", "", "", "M2-B_WAKE_WWAN_1V8#",
 234                 "M2-B_RESET_1V8#", "", "", "",
 235                 "", "", "", "", "", "", "", "";
 236 };
 237
 238 &gpio4 {
 239         gpio-line-names =
 240                 "NC0", "NC1", "BOOTCFG0", "BOOTCFG1",
 241                 "BOOTCFG2", "BOOTCFG3", "BOOTCFG4", "BOOTCFG5",
 242                 "BOOTCFG6", "BOOTCFG7", "NC10", "NC11",
 243                 "BOOTCFG8", "BOOTCFG9", "BOOTCFG10", "BOOTCFG11",
 244                 "BOOTCFG12", "BOOTCFG13", "BOOTCFG14", "BOOTCFG15",
 245                 "NC20", "", "", "",
 246                 "", "CAN_INT#", "CAN_RST#", "GPIO4_IO27",
 247                 "DIS_USB_DN2", "", "", "";
 248 };
 249
 250 &gpio5 {
 251         gpio-line-names =
 252                 "", "DIS_USB_DN1", "USBHUB_RESET#", "GPIO5_IO03",
 253                 "GPIO5_IO04", "", "", "",
 254                 "", "SPI1_CS#", "", "",
 255                 "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
 256                 "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
 257                 "I2C4_SCL_3V3", "I2C4_SDA_3V3", "", "",
 258                 "", "SPI3_CS#", "", "", "", "", "", "";
 259 };
 260
 261 &i2c1 {
 262         /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
 263         clock-frequency = <100000>;
 264         pinctrl-names = "default", "gpio";
 265         pinctrl-0 = <&pinctrl_i2c1>;
 266         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 267         scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 268         sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 269         status = "okay";
 270
 271         pmic: pmic@4b {
 272                 compatible = "rohm,bd71847";
 273                 reg = <0x4b>;
 274                 pinctrl-names = "default";
 275                 pinctrl-0 = <&pinctrl_pmic>;
 276                 interrupt-parent = <&gpio1>;
 277                 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
 278                 rohm,reset-snvs-powered;
 279
 280                 /*
 281                  * i.MX 8M Mini Data Sheet for Consumer Products
 282                  * 3.1.3 Operating ranges
 283                  * MIMX8MM4DVTLZAA
 284                  */
 285                 regulators {
 286                         /* VDD_SOC */
 287                         buck1_reg: BUCK1 {
 288                                 regulator-name = "buck1";
 289                                 regulator-min-microvolt = <850000>;
 290                                 regulator-max-microvolt = <850000>;
 291                                 regulator-boot-on;
 292                                 regulator-always-on;
 293                                 regulator-ramp-delay = <1250>;
 294                         };
 295
 296                         /* VDD_ARM */
 297                         buck2_reg: BUCK2 {
 298                                 regulator-name = "buck2";
 299                                 regulator-min-microvolt = <850000>;
 300                                 regulator-max-microvolt = <1050000>;
 301                                 regulator-boot-on;
 302                                 regulator-always-on;
 303                                 regulator-ramp-delay = <1250>;
 304                                 rohm,dvs-run-voltage = <1000000>;
 305                                 rohm,dvs-idle-voltage = <950000>;
 306                         };
 307
 308                         /* VDD_DRAM, BUCK5 */
 309                         buck3_reg: BUCK3 {
 310                                 regulator-name = "buck3";
 311                                 /* 1.5 GHz DDR bus clock */
 312                                 regulator-min-microvolt = <900000>;
 313                                 regulator-max-microvolt = <1000000>;
 314                                 regulator-boot-on;
 315                                 regulator-always-on;
 316                         };
 317
 318                         /* 3V3_VDD, BUCK6 */
 319                         buck4_reg: BUCK4 {
 320                                 regulator-name = "buck4";
 321                                 regulator-min-microvolt = <3300000>;
 322                                 regulator-max-microvolt = <3300000>;
 323                                 regulator-boot-on;
 324                                 regulator-always-on;
 325                         };
 326
 327                         /* 1V8_VDD, BUCK7 */
 328                         buck5_reg: BUCK5 {
 329                                 regulator-name = "buck5";
 330                                 regulator-min-microvolt = <1800000>;
 331                                 regulator-max-microvolt = <1800000>;
 332                                 regulator-boot-on;
 333                                 regulator-always-on;
 334                         };
 335
 336                         /* 1V1_NVCC_DRAM, BUCK8 */
 337                         buck6_reg: BUCK6 {
 338                                 regulator-name = "buck6";
 339                                 regulator-min-microvolt = <1100000>;
 340                                 regulator-max-microvolt = <1100000>;
 341                                 regulator-boot-on;
 342                                 regulator-always-on;
 343                         };
 344
 345                         /* 1V8_NVCC_SNVS */
 346                         ldo1_reg: LDO1 {
 347                                 regulator-name = "ldo1";
 348                                 regulator-min-microvolt = <1800000>;
 349                                 regulator-max-microvolt = <1800000>;
 350                                 regulator-boot-on;
 351                                 regulator-always-on;
 352                         };
 353
 354                         /* 0V8_VDD_SNVS */
 355                         ldo2_reg: LDO2 {
 356                                 regulator-name = "ldo2";
 357                                 regulator-min-microvolt = <800000>;
 358                                 regulator-max-microvolt = <800000>;
 359                                 regulator-boot-on;
 360                                 regulator-always-on;
 361                         };
 362
 363                         /* 1V8_VDDA */
 364                         ldo3_reg: LDO3 {
 365                                 regulator-name = "ldo3";
 366                                 regulator-min-microvolt = <1800000>;
 367                                 regulator-max-microvolt = <1800000>;
 368                                 regulator-boot-on;
 369                                 regulator-always-on;
 370                         };
 371
 372                         /* 0V9_VDD_PHY */
 373                         ldo4_reg: LDO4 {
 374                                 regulator-name = "ldo4";
 375                                 regulator-min-microvolt = <900000>;
 376                                 regulator-max-microvolt = <900000>;
 377                                 regulator-boot-on;
 378                                 regulator-always-on;
 379                         };
 380
 381                         /* 1V2_VDD_PHY */
 382                         ldo6_reg: LDO6 {
 383                                 regulator-name = "ldo6";
 384                                 regulator-min-microvolt = <1200000>;
 385                                 regulator-max-microvolt = <1200000>;
 386                                 regulator-boot-on;
 387                                 regulator-always-on;
 388                         };
 389                 };
 390         };
 391 };
 392
 393 &i2c2 {
 394         /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
 395         clock-frequency = <100000>;
 396         pinctrl-names = "default", "gpio";
 397         pinctrl-0 = <&pinctrl_i2c2>;
 398         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 399         scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 400         sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 401         status = "okay";
 402
 403         usb-hub@2c {
 404                 pinctrl-names = "default";
 405                 pinctrl-0 = <&pinctrl_usb_hub>;
 406                 compatible = "microchip,usb2514bi";
 407                 reg = <0x2c>;
 408                 individual-port-switching;
 409                 reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
 410                 self-powered;
 411         };
 412
 413         eeprom: eeprom@50 {
 414                 compatible = "atmel,24c32";
 415                 reg = <0x50>;
 416                 pagesize = <32>;
 417         };
 418
 419         rtc: rtc@68 {
 420                 pinctrl-names = "default";
 421                 pinctrl-0 = <&pinctrl_rtc>;
 422                 compatible = "st,m41t62";
 423                 reg = <0x68>;
 424                 interrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>;
 425         };
 426
 427         pcieclk: clk@6a {
 428                 compatible = "renesas,9fgv0241";
 429                 reg = <0x6a>;
 430                 clocks = <&clk_xtal25>;
 431                 #clock-cells = <1>;
 432         };
 433 };
 434
 435 &i2c3 { /* Display connector I2C */
 436         /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
 437         clock-frequency = <320000>;
 438         pinctrl-names = "default", "gpio";
 439         pinctrl-0 = <&pinctrl_i2c3>;
 440         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 441         scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 442         sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 443         status = "okay";
 444 };
 445
 446 &i2c4 { /* Feature connector I2C */
 447         /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
 448         clock-frequency = <320000>;
 449         pinctrl-names = "default", "gpio";
 450         pinctrl-0 = <&pinctrl_i2c4>;
 451         pinctrl-1 = <&pinctrl_i2c4_gpio>;
 452         scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 453         sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 454         status = "okay";
 455 };
 456
 457 &iomuxc {
 458         pinctrl-names = "default";
 459         pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
 460                     <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
 461                     <&pinctrl_panel_expansion>;
 462
 463         pinctrl_ecspi1: ecspi1-grp {
 464                 fsl,pins = <
 465                         MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK            0x44
 466                         MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI            0x44
 467                         MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO            0x44
 468                         MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9               0x40
 469                 >;
 470         };
 471
 472         pinctrl_ecspi2: ecspi2-grp {
 473                 fsl,pins = <
 474                         MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK            0x44
 475                         MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI            0x44
 476                         MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO            0x44
 477                         MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13              0x40
 478                 >;
 479         };
 480
 481         pinctrl_ecspi3: ecspi3-grp {
 482                 fsl,pins = <
 483                         MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK              0x44
 484                         MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI              0x44
 485                         MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO              0x44
 486                         MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25               0x40
 487                 >;
 488         };
 489
 490         pinctrl_fec1: fec1-grp {
 491                 fsl,pins = <
 492                         MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 493                         MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 494                         MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 495                         MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 496                         MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 497                         MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 498                         MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 499                         MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 500                         MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 501                         MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 502                         MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 503                         MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 504                         MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 505                         MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 506                         /* ENET_RST# */
 507                         MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1               0x6
 508                         /* ENET_WOL# */
 509                         MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11              0x40000090
 510                         /* ENET_INT# */
 511                         MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15              0x40000090
 512                 >;
 513         };
 514
 515         pinctrl_hog_feature: hog-feature-grp {
 516                 fsl,pins = <
 517                         /* GPIO4_IO27 */
 518                         MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27               0x40000006
 519                         /* GPIO5_IO03 */
 520                         MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3                 0x40000006
 521                         /* GPIO5_IO04 */
 522                         MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4                 0x40000006
 523
 524                         /* CAN_INT# */
 525                         MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25                0x40000090
 526                         /* CAN_RST# */
 527                         MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26               0x26
 528                 >;
 529         };
 530
 531         pinctrl_hog_panel: hog-panel-grp {
 532                 fsl,pins = <
 533                         /* GRAPHICS_GPIO0_1V8 */
 534                         MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7              0x26
 535                 >;
 536         };
 537
 538         pinctrl_hog_misc: hog-misc-grp {
 539                 fsl,pins = <
 540                         /* PG_V_IN_VAR# */
 541                         MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1               0x40000000
 542                         /* CSI_PD_1V8 */
 543                         MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8              0x0
 544                         /* CSI_RESET_1V8# */
 545                         MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9              0x0
 546
 547                         /* DIS_USB_DN1 */
 548                         MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1                 0x0
 549                         /* DIS_USB_DN2 */
 550                         MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28               0x0
 551
 552                         /* EEPROM_WP_1V8# */
 553                         MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5                0x100
 554                         /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
 555                         MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6                0x0
 556                         /* GRAPHICS_PRSNT_1V8# */
 557                         MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7                0x40000000
 558
 559                         /* CLK_CCM_CLKO1_3V3 */
 560                         MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1      0x10
 561                 >;
 562         };
 563
 564         pinctrl_hog_sbc: hog-sbc-grp {
 565                 fsl,pins = <
 566                         /* MEMCFG[0..2] straps */
 567                         MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8                0x40000140
 568                         MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1                  0x40000140
 569                         MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0                  0x40000140
 570
 571                         /* BOOT_CFG[0..15] straps */
 572                         MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2                0x40000000
 573                         MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3                0x40000000
 574                         MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4                0x40000000
 575                         MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5                0x40000000
 576                         MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6                0x40000000
 577                         MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7                0x40000000
 578                         MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8                0x40000000
 579                         MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9                0x40000000
 580                         MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12               0x40000000
 581                         MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13               0x40000000
 582                         MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14               0x40000000
 583                         MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15               0x40000000
 584                         MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16               0x40000000
 585                         MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17               0x40000000
 586                         MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18               0x40000000
 587                         MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19               0x40000000
 588
 589                         /* Not connected pins */
 590                         MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20               0x0
 591                         MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10               0x0
 592                         MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11                0x0
 593                         MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0                0x0
 594                         MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1                 0x0
 595                 >;
 596         };
 597
 598         pinctrl_i2c1: i2c1-grp {
 599                 fsl,pins = <
 600                         MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL                  0x40000084
 601                         MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA                  0x40000084
 602                 >;
 603         };
 604
 605         pinctrl_i2c1_gpio: i2c1-gpio-grp {
 606                 fsl,pins = <
 607                         MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14                0x84
 608                         MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15                0x84
 609                 >;
 610         };
 611
 612         pinctrl_i2c2: i2c2-grp {
 613                 fsl,pins = <
 614                         MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL                  0x40000084
 615                         MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA                  0x40000084
 616                 >;
 617         };
 618
 619         pinctrl_i2c2_gpio: i2c2-gpio-grp {
 620                 fsl,pins = <
 621                         MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16                0x84
 622                         MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17                0x84
 623                 >;
 624         };
 625
 626         pinctrl_i2c3: i2c3-grp {
 627                 fsl,pins = <
 628                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL                  0x40000084
 629                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA                  0x40000084
 630                 >;
 631         };
 632
 633         pinctrl_i2c3_gpio: i2c3-gpio-grp {
 634                 fsl,pins = <
 635                         MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18                0x84
 636                         MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19                0x84
 637                 >;
 638         };
 639
 640         pinctrl_i2c4: i2c4-grp {
 641                 fsl,pins = <
 642                         MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL                  0x40000084
 643                         MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA                  0x40000084
 644                 >;
 645         };
 646
 647         pinctrl_i2c4_gpio: i2c4-gpio-grp {
 648                 fsl,pins = <
 649                         MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20                0x84
 650                         MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21                0x84
 651                 >;
 652         };
 653
 654         pinctrl_panel_backlight: panel-backlight-grp {
 655                 fsl,pins = <
 656                         /* BL_ENABLE_1V8 */
 657                         MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0                 0x104
 658                 >;
 659         };
 660
 661         pinctrl_panel_expansion: panel-expansion-grp {
 662                 fsl,pins = <
 663                         /* DSI_RESET_1V8# */
 664                         MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2                0x2
 665                         /* DSI_IRQ_1V8# */
 666                         MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3                0x40000090
 667                 >;
 668         };
 669
 670         pinctrl_panel_vcc_reg: panel-vcc-grp {
 671                 fsl,pins = <
 672                         /* TFT_ENABLE_1V8 */
 673                         MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6              0x104
 674                 >;
 675         };
 676
 677         pinctrl_panel_pwm: panel-pwm-grp {
 678                 fsl,pins = <
 679                         /* BL_PWM_3V3 */
 680                         MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT             0x12
 681                 >;
 682         };
 683
 684         pinctrl_pcie0: pcie-grp {
 685                 fsl,pins = <
 686                         /* M2-B_RESET_1V8# */
 687                         MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20                0x102
 688                         /* M2-B_PCIE_RST# */
 689                         MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5               0x2
 690                         /* M2-B_FULL_CARD_PWROFF_1V8# */
 691                         MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4                0x102
 692                         /* M2-B_W_DISABLE1_WWAN_1V8# */
 693                         MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10             0x102
 694                         /* M2-B_W_DISABLE2_GPS_1V8# */
 695                         MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11              0x102
 696                         /* CLK_M2_32K768 */
 697                         MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K      0x14
 698                         /* M2-B_WAKE_WWAN_1V8# */
 699                         MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19               0x40000140
 700                         /* M2-B_PCIE_WAKE# */
 701                         MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6               0x40000140
 702                         /* M2-B_PCIE_CLKREQ# */
 703                         MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x40000140
 704                 >;
 705         };
 706
 707         pinctrl_pmic: pmic-grp {
 708                 fsl,pins = <
 709                         MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x40000090
 710                 >;
 711         };
 712
 713         pinctrl_rtc: rtc-grp {
 714                 fsl,pins = <
 715                         /* RTC_IRQ# */
 716                         MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7               0x40000090
 717                 >;
 718         };
 719
 720         pinctrl_sai5: sai5-grp {
 721                 fsl,pins = <
 722                         MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK                0x100
 723                         MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0            0x0
 724                         MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC             0x100
 725                         MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK             0x100
 726                         MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0            0x100
 727                 >;
 728         };
 729
 730         pinctrl_uart1: uart1-grp {
 731                 fsl,pins = <
 732                         MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX              0x90
 733                         MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B          0x90
 734                         MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX             0x50
 735                         MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B          0x50
 736                 >;
 737         };
 738
 739         pinctrl_uart2: uart2-grp {
 740                 fsl,pins = <
 741                         MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B           0x50
 742                         MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B           0x90
 743                         MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX              0x50
 744                         MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX             0x90
 745                 >;
 746         };
 747
 748         pinctrl_uart3: uart3-grp {
 749                 fsl,pins = <
 750                         MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX             0x40
 751                         MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX             0x40
 752                 >;
 753         };
 754
 755         pinctrl_uart4: uart4-grp {
 756                 fsl,pins = <
 757                         MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX             0x40
 758                         MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX             0x40
 759                 >;
 760         };
 761
 762         pinctrl_usb_hub: usb-hub-grp {
 763                 fsl,pins = <
 764                         /* USBHUB_RESET# */
 765                         MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2                0x4
 766                 >;
 767         };
 768
 769         pinctrl_usb_otg1: usb-otg1-grp {
 770                 fsl,pins = <
 771                         MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10              0x40000000
 772                         MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR            0x4
 773                         MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC             0x40000090
 774                 >;
 775         };
 776
 777         pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp {
 778                 fsl,pins = <
 779                         MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19             0x4
 780                 >;
 781         };
 782
 783         pinctrl_usdhc2: usdhc2-grp {
 784                 fsl,pins = <
 785                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x190
 786                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d0
 787                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d0
 788                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d0
 789                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d0
 790                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d0
 791                         MX8MM_IOMUXC_SD2_WP_USDHC2_WP                   0x400000d6
 792                         MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B               0x0d6
 793                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x1d0
 794                 >;
 795         };
 796
 797         pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
 798                 fsl,pins = <
 799                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x194
 800                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d4
 801                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d4
 802                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d4
 803                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d4
 804                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d4
 805                         MX8MM_IOMUXC_SD2_WP_USDHC2_WP                   0x400000d6
 806                         MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B               0x0d6
 807                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x1d0
 808                 >;
 809         };
 810
 811         pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
 812                 fsl,pins = <
 813                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x196
 814                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d6
 815                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d6
 816                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d6
 817                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d6
 818                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d6
 819                         MX8MM_IOMUXC_SD2_WP_USDHC2_WP                   0x400000d6
 820                         MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B               0x0d6
 821                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x1d0
 822                 >;
 823         };
 824
 825         pinctrl_usdhc3: usdhc3-grp {
 826                 fsl,pins = <
 827                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
 828                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
 829                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
 830                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
 831                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
 832                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
 833                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
 834                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
 835                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
 836                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
 837                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
 838                         MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B           0x40
 839                 >;
 840         };
 841
 842         pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
 843                 fsl,pins = <
 844                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
 845                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
 846                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
 847                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
 848                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
 849                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
 850                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
 851                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
 852                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
 853                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
 854                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
 855                         MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B           0x40
 856                 >;
 857         };
 858
 859         pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
 860                 fsl,pins = <
 861                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
 862                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
 863                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
 864                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
 865                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
 866                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
 867                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
 868                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
 869                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
 870                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
 871                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
 872                         MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B           0x40
 873                 >;
 874         };
 875
 876         pinctrl_watchdog_gpio: watchdog-gpio-grp {
 877                 fsl,pins = <
 878                         /* WDOG_B# */
 879                         MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2               0x26
 880                         /* WDOG_EN -- ungate WDT RESET# signal propagation */
 881                         MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9                0x6
 882                         /* WDOG_KICK# / WDI */
 883                         MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8               0x26
 884                 >;
 885         };
 886 };
 887
 888 &pcie_phy {
 889         fsl,clkreq-unsupported; /* CLKREQ_B is not connected to suitable input */
 890         fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
 891         fsl,tx-deemph-gen1 = <0x2d>;
 892         fsl,tx-deemph-gen2 = <0xf>;
 893         clocks = <&pcieclk 0>;
 894         status = "okay";
 895 };
 896
 897 &pcie0 {
 898         pinctrl-names = "default";
 899         pinctrl-0 = <&pinctrl_pcie0>;
 900         reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
 901         clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
 902                  <&pcieclk 0>;
 903         clock-names = "pcie", "pcie_aux", "pcie_bus";
 904         assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 905                           <&clk IMX8MM_CLK_PCIE1_CTRL>;
 906         assigned-clock-rates = <10000000>, <250000000>;
 907         assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 908                                  <&clk IMX8MM_SYS_PLL2_250M>;
 909         status = "okay";
 910 };
 911
 912 &pwm1 {
 913         pinctrl-names = "default";
 914         pinctrl-0 = <&pinctrl_panel_pwm>;
 915         /* Disabled by default, unless display board plugged in. */
 916         status = "disabled";
 917 };
 918
 919 &sai5 {
 920         pinctrl-names = "default";
 921         pinctrl-0 = <&pinctrl_sai5>;
 922         fsl,sai-mclk-direction-output;
 923         /* Input into codec PLL */
 924         assigned-clocks = <&clk IMX8MM_CLK_SAI5>;
 925         assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;
 926         assigned-clock-rates = <22579200>;
 927         /* Disabled by default, unless display board plugged in. */
 928         status = "disabled";
 929 };
 930
 931 &uart1 {
 932         pinctrl-names = "default";
 933         pinctrl-0 = <&pinctrl_uart1>;
 934         uart-has-rtscts;
 935         status = "disabled";
 936 };
 937
 938 &uart2 {
 939         pinctrl-names = "default";
 940         pinctrl-0 = <&pinctrl_uart2>;
 941         status = "disabled";
 942 };
 943
 944 &uart3 {        /* A53 Debug */
 945         pinctrl-names = "default";
 946         pinctrl-0 = <&pinctrl_uart3>;
 947         status = "okay";
 948 };
 949
 950 &uart4 {        /* M4 Debug */
 951         pinctrl-names = "default";
 952         pinctrl-0 = <&pinctrl_uart4>;
 953         /* UART4 is reserved for CM and RDC blocks CA access to UART4. */
 954         status = "disabled";
 955 };
 956
 957 &usbotg1 {
 958         pinctrl-names = "default";
 959         pinctrl-0 = <&pinctrl_usb_otg1>;
 960         dr_mode = "otg";
 961         status = "okay";
 962 };
 963
 964 &usbotg2 {
 965         disable-over-current;
 966         dr_mode = "host";
 967         status = "okay";
 968 };
 969
 970 &usdhc2 {       /* MicroSD */
 971         assigned-clocks = <&clk IMX8MM_CLK_USDHC2_ROOT>;
 972         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 973         pinctrl-0 = <&pinctrl_usdhc2>;
 974         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 975         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 976         bus-width = <4>;
 977         vmmc-supply = <&reg_usdhc2_vcc>;
 978         status = "okay";
 979 };
 980
 981 &usdhc3 {       /* eMMC */
 982         assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
 983         assigned-clock-rates = <400000000>;
 984         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 985         pinctrl-0 = <&pinctrl_usdhc3>;
 986         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 987         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 988         bus-width = <8>;
 989         non-removable;
 990         vmmc-supply = <&buck4_reg>;
 991         vqmmc-supply = <&buck5_reg>;
 992         status = "okay";
 993 };
 994
 995 &wdog1 {
 996         status = "okay";
 997 };