1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright 2020 Compass Electronics Group, LLC
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 dmic_codec: dmic-codec {
11 compatible = "dmic-codec";
13 #sound-dai-cells = <0>;
17 compatible = "gpio-leds";
21 gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
22 default-state = "off";
27 gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
28 default-state = "off";
33 gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
34 default-state = "off";
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_led3>;
41 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
42 linux,default-trigger = "heartbeat";
46 pcie0_refclk: pcie0-refclk {
47 compatible = "fixed-clock";
49 clock-frequency = <100000000>;
52 pcie0_refclk_gated: pcie0-refclk-gated {
53 compatible = "gpio-gate-clock";
54 clocks = <&pcie0_refclk>;
56 enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
59 reg_audio: regulator-audio {
60 compatible = "regulator-fixed";
61 regulator-name = "3v3_aud";
62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
64 gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
68 reg_usbotg1: regulator-usbotg1 {
69 compatible = "regulator-fixed";
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_reg_usb_otg1>;
72 regulator-name = "usb_otg_vbus";
73 regulator-min-microvolt = <5000000>;
74 regulator-max-microvolt = <5000000>;
75 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
79 reg_camera: regulator-camera {
80 compatible = "regulator-fixed";
81 regulator-name = "mipi_pwr";
82 regulator-min-microvolt = <2800000>;
83 regulator-max-microvolt = <2800000>;
84 gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
86 startup-delay-us = <100000>;
89 reg_pcie0: regulator-pcie {
90 compatible = "regulator-fixed";
91 regulator-name = "pci_pwr_en";
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
95 gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>;
96 startup-delay-us = <100000>;
99 reg_usdhc2_vmmc: regulator-usdhc2 {
100 compatible = "regulator-fixed";
101 regulator-name = "VSD_3V3";
102 regulator-min-microvolt = <3300000>;
103 regulator-max-microvolt = <3300000>;
104 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
109 compatible = "simple-audio-card";
110 simple-audio-card,name = "dmic";
111 simple-audio-card,format = "pdm";
112 simple-audio-card,bitclock-master = <&dailink_master>;
113 simple-audio-card,frame-master = <&dailink_master>;
115 dailink_master: simple-audio-card,cpu {
116 sound-dai = <&micfil>;
119 simple-audio-card,codec {
120 sound-dai = <&dmic_codec>;
125 compatible = "simple-audio-card";
126 simple-audio-card,name = "wm8962";
127 simple-audio-card,format = "i2s";
128 simple-audio-card,widgets = "Headphone", "Headphones",
129 "Microphone", "Headset Mic",
130 "Speaker", "Speaker";
131 simple-audio-card,routing = "Headphones", "HPOUTL",
132 "Headphones", "HPOUTR",
133 "Speaker", "SPKOUTL",
134 "Speaker", "SPKOUTR",
135 "Headset Mic", "MICBIAS",
136 "IN3R", "Headset Mic";
138 simple-audio-card,cpu {
142 simple-audio-card,codec {
143 sound-dai = <&wm8962>;
144 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_espi2>;
158 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
162 compatible = "microchip,at25160bn", "atmel,at25";
164 spi-max-frequency = <5000000>;
169 address-width = <16>;
174 clock-frequency = <400000>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_i2c2>;
180 compatible = "ovti,ov5640";
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_ov5640>;
184 clocks = <&clk IMX8MM_CLK_CLKO1>;
185 clock-names = "xclk";
186 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
187 assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
188 assigned-clock-rates = <24000000>;
189 AVDD-supply = <®_camera>; /* 2.8v */
190 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
191 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
194 /* MIPI CSI-2 bus endpoint */
195 ov5640_to_mipi_csi2: endpoint {
196 remote-endpoint = <&imx8mm_mipi_csi_in>;
205 clock-frequency = <400000>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_i2c4>;
210 wm8962: audio-codec@1a {
211 compatible = "wlf,wm8962";
213 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
214 DCVDD-supply = <®_audio>;
215 DBVDD-supply = <®_audio>;
216 AVDD-supply = <®_audio>;
217 CPVDD-supply = <®_audio>;
218 MICVDD-supply = <®_audio>;
219 PLLVDD-supply = <®_audio>;
220 SPKVDD1-supply = <®_audio>;
221 SPKVDD2-supply = <®_audio>;
223 0x0000 /* 0:Default */
224 0x0000 /* 1:Default */
225 0x0000 /* 2:FN_DMICCLK */
226 0x0000 /* 3:Default */
227 0x0000 /* 4:FN_DMICCDAT */
228 0x0000 /* 5:Default */
230 #sound-dai-cells = <0>;
234 compatible = "nxp,pcal6416";
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_pcal6414>;
240 interrupt-parent = <&gpio4>;
241 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
245 compatible = "nxp,pcal6416";
249 interrupt-parent = <&gpio4>;
250 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_pdm>;
257 assigned-clocks = <&clk IMX8MM_CLK_PDM>;
258 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
259 assigned-clock-rates = <49152000>;
267 imx8mm_mipi_csi_in: endpoint {
268 remote-endpoint = <&ov5640_to_mipi_csi2>;
276 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
277 fsl,tx-deemph-gen1 = <0x2d>;
278 fsl,tx-deemph-gen2 = <0xf>;
279 fsl,clkreq-unsupported;
280 clocks = <&pcie0_refclk_gated>;
286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_pcie0>;
288 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
289 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>,
290 <&clk IMX8MM_CLK_PCIE1_AUX>;
291 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
292 <&clk IMX8MM_CLK_PCIE1_CTRL>;
293 assigned-clock-rates = <10000000>, <250000000>;
294 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
295 <&clk IMX8MM_SYS_PLL2_250M>;
296 vpcie-supply = <®_pcie0>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_sai3>;
303 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
304 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
305 assigned-clock-rates = <24576000>;
306 fsl,sai-mclk-direction-output;
314 &uart2 { /* console */
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_uart2>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_uart3>;
323 assigned-clocks = <&clk IMX8MM_CLK_UART3>;
324 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
330 vbus-supply = <®_usbotg1>;
331 disable-over-current;
337 disable-over-current;
343 reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
347 pinctrl-names = "default", "state_100mhz", "state_200mhz";
348 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
349 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
350 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
352 vmmc-supply = <®_usdhc2_vmmc>;
357 pinctrl_espi2: espi2grp {
359 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
360 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
361 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
362 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x41
366 pinctrl_i2c2: i2c2grp {
368 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
369 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
373 pinctrl_i2c4: i2c4grp {
375 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
376 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
380 pinctrl_led3: led3grp {
382 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41
386 pinctrl_ov5640: ov5640grp {
388 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
389 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
390 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
394 pinctrl_pcal6414: pcal6414-gpiogrp {
396 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
400 pinctrl_pdm: pdmgrp {
402 MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
403 MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
407 pinctrl_reg_usb_otg1: usbotg1grp {
409 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
413 pinctrl_pcie0: pcie0grp {
415 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
419 pinctrl_sai3: sai3grp {
421 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
422 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
423 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
424 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
425 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
429 pinctrl_uart2: uart2grp {
431 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
432 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
436 pinctrl_uart3: uart3grp {
438 MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
439 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
440 MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40
441 MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
445 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
447 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
448 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
452 pinctrl_usdhc2: usdhc2grp {
454 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
455 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
456 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
457 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
458 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
459 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
460 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
464 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
466 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
467 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
468 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
469 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
470 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
471 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
472 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
476 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
478 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
479 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
480 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
481 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
482 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
483 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
484 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0