1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright 2020 Compass Electronics Group, LLC
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 compatible = "gpio-leds";
14 gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
15 default-state = "off";
20 gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
21 default-state = "off";
26 gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
27 default-state = "off";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_led3>;
34 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
35 linux,default-trigger = "heartbeat";
39 pcie0_refclk: pcie0-refclk {
40 compatible = "fixed-clock";
42 clock-frequency = <100000000>;
45 pcie0_refclk_gated: pcie0-refclk-gated {
46 compatible = "gpio-gate-clock";
47 clocks = <&pcie0_refclk>;
49 enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
52 reg_audio: regulator-audio {
53 compatible = "regulator-fixed";
54 regulator-name = "3v3_aud";
55 regulator-min-microvolt = <3300000>;
56 regulator-max-microvolt = <3300000>;
57 gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
61 reg_usbotg1: regulator-usbotg1 {
62 compatible = "regulator-fixed";
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_reg_usb_otg1>;
65 regulator-name = "usb_otg_vbus";
66 regulator-min-microvolt = <5000000>;
67 regulator-max-microvolt = <5000000>;
68 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
72 reg_camera: regulator-camera {
73 compatible = "regulator-fixed";
74 regulator-name = "mipi_pwr";
75 regulator-min-microvolt = <2800000>;
76 regulator-max-microvolt = <2800000>;
77 gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
79 startup-delay-us = <100000>;
82 reg_pcie0: regulator-pcie {
83 compatible = "regulator-fixed";
84 regulator-name = "pci_pwr_en";
85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>;
88 gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>;
89 startup-delay-us = <100000>;
92 reg_usdhc2_vmmc: regulator-usdhc2 {
93 compatible = "regulator-fixed";
94 regulator-name = "VSD_3V3";
95 regulator-min-microvolt = <3300000>;
96 regulator-max-microvolt = <3300000>;
97 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
102 compatible = "fsl,imx-audio-wm8962";
103 model = "wm8962-audio";
105 audio-codec = <&wm8962>;
107 "Headphone Jack", "HPOUTL",
108 "Headphone Jack", "HPOUTR",
109 "Ext Spk", "SPKOUTL",
110 "Ext Spk", "SPKOUTR",
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_espi2>;
123 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
127 compatible = "microchip,at25160bn", "atmel,at25";
129 spi-max-frequency = <5000000>;
134 address-width = <16>;
139 clock-frequency = <400000>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_i2c2>;
145 compatible = "ovti,ov5640";
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_ov5640>;
149 clocks = <&clk IMX8MM_CLK_CLKO1>;
150 clock-names = "xclk";
151 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
152 assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
153 assigned-clock-rates = <24000000>;
154 AVDD-supply = <®_camera>; /* 2.8v */
155 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
156 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
159 /* MIPI CSI-2 bus endpoint */
160 ov5640_to_mipi_csi2: endpoint {
161 remote-endpoint = <&imx8mm_mipi_csi_in>;
170 clock-frequency = <400000>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_i2c4>;
175 wm8962: audio-codec@1a {
176 compatible = "wlf,wm8962";
178 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
179 DCVDD-supply = <®_audio>;
180 DBVDD-supply = <®_audio>;
181 AVDD-supply = <®_audio>;
182 CPVDD-supply = <®_audio>;
183 MICVDD-supply = <®_audio>;
184 PLLVDD-supply = <®_audio>;
185 SPKVDD1-supply = <®_audio>;
186 SPKVDD2-supply = <®_audio>;
188 0x0000 /* 0:Default */
189 0x0000 /* 1:Default */
190 0x0000 /* 2:FN_DMICCLK */
191 0x0000 /* 3:Default */
192 0x0000 /* 4:FN_DMICCDAT */
193 0x0000 /* 5:Default */
198 compatible = "nxp,pcal6416";
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_pcal6414>;
204 interrupt-parent = <&gpio4>;
205 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
209 compatible = "nxp,pcal6416";
213 interrupt-parent = <&gpio4>;
214 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
222 imx8mm_mipi_csi_in: endpoint {
223 remote-endpoint = <&ov5640_to_mipi_csi2>;
231 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
232 fsl,tx-deemph-gen1 = <0x2d>;
233 fsl,tx-deemph-gen2 = <0xf>;
234 fsl,clkreq-unsupported;
235 clocks = <&pcie0_refclk_gated>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_pcie0>;
243 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
244 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
245 <&pcie0_refclk_gated>;
246 clock-names = "pcie", "pcie_aux", "pcie_bus";
247 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
248 <&clk IMX8MM_CLK_PCIE1_CTRL>;
249 assigned-clock-rates = <10000000>, <250000000>;
250 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
251 <&clk IMX8MM_SYS_PLL2_250M>;
252 vpcie-supply = <®_pcie0>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_sai3>;
259 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
260 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
261 assigned-clock-rates = <24576000>;
262 fsl,sai-mclk-direction-output;
270 &uart2 { /* console */
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_uart2>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_uart3>;
279 assigned-clocks = <&clk IMX8MM_CLK_UART3>;
280 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
286 vbus-supply = <®_usbotg1>;
287 disable-over-current;
293 pinctrl-names = "default";
294 disable-over-current;
300 reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
304 pinctrl-names = "default", "state_100mhz", "state_200mhz";
305 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
306 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
307 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
309 vmmc-supply = <®_usdhc2_vmmc>;
314 pinctrl_espi2: espi2grp {
316 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
317 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
318 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
319 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x41
323 pinctrl_i2c2: i2c2grp {
325 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
326 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
330 pinctrl_i2c4: i2c4grp {
332 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
333 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
337 pinctrl_led3: led3grp {
339 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41
343 pinctrl_ov5640: ov5640grp {
345 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
346 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
347 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
351 pinctrl_pcal6414: pcal6414-gpiogrp {
353 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
357 pinctrl_reg_usb_otg1: usbotg1grp {
359 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
363 pinctrl_pcie0: pcie0grp {
365 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
369 pinctrl_sai3: sai3grp {
371 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
372 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
373 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
374 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
375 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
379 pinctrl_uart2: uart2grp {
381 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
382 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
386 pinctrl_uart3: uart3grp {
388 MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
389 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
390 MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40
391 MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
395 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
397 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
398 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
402 pinctrl_usdhc2: usdhc2grp {
404 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
405 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
406 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
407 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
408 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
409 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
410 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
414 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
416 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
417 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
418 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
419 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
420 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
421 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
422 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
426 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
428 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
429 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
430 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
431 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
432 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
433 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
434 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0