arch/arm64/boot/dts/freescale/imx8dxl.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019~2020, 2022 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8-clock.h>
   7 #include <dt-bindings/firmware/imx/rsrc.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/input/input.h>
  11 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 ethernet0 = &fec1;
  21                 ethernet1 = &eqos;
  22                 gpio0 = &lsio_gpio0;
  23                 gpio1 = &lsio_gpio1;
  24                 gpio2 = &lsio_gpio2;
  25                 gpio3 = &lsio_gpio3;
  26                 gpio4 = &lsio_gpio4;
  27                 gpio5 = &lsio_gpio5;
  28                 gpio6 = &lsio_gpio6;
  29                 gpio7 = &lsio_gpio7;
  30                 mu1 = &lsio_mu1;
  31         };
  32
  33         cpus: cpus {
  34                 #address-cells = <2>;
  35                 #size-cells = <0>;
  36
  37                 /* We have 1 clusters with 2 Cortex-A35 cores */
  38                 A35_0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a35";
  41                         reg = <0x0 0x0>;
  42                         enable-method = "psci";
  43                         next-level-cache = <&A35_L2>;
  44                         clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
  45                         #cooling-cells = <2>;
  46                         operating-points-v2 = <&a35_opp_table>;
  47                 };
  48
  49                 A35_1: cpu@1 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a35";
  52                         reg = <0x0 0x1>;
  53                         enable-method = "psci";
  54                         next-level-cache = <&A35_L2>;
  55                         clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
  56                         #cooling-cells = <2>;
  57                         operating-points-v2 = <&a35_opp_table>;
  58                 };
  59
  60                 A35_L2: l2-cache0 {
  61                         compatible = "cache";
  62                 };
  63         };
  64
  65         a35_opp_table: opp-table {
  66                 compatible = "operating-points-v2";
  67                 opp-shared;
  68
  69                 opp-900000000 {
  70                         opp-hz = /bits/ 64 <900000000>;
  71                         opp-microvolt = <1000000>;
  72                         clock-latency-ns = <150000>;
  73                 };
  74
  75                 opp-1200000000 {
  76                         opp-hz = /bits/ 64 <1200000000>;
  77                         opp-microvolt = <1100000>;
  78                         clock-latency-ns = <150000>;
  79                         opp-suspend;
  80                 };
  81         };
  82
  83         gic: interrupt-controller@51a00000 {
  84                 compatible = "arm,gic-v3";
  85                 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
  86                       <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
  87                 #interrupt-cells = <3>;
  88                 interrupt-controller;
  89                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  90         };
  91
  92         reserved-memory {
  93                 #address-cells = <2>;
  94                 #size-cells = <2>;
  95                 ranges;
  96
  97                 dsp_reserved: dsp@92400000 {
  98                         reg = <0 0x92400000 0 0x2000000>;
  99                         no-map;
 100                 };
 101         };
 102
 103         pmu {
 104                 compatible = "arm,armv8-pmuv3";
 105                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 106         };
 107
 108         psci {
 109                 compatible = "arm,psci-1.0";
 110                 method = "smc";
 111         };
 112
 113         system-controller {
 114                 compatible = "fsl,imx-scu";
 115                 mbox-names = "tx0",
 116                              "rx0",
 117                              "gip3";
 118                 mboxes = <&lsio_mu1 0 0
 119                           &lsio_mu1 1 0
 120                           &lsio_mu1 3 3>;
 121
 122                 pd: power-controller {
 123                         compatible = "fsl,scu-pd";
 124                         #power-domain-cells = <1>;
 125                         wakeup-irq = <160 163 235 236 237 228 229 230 231 238
 126                                      239 240 166 169>;
 127                 };
 128
 129                 clk: clock-controller {
 130                         compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
 131                         #clock-cells = <2>;
 132                         clocks = <&xtal32k &xtal24m>;
 133                         clock-names = "xtal_32KHz", "xtal_24Mhz";
 134                 };
 135
 136                 iomuxc: pinctrl {
 137                         compatible = "fsl,imx8dxl-iomuxc";
 138                 };
 139
 140                 ocotp: ocotp {
 141                         compatible = "fsl,imx8qxp-scu-ocotp";
 142                         #address-cells = <1>;
 143                         #size-cells = <1>;
 144
 145                         fec_mac0: mac@2c4 {
 146                                 reg = <0x2c4 6>;
 147                         };
 148
 149                         fec_mac1: mac@2c6 {
 150                                 reg = <0x2c6 6>;
 151                         };
 152                 };
 153
 154                 rtc: rtc {
 155                         compatible = "fsl,imx8qxp-sc-rtc";
 156                 };
 157
 158                 sc_pwrkey: keys {
 159                         compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
 160                         linux,keycodes = <KEY_POWER>;
 161                         wakeup-source;
 162                 };
 163
 164                 watchdog {
 165                         compatible = "fsl,imx-sc-wdt";
 166                         timeout-sec = <60>;
 167                 };
 168
 169                 tsens: thermal-sensor {
 170                         compatible = "fsl,imx-sc-thermal";
 171                         #thermal-sensor-cells = <1>;
 172                 };
 173         };
 174
 175         timer {
 176                 compatible = "arm,armv8-timer";
 177                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
 178                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
 179                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
 180                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
 181         };
 182
 183         thermal_zones: thermal-zones {
 184                 cpu-thermal0 {
 185                         polling-delay-passive = <250>;
 186                         polling-delay = <2000>;
 187                         thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
 188
 189                         trips {
 190                                 cpu_alert0: trip0 {
 191                                         temperature = <107000>;
 192                                         hysteresis = <2000>;
 193                                         type = "passive";
 194                                 };
 195                                 cpu_crit0: trip1 {
 196                                         temperature = <127000>;
 197                                         hysteresis = <2000>;
 198                                         type = "critical";
 199                                 };
 200                         };
 201
 202                         cooling-maps {
 203                                 map0 {
 204                                         trip = <&cpu_alert0>;
 205                                         cooling-device =
 206                                         <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 207                                         <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 208                                 };
 209                         };
 210                 };
 211         };
 212
 213         /* The two values below cannot be changed by the board */
 214         xtal32k: clock-xtal32k {
 215                 compatible = "fixed-clock";
 216                 #clock-cells = <0>;
 217                 clock-frequency = <32768>;
 218                 clock-output-names = "xtal_32KHz";
 219         };
 220
 221         xtal24m: clock-xtal24m {
 222                 compatible = "fixed-clock";
 223                 #clock-cells = <0>;
 224                 clock-frequency = <24000000>;
 225                 clock-output-names = "xtal_24MHz";
 226         };
 227
 228         /* sorted in register address */
 229         #include "imx8-ss-adma.dtsi"
 230         #include "imx8-ss-conn.dtsi"
 231         #include "imx8-ss-ddr.dtsi"
 232         #include "imx8-ss-lsio.dtsi"
 233 };
 234
 235 #include "imx8dxl-ss-adma.dtsi"
 236 #include "imx8dxl-ss-conn.dtsi"
 237 #include "imx8dxl-ss-lsio.dtsi"
 238 #include "imx8dxl-ss-ddr.dtsi"