1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019~2020, 2022 NXP
7 compatible = "nxp,imx8dxl-fspi";
8 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
12 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
13 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
14 gpio-ranges = <&iomuxc 0 47 13>,
21 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
22 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
23 gpio-ranges = <&iomuxc 4 74 5>,
28 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
29 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
30 gpio-ranges = <&iomuxc 1 98 2>,
36 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
37 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
38 gpio-ranges = <&iomuxc 0 115 4>,
56 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
57 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
58 gpio-ranges = <&iomuxc 0 0 3>,
67 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
68 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
69 gpio-ranges = <&iomuxc 0 32 3>,
75 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
76 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
77 gpio-ranges = <&iomuxc 0 53 7>,
83 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
84 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
85 gpio-ranges = <&iomuxc 0 0 3>,
93 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
94 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
98 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
99 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
103 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
104 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
108 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
109 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
113 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
114 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
118 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
119 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;