1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019~2020, 2022 NXP
6 /delete-node/ &enet1_lpcg;
10 conn_enet0_root_clk: clock-conn-enet0-root {
11 compatible = "fixed-clock";
13 clock-frequency = <250000000>;
14 clock-output-names = "conn_enet0_root_clk";
19 eqos: ethernet@5b050000 {
20 compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
21 reg = <0x5b050000 0x10000>;
22 interrupt-parent = <&gic>;
23 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
24 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
25 interrupt-names = "eth_wake_irq", "macirq";
26 clocks = <&eqos_lpcg IMX_LPCG_CLK_4>,
27 <&eqos_lpcg IMX_LPCG_CLK_6>,
28 <&eqos_lpcg IMX_LPCG_CLK_0>,
29 <&eqos_lpcg IMX_LPCG_CLK_5>,
30 <&eqos_lpcg IMX_LPCG_CLK_2>;
31 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
32 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
33 assigned-clock-rates = <125000000>;
34 power-domains = <&pd IMX_SC_R_ENET_1>;
38 usbotg2: usb@5b0e0000 {
39 compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
40 reg = <0x5b0e0000 0x200>;
41 interrupt-parent = <&gic>;
42 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
43 fsl,usbphy = <&usbphy2>;
44 fsl,usbmisc = <&usbmisc2 0>;
46 * usbotg1 and usbotg2 share one clcok.
47 * scu firmware disables the access to the clock and keeps
48 * it always on in case other core (M4) uses one of these.
50 clocks = <&clk_dummy>;
51 ahb-burst-config = <0x0>;
52 tx-burst-size-dword = <0x10>;
53 rx-burst-size-dword = <0x10>;
54 power-domains = <&pd IMX_SC_R_USB_1>;
57 clk_dummy: clock-dummy {
58 compatible = "fixed-clock";
60 clock-frequency = <0>;
61 clock-output-names = "clk_dummy";
65 usbmisc2: usbmisc@5b0e0200 {
67 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
68 reg = <0x5b0e0200 0x200>;
71 usbphy2: usbphy@5b110000 {
72 compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
73 reg = <0x5b110000 0x1000>;
74 clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>;
75 power-domains = <&pd IMX_SC_R_USB_1_PHY>;
79 eqos_lpcg: clock-controller@5b240000 {
80 compatible = "fsl,imx8qxp-lpcg";
81 reg = <0x5b240000 0x10000>;
83 clocks = <&conn_enet0_root_clk>,
86 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
88 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>,
89 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
91 clock-output-names = "eqos_ptp",
96 power-domains = <&pd IMX_SC_R_ENET_1>;
99 usb2_2_lpcg: clock-controller@5b280000 {
100 compatible = "fsl,imx8qxp-lpcg";
101 reg = <0x5b280000 0x10000>;
103 clock-indices = <IMX_LPCG_CLK_7>;
104 clocks = <&conn_ipg_clk>;
105 clock-output-names = "usboh3_2_phy_ipg_clk";
106 power-domains = <&pd IMX_SC_R_USB_1_PHY>;
112 clocks = <&conn_enet0_root_clk>,
113 <&conn_enet0_root_clk>,
115 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
121 compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec";
122 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
126 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
127 assigned-clock-rates = <125000000>;
131 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
132 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
136 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
137 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
141 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
142 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
146 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
148 * usbotg1 and usbotg2 share one clock
149 * scfw disable clock access and keep it always on
150 * in case other core (M4) use one of these.
152 clocks = <&clk_dummy>;