arch/arm64/boot/dts/freescale/imx8dxl-evk.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019~2020, 2022 NXP
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "imx8dxl.dtsi"
   9
  10 / {
  11         model = "Freescale i.MX8DXL EVK";
  12         compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
  13
  14         aliases {
  15                 i2c2 = &i2c2;
  16                 mmc0 = &usdhc1;
  17                 mmc1 = &usdhc2;
  18                 serial0 = &lpuart0;
  19         };
  20
  21         chosen {
  22                 stdout-path = &lpuart0;
  23         };
  24
  25         memory@80000000 {
  26                 device_type = "memory";
  27                 reg = <0x00000000 0x80000000 0 0x40000000>;
  28         };
  29
  30         reserved-memory {
  31                 #address-cells = <2>;
  32                 #size-cells = <2>;
  33                 ranges;
  34
  35                 /*
  36                  * Memory reserved for optee usage. Please do not use.
  37                  * This will be automatically added to dtb if OP-TEE is installed.
  38                  * optee@96000000 {
  39                  *     reg = <0 0x96000000 0 0x2000000>;
  40                  *     no-map;
  41                  * };
  42                  */
  43
  44                 /* global autoconfigured region for contiguous allocations */
  45                 linux,cma {
  46                         compatible = "shared-dma-pool";
  47                         reusable;
  48                         size = <0 0x14000000>;
  49                         alloc-ranges = <0 0x98000000 0 0x14000000>;
  50                         linux,cma-default;
  51                 };
  52         };
  53
  54         mux3_en: regulator-0 {
  55                 compatible = "regulator-fixed";
  56                 regulator-min-microvolt = <3300000>;
  57                 regulator-max-microvolt = <3300000>;
  58                 regulator-name = "mux3_en";
  59                 gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>;
  60                 regulator-always-on;
  61         };
  62
  63         reg_fec1_sel: regulator-1 {
  64                 compatible = "regulator-fixed";
  65                 regulator-name = "fec1_supply";
  66                 regulator-min-microvolt = <3300000>;
  67                 regulator-max-microvolt = <3300000>;
  68                 gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>;
  69                 regulator-always-on;
  70                 status = "disabled";
  71         };
  72
  73         reg_fec1_io: regulator-2 {
  74                 compatible = "regulator-fixed";
  75                 regulator-name = "fec1_io_supply";
  76                 regulator-min-microvolt = <1800000>;
  77                 regulator-max-microvolt = <1800000>;
  78                 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
  79                 enable-active-high;
  80                 regulator-always-on;
  81                 status = "disabled";
  82         };
  83
  84         reg_usdhc2_vmmc: regulator-3 {
  85                 compatible = "regulator-fixed";
  86                 regulator-name = "SD1_SPWR";
  87                 regulator-min-microvolt = <3000000>;
  88                 regulator-max-microvolt = <3000000>;
  89                 gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
  90                 enable-active-high;
  91                 off-on-delay-us = <3480>;
  92         };
  93 };
  94
  95 &eqos {
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&pinctrl_eqos>;
  98         phy-mode = "rgmii-id";
  99         phy-handle = <&ethphy0>;
 100         nvmem-cells = <&fec_mac1>;
 101         nvmem-cell-names = "mac-address";
 102         status = "okay";
 103
 104         mdio {
 105                 compatible = "snps,dwmac-mdio";
 106                 #address-cells = <1>;
 107                 #size-cells = <0>;
 108
 109                 ethphy0: ethernet-phy@0 {
 110                         compatible = "ethernet-phy-ieee802.3-c22";
 111                         reg = <0>;
 112                         eee-broken-1000t;
 113                         qca,disable-smarteee;
 114                         qca,disable-hibernation-mode;
 115                         reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
 116                         reset-assert-us = <20>;
 117                         reset-deassert-us = <200000>;
 118                         vddio-supply = <&vddio0>;
 119
 120                         vddio0: vddio-regulator {
 121                                 regulator-min-microvolt = <1800000>;
 122                                 regulator-max-microvolt = <1800000>;
 123                         };
 124                 };
 125         };
 126 };
 127
 128 /*
 129  * fec1 shares the some PINs with usdhc2.
 130  * by default usdhc2 is enabled in this dts.
 131  * Please disable usdhc2 to enable fec1
 132  */
 133 &fec1 {
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&pinctrl_fec1>;
 136         phy-mode = "rgmii-txid";
 137         phy-handle = <&ethphy1>;
 138         fsl,magic-packet;
 139         rx-internal-delay-ps = <2000>;
 140         nvmem-cells = <&fec_mac0>;
 141         nvmem-cell-names = "mac-address";
 142         status = "disabled";
 143
 144         mdio {
 145                 #address-cells = <1>;
 146                 #size-cells = <0>;
 147
 148                 ethphy1: ethernet-phy@1 {
 149                         compatible = "ethernet-phy-ieee802.3-c22";
 150                         reg = <1>;
 151                         reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
 152                         reset-assert-us = <10000>;
 153                         qca,disable-smarteee;
 154                         vddio-supply = <&vddio1>;
 155
 156                         vddio1: vddio-regulator {
 157                                 regulator-min-microvolt = <1800000>;
 158                                 regulator-max-microvolt = <1800000>;
 159                         };
 160                 };
 161         };
 162 };
 163
 164 &i2c2 {
 165         #address-cells = <1>;
 166         #size-cells = <0>;
 167         clock-frequency = <100000>;
 168         pinctrl-names = "default";
 169         pinctrl-0 = <&pinctrl_i2c2>;
 170         status = "okay";
 171
 172         pca6416_1: gpio@20 {
 173                 compatible = "ti,tca6416";
 174                 reg = <0x20>;
 175                 gpio-controller;
 176                 #gpio-cells = <2>;
 177         };
 178
 179         pca6416_2: gpio@21 {
 180                 compatible = "ti,tca6416";
 181                 reg = <0x21>;
 182                 gpio-controller;
 183                 #gpio-cells = <2>;
 184         };
 185
 186         pca9548_1: i2c-mux@70 {
 187                 compatible = "nxp,pca9548";
 188                 #address-cells = <1>;
 189                 #size-cells = <0>;
 190                 reg = <0x70>;
 191
 192                 i2c@0 {
 193                         #address-cells = <1>;
 194                         #size-cells = <0>;
 195                         reg = <0x0>;
 196
 197                         max7322: gpio@68 {
 198                                 compatible = "maxim,max7322";
 199                                 reg = <0x68>;
 200                                 gpio-controller;
 201                                 #gpio-cells = <2>;
 202                                 status = "disabled";
 203                         };
 204                 };
 205
 206                 i2c@4 {
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209                         reg = <0x4>;
 210                 };
 211
 212                 i2c@5 {
 213                         #address-cells = <1>;
 214                         #size-cells = <0>;
 215                         reg = <0x5>;
 216                 };
 217
 218                 i2c@6 {
 219                         #address-cells = <1>;
 220                         #size-cells = <0>;
 221                         reg = <0x6>;
 222                 };
 223         };
 224 };
 225
 226 &lpuart0 {
 227         pinctrl-names = "default";
 228         pinctrl-0 = <&pinctrl_lpuart0>;
 229         status = "okay";
 230 };
 231
 232 &lsio_gpio4 {
 233         status = "okay";
 234 };
 235
 236 &lsio_gpio5 {
 237         status = "okay";
 238 };
 239
 240 &thermal_zones {
 241         pmic-thermal0 {
 242                 polling-delay-passive = <250>;
 243                 polling-delay = <2000>;
 244                 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
 245
 246                 trips {
 247                         pmic_alert0: trip0 {
 248                                 temperature = <110000>;
 249                                 hysteresis = <2000>;
 250                                 type = "passive";
 251                         };
 252
 253                         pmic_crit0: trip1 {
 254                                 temperature = <125000>;
 255                                 hysteresis = <2000>;
 256                                 type = "critical";
 257                         };
 258                 };
 259
 260                 cooling-maps {
 261                         map0 {
 262                                 trip = <&pmic_alert0>;
 263                                 cooling-device =
 264                                         <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 265                                         <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 266                         };
 267                 };
 268         };
 269 };
 270
 271 &usdhc1 {
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&pinctrl_usdhc1>;
 274         bus-width = <8>;
 275         no-sd;
 276         no-sdio;
 277         non-removable;
 278         status = "okay";
 279 };
 280
 281 &usdhc2 {
 282         pinctrl-names = "default";
 283         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 284         bus-width = <4>;
 285         vmmc-supply = <&reg_usdhc2_vmmc>;
 286         cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
 287         wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
 288         status = "okay";
 289 };
 290
 291 &iomuxc {
 292         pinctrl-names = "default";
 293         pinctrl-0 = <&pinctrl_hog>;
 294
 295         pinctrl_hog: hoggrp {
 296                 fsl,pins = <
 297                         IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD       0x000514a0
 298                         IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD       0x000014a0
 299                         IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1             0x0600004c
 300                         IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN     0x0600004c
 301                 >;
 302         };
 303
 304         pinctrl_usbotg1: usbotg1grp {
 305                 fsl,pins = <
 306                         IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR           0x00000021
 307                 >;
 308         };
 309
 310         pinctrl_usbotg2: usbotg2grp {
 311                 fsl,pins = <
 312                         IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR           0x00000021
 313                 >;
 314         };
 315
 316         pinctrl_eqos: eqosgrp {
 317                 fsl,pins = <
 318                         IMX8DXL_ENET0_MDC_CONN_EQOS_MDC                         0x06000020
 319                         IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO                       0x06000020
 320                         IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC             0x06000020
 321                         IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0           0x06000020
 322                         IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1           0x06000020
 323                         IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2           0x06000020
 324                         IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3           0x06000020
 325                         IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL       0x06000020
 326                         IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC             0x06000020
 327                         IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0           0x06000020
 328                         IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1           0x06000020
 329                         IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2           0x06000020
 330                         IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3           0x06000020
 331                         IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL       0x06000020
 332                 >;
 333         };
 334
 335         pinctrl_fec1: fec1grp {
 336                 fsl,pins = <
 337                         IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD           0x000014a0
 338                         IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD           0x000014a0
 339                         IMX8DXL_ENET0_MDC_CONN_ENET0_MDC                        0x06000020
 340                         IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO                      0x06000020
 341                         IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC            0x00000060
 342                         IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0          0x00000060
 343                         IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1          0x00000060
 344                         IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2          0x00000060
 345                         IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3          0x00000060
 346                         IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL      0x00000060
 347                         IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC            0x00000060
 348                         IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0          0x00000060
 349                         IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1          0x00000060
 350                         IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2          0x00000060
 351                         IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3          0x00000060
 352                         IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL      0x00000060
 353                 >;
 354         };
 355
 356         pinctrl_lpspi3: lpspi3grp {
 357                 fsl,pins = <
 358                         IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK          0x6000040
 359                         IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO          0x6000040
 360                         IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI          0x6000040
 361                         IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1          0x6000040
 362                 >;
 363         };
 364
 365         pinctrl_i2c2: i2c2grp {
 366                 fsl,pins = <
 367                         IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA          0x06000021
 368                         IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL          0x06000021
 369                 >;
 370         };
 371
 372         pinctrl_cm40_lpuart: cm40lpuartgrp {
 373                 fsl,pins = <
 374                         IMX8DXL_ADC_IN2_M40_UART0_RX            0x06000020
 375                         IMX8DXL_ADC_IN3_M40_UART0_TX            0x06000020
 376                 >;
 377         };
 378
 379         pinctrl_i2c3: i2c3grp {
 380                 fsl,pins = <
 381                         IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA          0x06000021
 382                         IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL          0x06000021
 383                 >;
 384         };
 385
 386         pinctrl_lpuart0: lpuart0grp {
 387                 fsl,pins = <
 388                         IMX8DXL_UART0_RX_ADMA_UART0_RX          0x06000020
 389                         IMX8DXL_UART0_TX_ADMA_UART0_TX          0x06000020
 390                 >;
 391         };
 392
 393         pinctrl_usdhc1: usdhc1grp {
 394                 fsl,pins = <
 395                         IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK        0x06000041
 396                         IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD        0x00000021
 397                         IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0    0x00000021
 398                         IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1    0x00000021
 399                         IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2    0x00000021
 400                         IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3    0x00000021
 401                         IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4    0x00000021
 402                         IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5    0x00000021
 403                         IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6    0x00000021
 404                         IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7    0x00000021
 405                         IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE  0x00000041
 406                 >;
 407         };
 408
 409         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 410                 fsl,pins = <
 411                         IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30      0x00000040 /* RESET_B */
 412                         IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00        0x00000021 /* WP */
 413                         IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01        0x00000021 /* CD */
 414                 >;
 415         };
 416
 417         pinctrl_usdhc2: usdhc2grp {
 418                 fsl,pins = <
 419                         IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK         0x06000041
 420                         IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD      0x00000021
 421                         IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0      0x00000021
 422                         IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1      0x00000021
 423                         IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2      0x00000021
 424                         IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3      0x00000021
 425                         IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT    0x00000021
 426                 >;
 427         };
 428 };