arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2020 NXP
   4  *      Dong Aisheng <aisheng.dong@nxp.com>
   5  */
   6
   7 #include <dt-bindings/clock/imx8-lpcg.h>
   8 #include <dt-bindings/firmware/imx/rsrc.h>
   9
  10 lsio_bus_clk: clock-lsio-bus {
  11         compatible = "fixed-clock";
  12         #clock-cells = <0>;
  13         clock-frequency = <100000000>;
  14         clock-output-names = "lsio_bus_clk";
  15 };
  16
  17 lsio_subsys: bus@5d000000 {
  18         compatible = "simple-bus";
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21         ranges = <0x5d000000 0x0 0x5d000000 0x1000000>,
  22                  <0x08000000 0x0 0x08000000 0x10000000>;
  23
  24         lsio_pwm0: pwm@5d000000 {
  25                 compatible = "fsl,imx27-pwm";
  26                 reg = <0x5d000000 0x10000>;
  27                 clock-names = "ipg", "per";
  28                 clocks = <&pwm0_lpcg 4>,
  29                          <&pwm0_lpcg 1>;
  30                 assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
  31                 assigned-clock-rates = <24000000>;
  32                 #pwm-cells = <3>;
  33                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
  34                 status = "disabled";
  35         };
  36
  37         lsio_pwm1: pwm@5d010000 {
  38                 compatible = "fsl,imx27-pwm";
  39                 reg = <0x5d010000 0x10000>;
  40                 clock-names = "ipg", "per";
  41                 clocks = <&pwm1_lpcg 4>,
  42                          <&pwm1_lpcg 1>;
  43                 assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
  44                 assigned-clock-rates = <24000000>;
  45                 #pwm-cells = <3>;
  46                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
  47                 status = "disabled";
  48         };
  49
  50         lsio_pwm2: pwm@5d020000 {
  51                 compatible = "fsl,imx27-pwm";
  52                 reg = <0x5d020000 0x10000>;
  53                 clock-names = "ipg", "per";
  54                 clocks = <&pwm2_lpcg 4>,
  55                          <&pwm2_lpcg 1>;
  56                 assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
  57                 assigned-clock-rates = <24000000>;
  58                 #pwm-cells = <3>;
  59                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  60                 status = "disabled";
  61         };
  62
  63         lsio_pwm3: pwm@5d030000 {
  64                 compatible = "fsl,imx27-pwm";
  65                 reg = <0x5d030000 0x10000>;
  66                 clock-names = "ipg", "per";
  67                 clocks = <&pwm3_lpcg 4>,
  68                          <&pwm3_lpcg 1>;
  69                 assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
  70                 assigned-clock-rates = <24000000>;
  71                 #pwm-cells = <3>;
  72                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
  73                 status = "disabled";
  74         };
  75
  76         lsio_gpio0: gpio@5d080000 {
  77                 reg = <0x5d080000 0x10000>;
  78                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
  79                 gpio-controller;
  80                 #gpio-cells = <2>;
  81                 interrupt-controller;
  82                 #interrupt-cells = <2>;
  83                 power-domains = <&pd IMX_SC_R_GPIO_0>;
  84         };
  85
  86         lsio_gpio1: gpio@5d090000 {
  87                 reg = <0x5d090000 0x10000>;
  88                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
  89                 gpio-controller;
  90                 #gpio-cells = <2>;
  91                 interrupt-controller;
  92                 #interrupt-cells = <2>;
  93                 power-domains = <&pd IMX_SC_R_GPIO_1>;
  94         };
  95
  96         lsio_gpio2: gpio@5d0a0000 {
  97                 reg = <0x5d0a0000 0x10000>;
  98                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
  99                 gpio-controller;
 100                 #gpio-cells = <2>;
 101                 interrupt-controller;
 102                 #interrupt-cells = <2>;
 103                 power-domains = <&pd IMX_SC_R_GPIO_2>;
 104         };
 105
 106         lsio_gpio3: gpio@5d0b0000 {
 107                 reg = <0x5d0b0000 0x10000>;
 108                 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 109                 gpio-controller;
 110                 #gpio-cells = <2>;
 111                 interrupt-controller;
 112                 #interrupt-cells = <2>;
 113                 power-domains = <&pd IMX_SC_R_GPIO_3>;
 114         };
 115
 116         lsio_gpio4: gpio@5d0c0000 {
 117                 reg = <0x5d0c0000 0x10000>;
 118                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 119                 gpio-controller;
 120                 #gpio-cells = <2>;
 121                 interrupt-controller;
 122                 #interrupt-cells = <2>;
 123                 power-domains = <&pd IMX_SC_R_GPIO_4>;
 124         };
 125
 126         lsio_gpio5: gpio@5d0d0000 {
 127                 reg = <0x5d0d0000 0x10000>;
 128                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 129                 gpio-controller;
 130                 #gpio-cells = <2>;
 131                 interrupt-controller;
 132                 #interrupt-cells = <2>;
 133                 power-domains = <&pd IMX_SC_R_GPIO_5>;
 134         };
 135
 136         lsio_gpio6: gpio@5d0e0000 {
 137                 reg = <0x5d0e0000 0x10000>;
 138                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 139                 gpio-controller;
 140                 #gpio-cells = <2>;
 141                 interrupt-controller;
 142                 #interrupt-cells = <2>;
 143                 power-domains = <&pd IMX_SC_R_GPIO_6>;
 144         };
 145
 146         lsio_gpio7: gpio@5d0f0000 {
 147                 reg = <0x5d0f0000 0x10000>;
 148                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 149                 gpio-controller;
 150                 #gpio-cells = <2>;
 151                 interrupt-controller;
 152                 #interrupt-cells = <2>;
 153                 power-domains = <&pd IMX_SC_R_GPIO_7>;
 154         };
 155
 156         flexspi0: spi@5d120000 {
 157                 #address-cells = <1>;
 158                 #size-cells = <0>;
 159                 compatible = "nxp,imx8qxp-fspi";
 160                 reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>;
 161                 reg-names = "fspi_base", "fspi_mmap";
 162                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 163                 clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>,
 164                          <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>;
 165                 clock-names = "fspi_en", "fspi";
 166                 power-domains = <&pd IMX_SC_R_FSPI_0>;
 167                 status = "disabled";
 168         };
 169
 170         lsio_mu0: mailbox@5d1b0000 {
 171                 reg = <0x5d1b0000 0x10000>;
 172                 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 173                 #mbox-cells = <2>;
 174                 status = "disabled";
 175         };
 176
 177         lsio_mu1: mailbox@5d1c0000 {
 178                 reg = <0x5d1c0000 0x10000>;
 179                 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 180                 #mbox-cells = <2>;
 181         };
 182
 183         lsio_mu2: mailbox@5d1d0000 {
 184                 reg = <0x5d1d0000 0x10000>;
 185                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 186                 #mbox-cells = <2>;
 187                 status = "disabled";
 188         };
 189
 190         lsio_mu3: mailbox@5d1e0000 {
 191                 reg = <0x5d1e0000 0x10000>;
 192                 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 193                 #mbox-cells = <2>;
 194                 status = "disabled";
 195         };
 196
 197         lsio_mu4: mailbox@5d1f0000 {
 198                 reg = <0x5d1f0000 0x10000>;
 199                 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 200                 #mbox-cells = <2>;
 201                 status = "disabled";
 202         };
 203
 204         lsio_mu5: mailbox@5d200000 {
 205                 reg = <0x5d200000 0x10000>;
 206                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 207                 #mbox-cells = <2>;
 208                 power-domains = <&pd IMX_SC_R_MU_5A>;
 209                 status = "disabled";
 210         };
 211
 212         lsio_mu6: mailbox@5d210000 {
 213                 reg = <0x5d210000 0x10000>;
 214                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 215                 #mbox-cells = <2>;
 216                 power-domains = <&pd IMX_SC_R_MU_6A>;
 217                 status = "disabled";
 218         };
 219
 220         lsio_mu13: mailbox@5d280000 {
 221                 reg = <0x5d280000 0x10000>;
 222                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 223                 #mbox-cells = <2>;
 224                 power-domains = <&pd IMX_SC_R_MU_13A>;
 225         };
 226
 227         /* LPCG clocks */
 228         pwm0_lpcg: clock-controller@5d400000 {
 229                 compatible = "fsl,imx8qxp-lpcg";
 230                 reg = <0x5d400000 0x10000>;
 231                 #clock-cells = <1>;
 232                 clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
 233                          <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
 234                          <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
 235                          <&lsio_bus_clk>,
 236                          <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
 237                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 238                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 239                                 <IMX_LPCG_CLK_6>;
 240                 clock-output-names = "pwm0_lpcg_ipg_clk",
 241                                      "pwm0_lpcg_ipg_hf_clk",
 242                                      "pwm0_lpcg_ipg_s_clk",
 243                                      "pwm0_lpcg_ipg_slv_clk",
 244                                      "pwm0_lpcg_ipg_mstr_clk";
 245                 power-domains = <&pd IMX_SC_R_PWM_0>;
 246         };
 247
 248         pwm1_lpcg: clock-controller@5d410000 {
 249                 compatible = "fsl,imx8qxp-lpcg";
 250                 reg = <0x5d410000 0x10000>;
 251                 #clock-cells = <1>;
 252                 clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
 253                          <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
 254                          <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
 255                          <&lsio_bus_clk>,
 256                          <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
 257                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 258                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 259                                 <IMX_LPCG_CLK_6>;
 260                 clock-output-names = "pwm1_lpcg_ipg_clk",
 261                                      "pwm1_lpcg_ipg_hf_clk",
 262                                      "pwm1_lpcg_ipg_s_clk",
 263                                      "pwm1_lpcg_ipg_slv_clk",
 264                                      "pwm1_lpcg_ipg_mstr_clk";
 265                 power-domains = <&pd IMX_SC_R_PWM_1>;
 266         };
 267
 268         pwm2_lpcg: clock-controller@5d420000 {
 269                 compatible = "fsl,imx8qxp-lpcg";
 270                 reg = <0x5d420000 0x10000>;
 271                 #clock-cells = <1>;
 272                 clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
 273                          <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
 274                          <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
 275                          <&lsio_bus_clk>,
 276                          <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
 277                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 278                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 279                                 <IMX_LPCG_CLK_6>;
 280                 clock-output-names = "pwm2_lpcg_ipg_clk",
 281                                      "pwm2_lpcg_ipg_hf_clk",
 282                                      "pwm2_lpcg_ipg_s_clk",
 283                                      "pwm2_lpcg_ipg_slv_clk",
 284                                      "pwm2_lpcg_ipg_mstr_clk";
 285                 power-domains = <&pd IMX_SC_R_PWM_2>;
 286         };
 287
 288         pwm3_lpcg: clock-controller@5d430000 {
 289                 compatible = "fsl,imx8qxp-lpcg";
 290                 reg = <0x5d430000 0x10000>;
 291                 #clock-cells = <1>;
 292                 clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
 293                          <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
 294                          <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
 295                          <&lsio_bus_clk>,
 296                          <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
 297                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 298                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 299                                 <IMX_LPCG_CLK_6>;
 300                 clock-output-names = "pwm3_lpcg_ipg_clk",
 301                                      "pwm3_lpcg_ipg_hf_clk",
 302                                      "pwm3_lpcg_ipg_s_clk",
 303                                      "pwm3_lpcg_ipg_slv_clk",
 304                                      "pwm3_lpcg_ipg_mstr_clk";
 305                 power-domains = <&pd IMX_SC_R_PWM_3>;
 306         };
 307
 308         pwm4_lpcg: clock-controller@5d440000 {
 309                 compatible = "fsl,imx8qxp-lpcg";
 310                 reg = <0x5d440000 0x10000>;
 311                 #clock-cells = <1>;
 312                 clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
 313                          <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
 314                          <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
 315                          <&lsio_bus_clk>,
 316                          <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>;
 317                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 318                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 319                                 <IMX_LPCG_CLK_6>;
 320                 clock-output-names = "pwm4_lpcg_ipg_clk",
 321                                      "pwm4_lpcg_ipg_hf_clk",
 322                                      "pwm4_lpcg_ipg_s_clk",
 323                                      "pwm4_lpcg_ipg_slv_clk",
 324                                      "pwm4_lpcg_ipg_mstr_clk";
 325                 power-domains = <&pd IMX_SC_R_PWM_4>;
 326         };
 327
 328         pwm5_lpcg: clock-controller@5d450000 {
 329                 compatible = "fsl,imx8qxp-lpcg";
 330                 reg = <0x5d450000 0x10000>;
 331                 #clock-cells = <1>;
 332                 clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
 333                          <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
 334                          <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
 335                          <&lsio_bus_clk>,
 336                          <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>;
 337                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 338                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 339                                 <IMX_LPCG_CLK_6>;
 340                 clock-output-names = "pwm5_lpcg_ipg_clk",
 341                                      "pwm5_lpcg_ipg_hf_clk",
 342                                      "pwm5_lpcg_ipg_s_clk",
 343                                      "pwm5_lpcg_ipg_slv_clk",
 344                                      "pwm5_lpcg_ipg_mstr_clk";
 345                 power-domains = <&pd IMX_SC_R_PWM_5>;
 346         };
 347
 348         pwm6_lpcg: clock-controller@5d460000 {
 349                 compatible = "fsl,imx8qxp-lpcg";
 350                 reg = <0x5d460000 0x10000>;
 351                 #clock-cells = <1>;
 352                 clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
 353                          <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
 354                          <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
 355                          <&lsio_bus_clk>,
 356                          <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>;
 357                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 358                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 359                                 <IMX_LPCG_CLK_6>;
 360                 clock-output-names = "pwm6_lpcg_ipg_clk",
 361                                      "pwm6_lpcg_ipg_hf_clk",
 362                                      "pwm6_lpcg_ipg_s_clk",
 363                                      "pwm6_lpcg_ipg_slv_clk",
 364                                      "pwm6_lpcg_ipg_mstr_clk";
 365                 power-domains = <&pd IMX_SC_R_PWM_6>;
 366         };
 367
 368         pwm7_lpcg: clock-controller@5d470000 {
 369                 compatible = "fsl,imx8qxp-lpcg";
 370                 reg = <0x5d470000 0x10000>;
 371                 #clock-cells = <1>;
 372                 clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
 373                          <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
 374                          <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
 375                          <&lsio_bus_clk>,
 376                          <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>;
 377                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
 378                                 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 379                                 <IMX_LPCG_CLK_6>;
 380                 clock-output-names = "pwm7_lpcg_ipg_clk",
 381                                      "pwm7_lpcg_ipg_hf_clk",
 382                                      "pwm7_lpcg_ipg_s_clk",
 383                                      "pwm7_lpcg_ipg_slv_clk",
 384                                      "pwm7_lpcg_ipg_mstr_clk";
 385                 power-domains = <&pd IMX_SC_R_PWM_7>;
 386         };
 387 };