1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2021 NXP
4 * Zhou Guoniu <guoniu.zhou@nxp.com>
6 img_ipg_clk: clock-img-ipg {
7 compatible = "fixed-clock";
9 clock-frequency = <200000000>;
10 clock-output-names = "img_ipg_clk";
13 img_subsys: bus@58000000 {
14 compatible = "simple-bus";
17 ranges = <0x58000000 0x0 0x58000000 0x1000000>;
19 jpegdec: jpegdec@58400000 {
20 reg = <0x58400000 0x00050000>;
21 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
22 clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
23 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
24 clock-names = "per", "ipg";
25 assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
26 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
27 assigned-clock-rates = <200000000>, <200000000>;
28 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
29 <&pd IMX_SC_R_MJPEG_DEC_S0>;
33 jpegenc: jpegenc@58450000 {
34 reg = <0x58450000 0x00050000>;
35 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
36 clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
37 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
38 clock-names = "per", "ipg";
39 assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
40 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
41 assigned-clock-rates = <200000000>, <200000000>;
42 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
43 <&pd IMX_SC_R_MJPEG_ENC_S0>;
47 img_jpeg_dec_lpcg: clock-controller@585d0000 {
48 compatible = "fsl,imx8qxp-lpcg";
49 reg = <0x585d0000 0x10000>;
51 clocks = <&img_ipg_clk>, <&img_ipg_clk>;
52 clock-indices = <IMX_LPCG_CLK_0>,
54 clock-output-names = "img_jpeg_dec_lpcg_clk",
55 "img_jpeg_dec_lpcg_ipg_clk";
56 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
59 img_jpeg_enc_lpcg: clock-controller@585f0000 {
60 compatible = "fsl,imx8qxp-lpcg";
61 reg = <0x585f0000 0x10000>;
63 clocks = <&img_ipg_clk>, <&img_ipg_clk>;
64 clock-indices = <IMX_LPCG_CLK_0>,
66 clock-output-names = "img_jpeg_enc_lpcg_clk",
67 "img_jpeg_enc_lpcg_ipg_clk";
68 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;