arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2019 NXP
   4  *      Dong Aisheng <aisheng.dong@nxp.com>
   5  */
   6
   7 #include <dt-bindings/clock/imx8-lpcg.h>
   8 #include <dt-bindings/firmware/imx/rsrc.h>
   9
  10 dma_subsys: bus@5a000000 {
  11         compatible = "simple-bus";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
  15
  16         dma_ipg_clk: clock-dma-ipg {
  17                 compatible = "fixed-clock";
  18                 #clock-cells = <0>;
  19                 clock-frequency = <120000000>;
  20                 clock-output-names = "dma_ipg_clk";
  21         };
  22
  23         lpuart0: serial@5a060000 {
  24                 reg = <0x5a060000 0x1000>;
  25                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
  26                 clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
  27                          <&uart0_lpcg IMX_LPCG_CLK_0>;
  28                 clock-names = "ipg", "baud";
  29                 assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
  30                 assigned-clock-rates = <80000000>;
  31                 power-domains = <&pd IMX_SC_R_UART_0>;
  32                 status = "disabled";
  33         };
  34
  35         lpuart1: serial@5a070000 {
  36                 reg = <0x5a070000 0x1000>;
  37                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
  38                 clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
  39                          <&uart1_lpcg IMX_LPCG_CLK_0>;
  40                 clock-names = "ipg", "baud";
  41                 assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
  42                 assigned-clock-rates = <80000000>;
  43                 power-domains = <&pd IMX_SC_R_UART_1>;
  44                 status = "disabled";
  45         };
  46
  47         lpuart2: serial@5a080000 {
  48                 reg = <0x5a080000 0x1000>;
  49                 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
  50                 clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
  51                          <&uart2_lpcg IMX_LPCG_CLK_0>;
  52                 clock-names = "ipg", "baud";
  53                 assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
  54                 assigned-clock-rates = <80000000>;
  55                 power-domains = <&pd IMX_SC_R_UART_2>;
  56                 status = "disabled";
  57         };
  58
  59         lpuart3: serial@5a090000 {
  60                 reg = <0x5a090000 0x1000>;
  61                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
  62                 clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
  63                          <&uart3_lpcg IMX_LPCG_CLK_0>;
  64                 clock-names = "ipg", "baud";
  65                 assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
  66                 assigned-clock-rates = <80000000>;
  67                 power-domains = <&pd IMX_SC_R_UART_3>;
  68                 status = "disabled";
  69         };
  70
  71         uart0_lpcg: clock-controller@5a460000 {
  72                 compatible = "fsl,imx8qxp-lpcg";
  73                 reg = <0x5a460000 0x10000>;
  74                 #clock-cells = <1>;
  75                 clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
  76                          <&dma_ipg_clk>;
  77                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
  78                 clock-output-names = "uart0_lpcg_baud_clk",
  79                                      "uart0_lpcg_ipg_clk";
  80                 power-domains = <&pd IMX_SC_R_UART_0>;
  81         };
  82
  83         uart1_lpcg: clock-controller@5a470000 {
  84                 compatible = "fsl,imx8qxp-lpcg";
  85                 reg = <0x5a470000 0x10000>;
  86                 #clock-cells = <1>;
  87                 clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
  88                          <&dma_ipg_clk>;
  89                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
  90                 clock-output-names = "uart1_lpcg_baud_clk",
  91                                      "uart1_lpcg_ipg_clk";
  92                 power-domains = <&pd IMX_SC_R_UART_1>;
  93         };
  94
  95         uart2_lpcg: clock-controller@5a480000 {
  96                 compatible = "fsl,imx8qxp-lpcg";
  97                 reg = <0x5a480000 0x10000>;
  98                 #clock-cells = <1>;
  99                 clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
 100                          <&dma_ipg_clk>;
 101                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
 102                 clock-output-names = "uart2_lpcg_baud_clk",
 103                                      "uart2_lpcg_ipg_clk";
 104                 power-domains = <&pd IMX_SC_R_UART_2>;
 105         };
 106
 107         uart3_lpcg: clock-controller@5a490000 {
 108                 compatible = "fsl,imx8qxp-lpcg";
 109                 reg = <0x5a490000 0x10000>;
 110                 #clock-cells = <1>;
 111                 clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
 112                          <&dma_ipg_clk>;
 113                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
 114                 clock-output-names = "uart3_lpcg_baud_clk",
 115                                      "uart3_lpcg_ipg_clk";
 116                 power-domains = <&pd IMX_SC_R_UART_3>;
 117         };
 118
 119         i2c0: i2c@5a800000 {
 120                 reg = <0x5a800000 0x4000>;
 121                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 122                 clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>,
 123                          <&i2c0_lpcg IMX_LPCG_CLK_4>;
 124                 clock-names = "per", "ipg";
 125                 assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
 126                 assigned-clock-rates = <24000000>;
 127                 power-domains = <&pd IMX_SC_R_I2C_0>;
 128                 status = "disabled";
 129         };
 130
 131         i2c1: i2c@5a810000 {
 132                 reg = <0x5a810000 0x4000>;
 133                 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 134                 clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>,
 135                          <&i2c1_lpcg IMX_LPCG_CLK_4>;
 136                 clock-names = "per", "ipg";
 137                 assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
 138                 assigned-clock-rates = <24000000>;
 139                 power-domains = <&pd IMX_SC_R_I2C_1>;
 140                 status = "disabled";
 141         };
 142
 143         i2c2: i2c@5a820000 {
 144                 reg = <0x5a820000 0x4000>;
 145                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
 146                 clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>,
 147                          <&i2c2_lpcg IMX_LPCG_CLK_4>;
 148                 clock-names = "per", "ipg";
 149                 assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
 150                 assigned-clock-rates = <24000000>;
 151                 power-domains = <&pd IMX_SC_R_I2C_2>;
 152                 status = "disabled";
 153         };
 154
 155         i2c3: i2c@5a830000 {
 156                 reg = <0x5a830000 0x4000>;
 157                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 158                 clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>,
 159                          <&i2c3_lpcg IMX_LPCG_CLK_4>;
 160                 clock-names = "per", "ipg";
 161                 assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
 162                 assigned-clock-rates = <24000000>;
 163                 power-domains = <&pd IMX_SC_R_I2C_3>;
 164                 status = "disabled";
 165         };
 166
 167         i2c0_lpcg: clock-controller@5ac00000 {
 168                 compatible = "fsl,imx8qxp-lpcg";
 169                 reg = <0x5ac00000 0x10000>;
 170                 #clock-cells = <1>;
 171                 clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
 172                          <&dma_ipg_clk>;
 173                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
 174                 clock-output-names = "i2c0_lpcg_clk",
 175                                      "i2c0_lpcg_ipg_clk";
 176                 power-domains = <&pd IMX_SC_R_I2C_0>;
 177         };
 178
 179         i2c1_lpcg: clock-controller@5ac10000 {
 180                 compatible = "fsl,imx8qxp-lpcg";
 181                 reg = <0x5ac10000 0x10000>;
 182                 #clock-cells = <1>;
 183                 clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
 184                          <&dma_ipg_clk>;
 185                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
 186                 clock-output-names = "i2c1_lpcg_clk",
 187                                      "i2c1_lpcg_ipg_clk";
 188                 power-domains = <&pd IMX_SC_R_I2C_1>;
 189         };
 190
 191         i2c2_lpcg: clock-controller@5ac20000 {
 192                 compatible = "fsl,imx8qxp-lpcg";
 193                 reg = <0x5ac20000 0x10000>;
 194                 #clock-cells = <1>;
 195                 clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
 196                          <&dma_ipg_clk>;
 197                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
 198                 clock-output-names = "i2c2_lpcg_clk",
 199                                      "i2c2_lpcg_ipg_clk";
 200                 power-domains = <&pd IMX_SC_R_I2C_2>;
 201         };
 202
 203         i2c3_lpcg: clock-controller@5ac30000 {
 204                 compatible = "fsl,imx8qxp-lpcg";
 205                 reg = <0x5ac30000 0x10000>;
 206                 #clock-cells = <1>;
 207                 clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
 208                          <&dma_ipg_clk>;
 209                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
 210                 clock-output-names = "i2c3_lpcg_clk",
 211                                      "i2c3_lpcg_ipg_clk";
 212                 power-domains = <&pd IMX_SC_R_I2C_3>;
 213         };
 214 };