1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com>
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 conn_subsys: bus@5b000000 {
11 compatible = "simple-bus";
14 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
16 conn_axi_clk: clock-conn-axi {
17 compatible = "fixed-clock";
19 clock-frequency = <333333333>;
20 clock-output-names = "conn_axi_clk";
23 conn_ahb_clk: clock-conn-ahb {
24 compatible = "fixed-clock";
26 clock-frequency = <166666666>;
27 clock-output-names = "conn_ahb_clk";
30 conn_ipg_clk: clock-conn-ipg {
31 compatible = "fixed-clock";
33 clock-frequency = <83333333>;
34 clock-output-names = "conn_ipg_clk";
37 usdhc1: mmc@5b010000 {
38 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
39 reg = <0x5b010000 0x10000>;
40 clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
41 <&sdhc0_lpcg IMX_LPCG_CLK_5>,
42 <&sdhc0_lpcg IMX_LPCG_CLK_0>;
43 clock-names = "ipg", "ahb", "per";
44 power-domains = <&pd IMX_SC_R_SDHC_0>;
48 usdhc2: mmc@5b020000 {
49 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
50 reg = <0x5b020000 0x10000>;
51 clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
52 <&sdhc1_lpcg IMX_LPCG_CLK_5>,
53 <&sdhc1_lpcg IMX_LPCG_CLK_0>;
54 clock-names = "ipg", "ahb", "per";
55 power-domains = <&pd IMX_SC_R_SDHC_1>;
56 fsl,tuning-start-tap = <20>;
57 fsl,tuning-step = <2>;
61 usdhc3: mmc@5b030000 {
62 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
63 reg = <0x5b030000 0x10000>;
64 clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
65 <&sdhc2_lpcg IMX_LPCG_CLK_5>,
66 <&sdhc2_lpcg IMX_LPCG_CLK_0>;
67 clock-names = "ipg", "ahb", "per";
68 power-domains = <&pd IMX_SC_R_SDHC_2>;
72 fec1: ethernet@5b040000 {
73 reg = <0x5b040000 0x10000>;
74 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
79 <&enet0_lpcg IMX_LPCG_CLK_2>,
80 <&enet0_lpcg IMX_LPCG_CLK_3>,
81 <&enet0_lpcg IMX_LPCG_CLK_0>;
82 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
83 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
84 <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
85 assigned-clock-rates = <250000000>, <125000000>;
86 fsl,num-tx-queues = <3>;
87 fsl,num-rx-queues = <3>;
88 power-domains = <&pd IMX_SC_R_ENET_0>;
92 fec2: ethernet@5b050000 {
93 reg = <0x5b050000 0x10000>;
94 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
99 <&enet1_lpcg IMX_LPCG_CLK_2>,
100 <&enet1_lpcg IMX_LPCG_CLK_3>,
101 <&enet1_lpcg IMX_LPCG_CLK_0>;
102 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
103 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
104 <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
105 assigned-clock-rates = <250000000>, <125000000>;
106 fsl,num-tx-queues = <3>;
107 fsl,num-rx-queues = <3>;
108 power-domains = <&pd IMX_SC_R_ENET_1>;
113 sdhc0_lpcg: clock-controller@5b200000 {
114 compatible = "fsl,imx8qxp-lpcg";
115 reg = <0x5b200000 0x10000>;
117 clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
118 <&conn_ipg_clk>, <&conn_axi_clk>;
119 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
121 clock-output-names = "sdhc0_lpcg_per_clk",
122 "sdhc0_lpcg_ipg_clk",
123 "sdhc0_lpcg_ahb_clk";
124 power-domains = <&pd IMX_SC_R_SDHC_0>;
127 sdhc1_lpcg: clock-controller@5b210000 {
128 compatible = "fsl,imx8qxp-lpcg";
129 reg = <0x5b210000 0x10000>;
131 clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
132 <&conn_ipg_clk>, <&conn_axi_clk>;
133 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
135 clock-output-names = "sdhc1_lpcg_per_clk",
136 "sdhc1_lpcg_ipg_clk",
137 "sdhc1_lpcg_ahb_clk";
138 power-domains = <&pd IMX_SC_R_SDHC_1>;
141 sdhc2_lpcg: clock-controller@5b220000 {
142 compatible = "fsl,imx8qxp-lpcg";
143 reg = <0x5b220000 0x10000>;
145 clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
146 <&conn_ipg_clk>, <&conn_axi_clk>;
147 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
149 clock-output-names = "sdhc2_lpcg_per_clk",
150 "sdhc2_lpcg_ipg_clk",
151 "sdhc2_lpcg_ahb_clk";
152 power-domains = <&pd IMX_SC_R_SDHC_2>;
155 enet0_lpcg: clock-controller@5b230000 {
156 compatible = "fsl,imx8qxp-lpcg";
157 reg = <0x5b230000 0x10000>;
159 clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
160 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
162 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
165 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
166 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
167 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
168 clock-output-names = "enet0_lpcg_timer_clk",
169 "enet0_lpcg_txc_sampling_clk",
170 "enet0_lpcg_ahb_clk",
171 "enet0_lpcg_rgmii_txc_clk",
172 "enet0_lpcg_ipg_clk",
173 "enet0_lpcg_ipg_s_clk";
174 power-domains = <&pd IMX_SC_R_ENET_0>;
177 enet1_lpcg: clock-controller@5b240000 {
178 compatible = "fsl,imx8qxp-lpcg";
179 reg = <0x5b240000 0x10000>;
181 clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
182 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
184 <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
187 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
188 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
189 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
190 clock-output-names = "enet1_lpcg_timer_clk",
191 "enet1_lpcg_txc_sampling_clk",
192 "enet1_lpcg_ahb_clk",
193 "enet1_lpcg_rgmii_txc_clk",
194 "enet1_lpcg_ipg_clk",
195 "enet1_lpcg_ipg_s_clk";
196 power-domains = <&pd IMX_SC_R_ENET_1>;