arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /*
   3  * Copyright 2022 Toradex
   4  */
   5
   6 #include <dt-bindings/pwm/pwm.h>
   7
   8 / {
   9         chosen {
  10                 stdout-path = &lpuart1;
  11         };
  12
  13         /* Apalis BKL1 */
  14         backlight: backlight {
  15                 compatible = "pwm-backlight";
  16                 pinctrl-names = "default";
  17                 pinctrl-0 = <&pinctrl_gpio_bkl_on>;
  18                 brightness-levels = <0 45 63 88 119 158 203 255>;
  19                 default-brightness-level = <4>;
  20                 enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */
  21                 /* TODO: hook-up to Apalis BKL1_PWM */
  22                 status = "disabled";
  23         };
  24
  25         gpio_fan: gpio-fan {
  26                 compatible = "gpio-fan";
  27                 pinctrl-names = "default";
  28                 pinctrl-0 = <&pinctrl_gpio8>;
  29                 gpios = <&lsio_gpio3 28 GPIO_ACTIVE_HIGH>;
  30                 gpio-fan,speed-map = <   0 0
  31                                       3000 1>;
  32         };
  33
  34         /* TODO: LVDS Panel */
  35
  36         /* TODO: Shared PCIe/SATA Reference Clock */
  37
  38         /* TODO: PCIe Wi-Fi Reference Clock */
  39
  40         /*
  41          * Power management bus used to control LDO1OUT of the
  42          * second PMIC PF8100. This is used for controlling voltage levels of
  43          * typespecific RGMII signals and Apalis UART2_RTS UART2_CTS.
  44          *
  45          * IMX_SC_R_BOARD_R1 for 3.3V
  46          * IMX_SC_R_BOARD_R2 for 1.8V
  47          * IMX_SC_R_BOARD_R3 for 2.5V
  48          * Note that for 2.5V operation the pad muxing needs to be changed,
  49          * compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD.
  50          *
  51          * those power domains are mutually exclusive.
  52          */
  53         reg_ext_rgmii: regulator-ext-rgmii {
  54                 compatible = "regulator-fixed";
  55                 power-domains = <&pd IMX_SC_R_BOARD_R1>;
  56                 regulator-max-microvolt = <3300000>;
  57                 regulator-min-microvolt = <3300000>;
  58                 regulator-name = "VDD_EXT_RGMII (LDO1)";
  59
  60                 regulator-state-mem {
  61                         regulator-off-in-suspend;
  62                 };
  63         };
  64
  65         reg_module_3v3: regulator-module-3v3 {
  66                 compatible = "regulator-fixed";
  67                 regulator-max-microvolt = <3300000>;
  68                 regulator-min-microvolt = <3300000>;
  69                 regulator-name = "+V3.3";
  70         };
  71
  72         reg_module_3v3_avdd: regulator-module-3v3-avdd {
  73                 compatible = "regulator-fixed";
  74                 regulator-max-microvolt = <3300000>;
  75                 regulator-min-microvolt = <3300000>;
  76                 regulator-name = "+V3.3_AUDIO";
  77         };
  78
  79         reg_module_wifi: regulator-module-wifi {
  80                 compatible = "regulator-fixed";
  81                 pinctrl-names = "default";
  82                 pinctrl-0 = <&pinctrl_wifi_pdn>;
  83                 gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>;
  84                 enable-active-high;
  85                 regulator-always-on;
  86                 regulator-name = "wifi_pwrdn_fake_regulator";
  87                 regulator-settling-time-us = <100>;
  88         };
  89
  90         reg_pcie_switch: regulator-pcie-switch {
  91                 compatible = "regulator-fixed";
  92                 pinctrl-names = "default";
  93                 pinctrl-0 = <&pinctrl_gpio7>;
  94                 gpio = <&lsio_gpio3 26 GPIO_ACTIVE_HIGH>;
  95                 enable-active-high;
  96                 regulator-max-microvolt = <1800000>;
  97                 regulator-min-microvolt = <1800000>;
  98                 regulator-name = "pcie_switch";
  99                 startup-delay-us = <100000>;
 100         };
 101
 102         reg_usb_host_vbus: regulator-usb-host-vbus {
 103                 compatible = "regulator-fixed";
 104                 pinctrl-names = "default";
 105                 pinctrl-0 = <&pinctrl_usbh_en>;
 106                 /* Apalis USBH_EN */
 107                 gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>;
 108                 enable-active-high;
 109                 regulator-always-on;
 110                 regulator-max-microvolt = <5000000>;
 111                 regulator-min-microvolt = <5000000>;
 112                 regulator-name = "usb-host-vbus";
 113         };
 114
 115         reg_usb_hsic: regulator-usb-hsic {
 116                 compatible = "regulator-fixed";
 117                 regulator-max-microvolt = <3000000>;
 118                 regulator-min-microvolt = <3000000>;
 119                 regulator-name = "usb-hsic-dummy";
 120         };
 121
 122         reg_usb_phy: regulator-usb-hsic1 {
 123                 compatible = "regulator-fixed";
 124                 regulator-max-microvolt = <3000000>;
 125                 regulator-min-microvolt = <3000000>;
 126                 regulator-name = "usb-phy-dummy";
 127         };
 128
 129         reserved-memory {
 130                 #address-cells = <2>;
 131                 #size-cells = <2>;
 132                 ranges;
 133
 134                 decoder_boot: decoder-boot@84000000 {
 135                         reg = <0 0x84000000 0 0x2000000>;
 136                         no-map;
 137                 };
 138
 139                 encoder1_boot: encoder1-boot@86000000 {
 140                         reg = <0 0x86000000 0 0x200000>;
 141                         no-map;
 142                 };
 143
 144                 encoder2_boot: encoder2-boot@86200000 {
 145                         reg = <0 0x86200000 0 0x200000>;
 146                         no-map;
 147                 };
 148
 149                 /*
 150                  * reserved-memory layout
 151                  * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
 152                  * Shouldn't be used at A core and Linux side.
 153                  *
 154                  */
 155                 m4_reserved: m4@88000000 {
 156                         reg = <0 0x88000000 0 0x8000000>;
 157                         no-map;
 158                 };
 159
 160                 rpmsg_reserved: rpmsg@90200000 {
 161                         reg = <0 0x90200000 0 0x200000>;
 162                         no-map;
 163                 };
 164
 165                 vdevbuffer: vdevbuffer@90400000 {
 166                         compatible = "shared-dma-pool";
 167                         reg = <0 0x90400000 0 0x100000>;
 168                         no-map;
 169                 };
 170
 171                 decoder_rpc: decoder-rpc@92000000 {
 172                         reg = <0 0x92000000 0 0x200000>;
 173                         no-map;
 174                 };
 175
 176                 dsp_reserved: dsp@92400000 {
 177                         reg = <0 0x92400000 0 0x2000000>;
 178                         no-map;
 179                 };
 180
 181                 encoder1_rpc: encoder1-rpc@94400000 {
 182                         reg = <0 0x94400000 0 0x700000>;
 183                         no-map;
 184                 };
 185
 186                 encoder2_rpc: encoder2-rpc@94b00000 {
 187                         reg = <0 0x94b00000 0 0x700000>;
 188                         no-map;
 189                 };
 190
 191                 /* global autoconfigured region for contiguous allocations */
 192                 linux,cma {
 193                         compatible = "shared-dma-pool";
 194                         alloc-ranges = <0 0xc0000000 0 0x3c000000>;
 195                         linux,cma-default;
 196                         reusable;
 197                         size = <0 0x3c000000>;
 198                 };
 199         };
 200
 201         /* TODO: Apalis Analogue Audio */
 202
 203         /* TODO: HDMI Audio */
 204
 205         /* TODO: Apalis SPDIF1 */
 206
 207         touchscreen: touchscreen {
 208                 compatible = "toradex,vf50-touchscreen";
 209                 interrupt-parent = <&lsio_gpio3>;
 210                 interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
 211                 pinctrl-names = "idle", "default";
 212                 pinctrl-0 = <&pinctrl_touchctrl_idle>, <&pinctrl_touchctrl_gpios>;
 213                 pinctrl-1 = <&pinctrl_adc1>, <&pinctrl_touchctrl_gpios>;
 214                 io-channels = <&adc1 2>, <&adc1 1>,
 215                               <&adc1 0>, <&adc1 3>;
 216                 vf50-ts-min-pressure = <200>;
 217                 xp-gpios = <&lsio_gpio2 4 GPIO_ACTIVE_LOW>;
 218                 xm-gpios = <&lsio_gpio2 5 GPIO_ACTIVE_HIGH>;
 219                 yp-gpios = <&lsio_gpio2 17 GPIO_ACTIVE_LOW>;
 220                 ym-gpios = <&lsio_gpio2 21 GPIO_ACTIVE_HIGH>;
 221                 /*
 222                  * NOTE: you must remove the pinctrl-adc1 from the adc1
 223                  * node below to use the touchscreen
 224                  */
 225                 status = "disabled";
 226         };
 227
 228 };
 229
 230 &adc0 {
 231         pinctrl-names = "default";
 232         pinctrl-0 = <&pinctrl_adc0>;
 233 };
 234
 235 &adc1 {
 236         pinctrl-names = "default";
 237         pinctrl-0 = <&pinctrl_adc1>;
 238 };
 239
 240 /* TODO: Asynchronous Sample Rate Converter (ASRC) */
 241
 242 /* Apalis ETH1 */
 243 &fec1 {
 244         pinctrl-names = "default", "sleep";
 245         pinctrl-0 = <&pinctrl_fec1>;
 246         pinctrl-1 = <&pinctrl_fec1_sleep>;
 247         fsl,magic-packet;
 248         phy-handle = <&ethphy0>;
 249         phy-mode = "rgmii-id";
 250
 251         mdio {
 252                 #address-cells = <1>;
 253                 #size-cells = <0>;
 254
 255                 ethphy0: ethernet-phy@7 {
 256                         compatible = "ethernet-phy-ieee802.3-c22";
 257                         reg = <7>;
 258                         interrupt-parent = <&lsio_gpio1>;
 259                         interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
 260                         micrel,led-mode = <0>;
 261                         reset-assert-us = <2>;
 262                         reset-deassert-us = <2>;
 263                         reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>;
 264                         reset-names = "phy";
 265                 };
 266         };
 267 };
 268
 269 /* Apalis CAN1 */
 270 &flexcan1 {
 271         pinctrl-names = "default";
 272         pinctrl-0 = <&pinctrl_flexcan1>;
 273 };
 274
 275 /* Apalis CAN2 */
 276 &flexcan2 {
 277         pinctrl-names = "default";
 278         pinctrl-0 = <&pinctrl_flexcan2>;
 279 };
 280
 281 /* Apalis CAN3 (optional) */
 282 &flexcan3 {
 283         pinctrl-names = "default";
 284         pinctrl-0 = <&pinctrl_flexcan3>;
 285 };
 286
 287 /* TODO: Apalis HDMI1 */
 288
 289 /* On-module I2C */
 290 &i2c1 {
 291         pinctrl-names = "default";
 292         pinctrl-0 = <&pinctrl_lpi2c1>;
 293         #address-cells = <1>;
 294         #size-cells = <0>;
 295         clock-frequency = <100000>;
 296         status = "okay";
 297
 298         /* TODO: Audio Codec */
 299
 300         /* USB3503A */
 301         usb-hub@8 {
 302                 compatible = "smsc,usb3503a";
 303                 reg = <0x08>;
 304                 pinctrl-names = "default";
 305                 pinctrl-0 = <&pinctrl_usb3503a>;
 306                 connect-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_LOW>;
 307                 initial-mode = <1>;
 308                 intn-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>;
 309                 refclk-frequency = <25000000>;
 310                 reset-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_LOW>;
 311         };
 312 };
 313
 314 /* Apalis I2C1 */
 315 &i2c2 {
 316         pinctrl-names = "default";
 317         pinctrl-0 = <&pinctrl_lpi2c2>;
 318         #address-cells = <1>;
 319         #size-cells = <0>;
 320         clock-frequency = <100000>;
 321
 322         atmel_mxt_ts: touch@4a {
 323                 compatible = "atmel,maxtouch";
 324                 reg = <0x4a>;
 325                 interrupt-parent = <&lsio_gpio4>;
 326                 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;         /* Apalis GPIO5 */
 327                 pinctrl-names = "default";
 328                 pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpio6>;
 329                 reset-gpios = <&lsio_gpio4 2 GPIO_ACTIVE_LOW>;  /* Apalis GPIO6 */
 330                 status = "disabled";
 331         };
 332
 333         /* M41T0M6 real time clock on carrier board */
 334         rtc_i2c: rtc@68 {
 335                 compatible = "st,m41t0";
 336                 reg = <0x68>;
 337                 status = "disabled";
 338         };
 339 };
 340
 341 /* Apalis I2C3 (CAM) */
 342 &i2c3 {
 343         pinctrl-names = "default";
 344         pinctrl-0 = <&pinctrl_lpi2c3>;
 345         #address-cells = <1>;
 346         #size-cells = <0>;
 347         clock-frequency = <100000>;
 348 };
 349
 350 &jpegdec {
 351         status = "okay";
 352 };
 353
 354 &jpegenc {
 355         status = "okay";
 356 };
 357
 358 /* TODO: Apalis LVDS1 */
 359
 360 /* Apalis SPI1 */
 361 &lpspi0 {
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&pinctrl_lpspi0>;
 364         #address-cells = <1>;
 365         #size-cells = <0>;
 366         cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>;
 367 };
 368
 369 /* Apalis SPI2 */
 370 &lpspi2 {
 371         pinctrl-names = "default";
 372         pinctrl-0 = <&pinctrl_lpspi2>;
 373         #address-cells = <1>;
 374         #size-cells = <0>;
 375         cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>;
 376 };
 377
 378 /* Apalis UART3 */
 379 &lpuart0 {
 380         pinctrl-names = "default";
 381         pinctrl-0 = <&pinctrl_lpuart0>;
 382 };
 383
 384 /* Apalis UART1 */
 385 &lpuart1 {
 386         pinctrl-names = "default";
 387         pinctrl-0 = <&pinctrl_lpuart1>;
 388 };
 389
 390 /* Apalis UART4 */
 391 &lpuart2 {
 392         pinctrl-names = "default";
 393         pinctrl-0 = <&pinctrl_lpuart2>;
 394 };
 395
 396 /* Apalis UART2 */
 397 &lpuart3 {
 398         pinctrl-names = "default";
 399         pinctrl-0 = <&pinctrl_lpuart3>;
 400 };
 401
 402 &lsio_gpio0 {
 403         gpio-line-names = "MXM3_279",
 404                           "MXM3_277",
 405                           "MXM3_135",
 406                           "MXM3_203",
 407                           "MXM3_201",
 408                           "MXM3_275",
 409                           "MXM3_110",
 410                           "MXM3_120",
 411                           "MXM3_1/GPIO1",
 412                           "MXM3_3/GPIO2",
 413                           "MXM3_124",
 414                           "MXM3_122",
 415                           "MXM3_5/GPIO3",
 416                           "MXM3_7/GPIO4",
 417                           "",
 418                           "",
 419                           "MXM3_4",
 420                           "MXM3_211",
 421                           "MXM3_209",
 422                           "MXM3_2",
 423                           "MXM3_136",
 424                           "MXM3_134",
 425                           "MXM3_6",
 426                           "MXM3_8",
 427                           "MXM3_112",
 428                           "MXM3_118",
 429                           "MXM3_114",
 430                           "MXM3_116";
 431 };
 432
 433 &lsio_gpio1 {
 434         gpio-line-names = "",
 435                           "",
 436                           "",
 437                           "",
 438                           "MXM3_286",
 439                           "",
 440                           "MXM3_87",
 441                           "MXM3_99",
 442                           "MXM3_138",
 443                           "MXM3_140",
 444                           "MXM3_239",
 445                           "",
 446                           "MXM3_281",
 447                           "MXM3_283",
 448                           "MXM3_126",
 449                           "MXM3_132",
 450                           "",
 451                           "",
 452                           "",
 453                           "",
 454                           "MXM3_173",
 455                           "MXM3_175",
 456                           "MXM3_123";
 457
 458         hdmi-ctrl-hog {
 459                 pinctrl-names = "default";
 460                 pinctrl-0 = <&pinctrl_hdmi_ctrl>;
 461                 gpio-hog;
 462                 gpios = <30 GPIO_ACTIVE_HIGH>;
 463                 line-name = "CONNECTOR_IS_HDMI";
 464                 /* Set signals depending on HDP device type, 0 DP, 1 HDMI */
 465                 output-high;
 466         };
 467 };
 468
 469 &lsio_gpio2 {
 470         gpio-line-names = "",
 471                           "",
 472                           "",
 473                           "",
 474                           "",
 475                           "",
 476                           "",
 477                           "MXM3_198",
 478                           "MXM3_35",
 479                           "MXM3_164",
 480                           "",
 481                           "",
 482                           "",
 483                           "",
 484                           "MXM3_217",
 485                           "MXM3_215",
 486                           "",
 487                           "",
 488                           "MXM3_193",
 489                           "MXM3_194",
 490                           "MXM3_37",
 491                           "",
 492                           "MXM3_271",
 493                           "MXM3_273",
 494                           "MXM3_195",
 495                           "MXM3_197",
 496                           "MXM3_177",
 497                           "MXM3_179",
 498                           "MXM3_181",
 499                           "MXM3_183",
 500                           "MXM3_185",
 501                           "MXM3_187";
 502
 503         pcie-wifi-hog {
 504                 pinctrl-names = "default";
 505                 pinctrl-0 = <&pinctrl_pcie_wifi_refclk>;
 506                 gpio-hog;
 507                 gpios = <11 GPIO_ACTIVE_HIGH>;
 508                 line-name = "PCIE_WIFI_CLK";
 509                 output-high;
 510         };
 511 };
 512
 513 &lsio_gpio3 {
 514         gpio-line-names = "MXM3_191",
 515                           "",
 516                           "MXM3_221",
 517                           "MXM3_225",
 518                           "MXM3_223",
 519                           "MXM3_227",
 520                           "MXM3_200",
 521                           "MXM3_235",
 522                           "MXM3_231",
 523                           "MXM3_229",
 524                           "MXM3_233",
 525                           "MXM3_204",
 526                           "MXM3_196",
 527                           "",
 528                           "MXM3_202",
 529                           "",
 530                           "",
 531                           "",
 532                           "MXM3_305",
 533                           "MXM3_307",
 534                           "MXM3_309",
 535                           "MXM3_311",
 536                           "MXM3_315",
 537                           "MXM3_317",
 538                           "MXM3_319",
 539                           "MXM3_321",
 540                           "MXM3_15/GPIO7",
 541                           "MXM3_63",
 542                           "MXM3_17/GPIO8",
 543                           "MXM3_12",
 544                           "MXM3_14",
 545                           "MXM3_16";
 546 };
 547
 548 &lsio_gpio4 {
 549         gpio-line-names = "MXM3_18",
 550                           "MXM3_11/GPIO5",
 551                           "MXM3_13/GPIO6",
 552                           "MXM3_274",
 553                           "MXM3_84",
 554                           "MXM3_262",
 555                           "MXM3_96",
 556                           "",
 557                           "",
 558                           "",
 559                           "",
 560                           "",
 561                           "MXM3_190",
 562                           "",
 563                           "",
 564                           "",
 565                           "MXM3_269",
 566                           "MXM3_251",
 567                           "MXM3_253",
 568                           "MXM3_295",
 569                           "MXM3_299",
 570                           "MXM3_301",
 571                           "MXM3_297",
 572                           "MXM3_293",
 573                           "MXM3_291",
 574                           "MXM3_289",
 575                           "MXM3_287";
 576
 577         /* Enable pcie root / sata ref clock unconditionally */
 578         pcie-sata-hog {
 579                 pinctrl-names = "default";
 580                 pinctrl-0 = <&pinctrl_pcie_sata_refclk>;
 581                 gpio-hog;
 582                 gpios = <11 GPIO_ACTIVE_HIGH>;
 583                 line-name = "PCIE_SATA_CLK";
 584                 output-high;
 585         };
 586 };
 587
 588 &lsio_gpio5 {
 589         gpio-line-names = "",
 590                           "",
 591                           "",
 592                           "",
 593                           "",
 594                           "",
 595                           "",
 596                           "",
 597                           "",
 598                           "",
 599                           "",
 600                           "",
 601                           "",
 602                           "",
 603                           "MXM3_150",
 604                           "MXM3_160",
 605                           "MXM3_162",
 606                           "MXM3_144",
 607                           "MXM3_146",
 608                           "MXM3_148",
 609                           "MXM3_152",
 610                           "MXM3_156",
 611                           "MXM3_158",
 612                           "MXM3_159",
 613                           "MXM3_184",
 614                           "MXM3_180",
 615                           "MXM3_186",
 616                           "MXM3_188",
 617                           "MXM3_176",
 618                           "MXM3_178";
 619 };
 620
 621 &lsio_gpio6 {
 622         gpio-line-names = "",
 623                           "",
 624                           "",
 625                           "",
 626                           "",
 627                           "",
 628                           "",
 629                           "",
 630                           "",
 631                           "",
 632                           "MXM3_261",
 633                           "MXM3_263",
 634                           "MXM3_259",
 635                           "MXM3_257",
 636                           "MXM3_255",
 637                           "MXM3_128",
 638                           "MXM3_130",
 639                           "MXM3_265",
 640                           "MXM3_249",
 641                           "MXM3_247",
 642                           "MXM3_245",
 643                           "MXM3_243";
 644 };
 645
 646 /* Apalis PWM3, MXM3 pin 6 */
 647 &lsio_pwm0 {
 648         pinctrl-names = "default";
 649         pinctrl-0 = <&pinctrl_pwm0>;
 650         #pwm-cells = <3>;
 651 };
 652
 653 /* Apalis PWM4, MXM3 pin 8 */
 654 &lsio_pwm1 {
 655         pinctrl-names = "default";
 656         pinctrl-0 = <&pinctrl_pwm1>;
 657         #pwm-cells = <3>;
 658 };
 659
 660 /* Apalis PWM1, MXM3 pin 2 */
 661 &lsio_pwm2 {
 662         pinctrl-names = "default";
 663         pinctrl-0 = <&pinctrl_pwm2>;
 664         #pwm-cells = <3>;
 665 };
 666
 667 /* Apalis PWM2, MXM3 pin 4 */
 668 &lsio_pwm3 {
 669         pinctrl-names = "default";
 670         pinctrl-0 = <&pinctrl_pwm3>;
 671         #pwm-cells = <3>;
 672 };
 673
 674 /* Messaging Units */
 675 &mu_m0 {
 676         status = "okay";
 677 };
 678
 679 &mu1_m0 {
 680         status = "okay";
 681 };
 682
 683 &mu2_m0 {
 684         status = "okay";
 685 };
 686
 687 /* TODO: Apalis PCIE1 */
 688
 689 /* TODO: On-module Wi-Fi */
 690
 691 /* TODO: Apalis BKL1_PWM */
 692
 693 /* TODO: Apalis DAP1 */
 694
 695 /* TODO: Analogue Audio */
 696
 697 /* TODO: Apalis SATA1 */
 698
 699 /* TODO: Apalis SPDIF1 */
 700
 701 /* TODO: Thermal Zones */
 702
 703 /* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
 704
 705 /* TODO: Apalis USBH4 */
 706
 707 /* Apalis USBO1 */
 708 &usbphy1 {
 709         phy-3p0-supply = <&reg_usb_phy>;
 710         status = "okay";
 711 };
 712
 713 &usbotg1 {
 714         pinctrl-names = "default";
 715         pinctrl-0 = <&pinctrl_usbotg1>;
 716         adp-disable;
 717         hnp-disable;
 718         over-current-active-low;
 719         power-active-high;
 720         srp-disable;
 721 };
 722
 723 /* On-module eMMC */
 724 &usdhc1 {
 725         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 726         pinctrl-0 = <&pinctrl_usdhc1>;
 727         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 728         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 729         bus-width = <8>;
 730         non-removable;
 731         status = "okay";
 732 };
 733
 734 /* Apalis MMC1 */
 735 &usdhc2 {
 736         pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
 737         pinctrl-0 = <&pinctrl_usdhc2_4bit>,
 738                     <&pinctrl_usdhc2_8bit>,
 739                     <&pinctrl_mmc1_cd>;
 740         pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>,
 741                     <&pinctrl_usdhc2_8bit_100mhz>,
 742                     <&pinctrl_mmc1_cd>;
 743         pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>,
 744                     <&pinctrl_usdhc2_8bit_200mhz>,
 745                     <&pinctrl_mmc1_cd>;
 746         pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>,
 747                     <&pinctrl_usdhc2_8bit_sleep>,
 748                     <&pinctrl_mmc1_cd_sleep>;
 749         bus-width = <8>;
 750         cd-gpios = <&lsio_gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */
 751         no-1-8-v;
 752 };
 753
 754 /* Apalis SD1 */
 755 &usdhc3 {
 756         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 757         pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>;
 758         pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_sd1_cd>;
 759         pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_sd1_cd>;
 760         bus-width = <4>;
 761         cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */
 762         no-1-8-v;
 763 };
 764
 765 /* Video Processing Unit */
 766 &vpu {
 767         compatible = "nxp,imx8qm-vpu";
 768         status = "okay";
 769 };
 770
 771 &vpu_core0 {
 772         reg = <0x2d080000 0x10000>;
 773         memory-region = <&decoder_boot>, <&decoder_rpc>;
 774         status = "okay";
 775 };
 776
 777 &vpu_core1 {
 778         reg = <0x2d090000 0x10000>;
 779         memory-region = <&encoder1_boot>, <&encoder1_rpc>;
 780         status = "okay";
 781 };
 782
 783 &vpu_core2 {
 784         reg = <0x2d0a0000 0x10000>;
 785         memory-region = <&encoder2_boot>, <&encoder2_rpc>;
 786         status = "okay";
 787 };
 788
 789 &iomuxc {
 790         pinctrl-names = "default";
 791         pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
 792                     <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
 793                     <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_keys>,
 794                     <&pinctrl_gpio_usbh_oc_n>, <&pinctrl_lpuart1ctrl>,
 795                     <&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>,
 796                     <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>,
 797                     <&pinctrl_mlb_gpios>, <&pinctrl_qspi1a_gpios>,
 798                     <&pinctrl_sata1_act>, <&pinctrl_sim0_gpios>,
 799                     <&pinctrl_usdhc1_gpios>;
 800
 801         /* Apalis AN1_ADC */
 802         pinctrl_adc0: adc0grp {
 803                 fsl,pins = /* Apalis AN1_ADC0 */
 804                            <IMX8QM_ADC_IN0_DMA_ADC0_IN0                         0xc0000060>,
 805                            /* Apalis AN1_ADC1 */
 806                            <IMX8QM_ADC_IN1_DMA_ADC0_IN1                         0xc0000060>,
 807                            /* Apalis AN1_ADC2 */
 808                            <IMX8QM_ADC_IN2_DMA_ADC0_IN2                         0xc0000060>,
 809                            /* Apalis AN1_TSWIP_ADC3 */
 810                            <IMX8QM_ADC_IN3_DMA_ADC0_IN3                         0xc0000060>;
 811         };
 812
 813         /* Apalis AN1_TS */
 814         pinctrl_adc1: adc1grp {
 815                 fsl,pins = /* Apalis AN1_TSPX */
 816                            <IMX8QM_ADC_IN4_DMA_ADC1_IN0                         0xc0000060>,
 817                            /* Apalis AN1_TSMX */
 818                            <IMX8QM_ADC_IN5_DMA_ADC1_IN1                         0xc0000060>,
 819                            /* Apalis AN1_TSPY */
 820                            <IMX8QM_ADC_IN6_DMA_ADC1_IN2                         0xc0000060>,
 821                            /* Apalis AN1_TSMY */
 822                            <IMX8QM_ADC_IN7_DMA_ADC1_IN3                         0xc0000060>;
 823         };
 824
 825         /* Apalis CAM1 */
 826         pinctrl_cam1_gpios: cam1gpiosgrp {
 827                 fsl,pins = /* Apalis CAM1_D7 */
 828                            <IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20           0x00000021>,
 829                            /* Apalis CAM1_D6 */
 830                            <IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21           0x00000021>,
 831                            /* Apalis CAM1_D5 */
 832                            <IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26                    0x00000021>,
 833                            /* Apalis CAM1_D4 */
 834                            <IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27                    0x00000021>,
 835                            /* Apalis CAM1_D3 */
 836                            <IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28                0x00000021>,
 837                            /* Apalis CAM1_D2 */
 838                            <IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29                0x00000021>,
 839                            /* Apalis CAM1_D1 */
 840                            <IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30                0x00000021>,
 841                            /* Apalis CAM1_D0 */
 842                            <IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31                0x00000021>,
 843                            /* Apalis CAM1_PCLK */
 844                            <IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00                     0x00000021>,
 845                            /* Apalis CAM1_MCLK */
 846                            <IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18                     0x00000021>,
 847                            /* Apalis CAM1_VSYNC */
 848                            <IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24                   0x00000021>,
 849                            /* Apalis CAM1_HSYNC */
 850                            <IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25                   0x00000021>;
 851         };
 852
 853         /* Apalis DAP1 */
 854         pinctrl_dap1_gpios: dap1gpiosgrp {
 855                 fsl,pins = /* Apalis DAP1_MCLK */
 856                            <IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19                     0x00000021>,
 857                            /* Apalis DAP1_D_OUT */
 858                            <IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12                     0x00000021>,
 859                            /* Apalis DAP1_RESET */
 860                            <IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07                   0x00000021>,
 861                            /* Apalis DAP1_BIT_CLK */
 862                            <IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06                     0x00000021>,
 863                            /* Apalis DAP1_D_IN */
 864                            <IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14                    0x00000021>,
 865                            /* Apalis DAP1_SYNC */
 866                            <IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11                     0x00000021>,
 867                            /* On-module Wi-Fi_I2S_EN# */
 868                            <IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13                0x00000021>;
 869         };
 870
 871         /* Apalis LCD1_G1+2 */
 872         pinctrl_esai0_gpios: esai0gpiosgrp {
 873                 fsl,pins = /* Apalis LCD1_G1 */
 874                            <IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22                    0x00000021>,
 875                            /* Apalis LCD1_G2 */
 876                            <IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23                    0x00000021>;
 877         };
 878
 879         /* On-module Gigabit Ethernet PHY Micrel KSZ9031 for Apalis GLAN */
 880         pinctrl_fec1: fec1grp {
 881                 fsl,pins = /* Use pads in 3.3V mode */
 882                            <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD                 0x000014a0>,
 883                            <IMX8QM_ENET0_MDC_CONN_ENET0_MDC                             0x06000020>,
 884                            <IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO                           0x06000020>,
 885                            <IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL           0x06000020>,
 886                            <IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC                 0x06000020>,
 887                            <IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0               0x06000020>,
 888                            <IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1               0x06000020>,
 889                            <IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2               0x06000020>,
 890                            <IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3               0x06000020>,
 891                            <IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC                 0x06000020>,
 892                            <IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL           0x06000020>,
 893                            <IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0               0x06000020>,
 894                            <IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1               0x06000020>,
 895                            <IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2               0x06000020>,
 896                            <IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3               0x06000020>,
 897                            <IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M     0x06000020>,
 898                            /* On-module ETH_RESET# */
 899                            <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11                         0x06000020>,
 900                            /* On-module ETH_INT# */
 901                            <IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29                   0x04000060>;
 902         };
 903
 904         pinctrl_fec1_sleep: fec1-sleepgrp {
 905                 fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD         0x000014a0>,
 906                            <IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14                    0x04000040>,
 907                            <IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13                   0x04000040>,
 908                            <IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31           0x04000040>,
 909                            <IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30              0x04000040>,
 910                            <IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00             0x04000040>,
 911                            <IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01             0x04000040>,
 912                            <IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02             0x04000040>,
 913                            <IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03             0x04000040>,
 914                            <IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04              0x04000040>,
 915                            <IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05           0x04000040>,
 916                            <IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06             0x04000040>,
 917                            <IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07             0x04000040>,
 918                            <IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08             0x04000040>,
 919                            <IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09             0x04000040>,
 920                            <IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15        0x04000040>,
 921                            <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11                 0x06000020>,
 922                            <IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29           0x04000040>;
 923         };
 924
 925         /* Apalis LCD1_ */
 926         pinctrl_fec2_gpios: fec2gpiosgrp {
 927                 fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD         0x000014a0>,
 928                            /* Apalis LCD1_R1 */
 929                            <IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18                    0x00000021>,
 930                            /* Apalis LCD1_R0 */
 931                            <IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17                   0x00000021>,
 932                            /* Apalis LCD1_G0 */
 933                            <IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16        0x00000021>,
 934                            /* Apalis LCD1_R7 */
 935                            <IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17           0x00000021>,
 936                            /* Apalis LCD1_DE */
 937                            <IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18             0x00000021>,
 938                            /* Apalis LCD1_HSYNC */
 939                            <IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19             0x00000021>,
 940                            /* Apalis LCD1_VSYNC */
 941                            <IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20             0x00000021>,
 942                            /* Apalis LCD1_PCLK */
 943                            <IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21             0x00000021>,
 944                            /* Apalis LCD1_R6 */
 945                            <IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11           0x00000021>,
 946                            /* Apalis LCD1_R5 */
 947                            <IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10              0x00000021>,
 948                            /* Apalis LCD1_R4 */
 949                            <IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12             0x00000021>,
 950                            /* Apalis LCD1_R3 */
 951                            <IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13             0x00000021>,
 952                            /* Apalis LCD1_R2 */
 953                            <IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14             0x00000021>;
 954         };
 955
 956         /* Apalis CAN1 */
 957         pinctrl_flexcan1: flexcan0grp {
 958                 fsl,pins = <IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX                  0x00000021>,
 959                            <IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX                  0x00000021>;
 960         };
 961
 962         /* Apalis CAN2 */
 963         pinctrl_flexcan2: flexcan1grp {
 964                 fsl,pins = <IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX                  0x00000021>,
 965                            <IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX                  0x00000021>;
 966         };
 967
 968         /* Apalis CAN3 (optional) */
 969         pinctrl_flexcan3: flexcan2grp {
 970                 fsl,pins = <IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX                  0x00000021>,
 971                            <IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX                  0x00000021>;
 972         };
 973
 974         /* Apalis GPIO1 */
 975         pinctrl_gpio1: gpio1grp {
 976                 fsl,pins = <IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08                 0x06000021>;
 977         };
 978
 979         /* Apalis GPIO2 */
 980         pinctrl_gpio2: gpio2grp {
 981                 fsl,pins = <IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09                 0x06000021>;
 982         };
 983
 984         /* Apalis GPIO3 */
 985         pinctrl_gpio3: gpio3grp {
 986                 fsl,pins = <IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12                 0x06000021>;
 987         };
 988
 989         /* Apalis GPIO4 */
 990         pinctrl_gpio4: gpio4grp {
 991                 fsl,pins = <IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13                 0x06000021>;
 992         };
 993
 994         /* Apalis GPIO5 */
 995         pinctrl_gpio5: gpio5grp {
 996                 fsl,pins = <IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01                  0x06000021>;
 997         };
 998
 999         /* Apalis GPIO6 */
1000         pinctrl_gpio6: gpio6grp {
1001                 fsl,pins = <IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02                  0x00000021>;
1002         };
1003
1004         /* Apalis GPIO7 */
1005         pinctrl_gpio7: gpio7grp {
1006                 fsl,pins = <IMX8QM_MLB_SIG_LSIO_GPIO3_IO26                      0x00000021>;
1007         };
1008
1009         /* Apalis GPIO8 */
1010         pinctrl_gpio8: gpio8grp {
1011                 fsl,pins = <IMX8QM_MLB_DATA_LSIO_GPIO3_IO28                     0x00000021>;
1012         };
1013
1014         /* Apalis BKL1_ON */
1015         pinctrl_gpio_bkl_on: gpiobklongrp {
1016                 fsl,pins = <IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04                 0x00000021>;
1017         };
1018
1019         /* Apalis WAKE1_MICO */
1020         pinctrl_gpio_keys: gpiokeysgrp {
1021                 fsl,pins = <IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20                     0x06700021>;
1022         };
1023
1024         /* Apalis USBH_OC# */
1025         pinctrl_gpio_usbh_oc_n: gpiousbhocngrp {
1026                 fsl,pins = <IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06                  0x04000021>;
1027         };
1028
1029         /* On-module HDMI_CTRL */
1030         pinctrl_hdmi_ctrl: hdmictrlgrp {
1031                 fsl,pins = <IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30           0x00000061>;
1032         };
1033
1034         /* On-module I2C */
1035         pinctrl_lpi2c1: lpi2c1grp {
1036                 fsl,pins = <IMX8QM_GPT0_CLK_DMA_I2C1_SCL                        0x04000020>,
1037                            <IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA                    0x04000020>;
1038         };
1039
1040         /* Apalis I2C1 */
1041         pinctrl_lpi2c2: lpi2c2grp {
1042                 fsl,pins = <IMX8QM_GPT1_CLK_DMA_I2C2_SCL                        0x04000020>,
1043                            <IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA                    0x04000020>;
1044         };
1045
1046         /* Apalis I2C3 (CAM) */
1047         pinctrl_lpi2c3: lpi2c3grp {
1048                 fsl,pins = <IMX8QM_SIM0_PD_DMA_I2C3_SCL                         0x04000020>,
1049                            <IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA                   0x04000020>;
1050         };
1051
1052         /* Apalis SPI1 */
1053         pinctrl_lpspi0: lpspi0grp {
1054                 fsl,pins = <IMX8QM_SPI0_SCK_DMA_SPI0_SCK                        0x0600004c>,
1055                            <IMX8QM_SPI0_SDO_DMA_SPI0_SDO                        0x0600004c>,
1056                            <IMX8QM_SPI0_SDI_DMA_SPI0_SDI                        0x0600004c>,
1057                            <IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05                     0x0600004c>;
1058         };
1059
1060         /* Apalis SPI2 */
1061         pinctrl_lpspi2: lpspi2grp {
1062                 fsl,pins = <IMX8QM_SPI2_SCK_DMA_SPI2_SCK                        0x0600004c>,
1063                            <IMX8QM_SPI2_SDO_DMA_SPI2_SDO                        0x0600004c>,
1064                            <IMX8QM_SPI2_SDI_DMA_SPI2_SDI                        0x0600004c>,
1065                            <IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10                     0x0600004c>;
1066         };
1067
1068         /* Apalis UART3 */
1069         pinctrl_lpuart0: lpuart0grp {
1070                 fsl,pins = <IMX8QM_UART0_RX_DMA_UART0_RX                        0x06000020>,
1071                            <IMX8QM_UART0_TX_DMA_UART0_TX                        0x06000020>;
1072         };
1073
1074         /* Apalis UART1 */
1075         pinctrl_lpuart1: lpuart1grp {
1076                 fsl,pins = <IMX8QM_UART1_RX_DMA_UART1_RX                        0x06000020>,
1077                            <IMX8QM_UART1_TX_DMA_UART1_TX                        0x06000020>,
1078                            <IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B                  0x06000020>,
1079                            <IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B                  0x06000020>;
1080         };
1081
1082         /* Apalis UART1 */
1083         pinctrl_lpuart1ctrl: lpuart1ctrlgrp {
1084                 fsl,pins = /* Apalis UART1_DTR */
1085                            <IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06                 0x00000021>,
1086                            /* Apalis UART1_DSR */
1087                            <IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07                 0x00000021>,
1088                            /* Apalis UART1_DCD */
1089                            <IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10                 0x00000021>,
1090                            /* Apalis UART1_RI */
1091                            <IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11                 0x00000021>;
1092         };
1093
1094         /* Apalis UART4 */
1095         pinctrl_lpuart2: lpuart2grp {
1096                 fsl,pins = <IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX                  0x06000020>,
1097                            <IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX                  0x06000020>;
1098         };
1099
1100         /* Apalis UART2 */
1101         pinctrl_lpuart3: lpuart3grp {
1102                 fsl,pins = <IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX                  0x06000020>,
1103                            <IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX                  0x06000020>,
1104                            <IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B             0x06000020>,
1105                            <IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B              0x06000020>;
1106         };
1107
1108         /* Apalis TS_2 */
1109         pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpiogrp {
1110                 fsl,pins = <IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06               0x00000021>;
1111         };
1112
1113         /* Apalis LCD1_G6+7 */
1114         pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp {
1115                 fsl,pins = /* Apalis LCD1_G6 */
1116                            <IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12               0x00000021>,
1117                            /* Apalis LCD1_G7 */
1118                            <IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13               0x00000021>;
1119         };
1120
1121         /* Apalis TS_3 */
1122         pinctrl_mipi_dsi_0_1_en: mipidsi0-1engrp {
1123                 fsl,pins = <IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07               0x00000021>;
1124         };
1125
1126         /* Apalis TS_4 */
1127         pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp {
1128                 fsl,pins = <IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22           0x00000021>;
1129         };
1130
1131         /* Apalis TS_1 */
1132         pinctrl_mlb_gpios: mlbgpiosgrp {
1133                 fsl,pins = <IMX8QM_MLB_CLK_LSIO_GPIO3_IO27                      0x00000021>;
1134         };
1135
1136         /* Apalis MMC1_CD# */
1137         pinctrl_mmc1_cd: mmc1cdgrp {
1138                 fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09                    0x00000021>;
1139         };
1140
1141         pinctrl_mmc1_cd_sleep: mmc1cdsleepgrp {
1142                 fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09                    0x04000021>;
1143         };
1144
1145         /* On-module PCIe_Wi-Fi */
1146         pinctrl_pcieb: pciebgrp {
1147                 fsl,pins = <IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30          0x00000021>,
1148                            <IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31            0x00000021>,
1149                            <IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00           0x00000021>;
1150         };
1151
1152         /* On-module PCIe_CLK_EN1 */
1153         pinctrl_pcie_sata_refclk: pciesatarefclkgrp {
1154                 fsl,pins = <IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11                    0x00000021>;
1155         };
1156
1157         /* On-module PCIe_CLK_EN2 */
1158         pinctrl_pcie_wifi_refclk: pciewifirefclkgrp {
1159                 fsl,pins = <IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11                0x00000021>;
1160         };
1161
1162         /* Apalis PWM3 */
1163         pinctrl_pwm0: pwm0grp {
1164                 fsl,pins = <IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT                    0x00000020>;
1165         };
1166
1167         /* Apalis PWM4 */
1168         pinctrl_pwm1: pwm1grp {
1169                 fsl,pins = <IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT                    0x00000020>;
1170         };
1171
1172         /* Apalis PWM1 */
1173         pinctrl_pwm2: pwm2grp {
1174                 fsl,pins = <IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT                   0x00000020>;
1175         };
1176
1177         /* Apalis PWM2 */
1178         pinctrl_pwm3: pwm3grp {
1179                 fsl,pins = <IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT                   0x00000020>;
1180         };
1181
1182         /* Apalis BKL1_PWM */
1183         pinctrl_pwm_bkl: pwmbklgrp {
1184                 fsl,pins = <IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT                  0x00000020>;
1185         };
1186
1187         /* Apalis LCD1_ */
1188         pinctrl_qspi1a_gpios: qspi1agpiosgrp {
1189                 fsl,pins = /* Apalis LCD1_B0 */
1190                            <IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26                 0x00000021>,
1191                            /* Apalis LCD1_B1 */
1192                            <IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25                 0x00000021>,
1193                            /* Apalis LCD1_B2 */
1194                            <IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24                 0x00000021>,
1195                            /* Apalis LCD1_B3 */
1196                            <IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23                 0x00000021>,
1197                            /* Apalis LCD1_B5 */
1198                            <IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22                   0x00000021>,
1199                            /* Apalis LCD1_B7 */
1200                            <IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21                  0x00000021>,
1201                            /* Apalis LCD1_B4 */
1202                            <IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19                 0x00000021>,
1203                            /* Apalis LCD1_B6 */
1204                            <IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20                 0x00000021>;
1205         };
1206
1207         /* On-module RESET_MOCI#_DRV */
1208         pinctrl_reset_moci: resetmocigrp {
1209                 fsl,pins = <IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30                 0x00000021>;
1210         };
1211
1212         /* On-module I2S SGTL5000 for Apalis Analogue Audio */
1213         pinctrl_sai1: sai1grp {
1214                 fsl,pins = <IMX8QM_SAI1_TXD_AUD_SAI1_TXD                        0xc600006c>,
1215                            <IMX8QM_SAI1_RXD_AUD_SAI1_RXD                        0xc600004c>,
1216                            <IMX8QM_SAI1_TXC_AUD_SAI1_TXC                        0xc600004c>,
1217                            <IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS                      0xc600004c>;
1218         };
1219
1220         /* Apalis SATA1_ACT# */
1221         pinctrl_sata1_act: sata1actgrp {
1222                 fsl,pins = <IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08                    0x00000021>;
1223         };
1224
1225         /* Apalis SD1_CD# */
1226         pinctrl_sd1_cd: sd1cdgrp {
1227                 fsl,pins = <IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12                  0x00000021>;
1228         };
1229
1230         /* On-module I2S SGTL5000 SYS_MCLK */
1231         pinctrl_sgtl5000: sgtl5000grp {
1232                 fsl,pins = <IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0                  0xc600004c>;
1233         };
1234
1235         /* Apalis LCD1_ */
1236         pinctrl_sim0_gpios: sim0gpiosgrp {
1237                 fsl,pins = /* Apalis LCD1_G5 */
1238                            <IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00                     0x00000021>,
1239                            /* Apalis LCD1_G3 */
1240                            <IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05                0x00000021>,
1241                            /* Apalis TS_5 */
1242                            <IMX8QM_SIM0_IO_LSIO_GPIO0_IO02                      0x00000021>,
1243                            /* Apalis LCD1_G4 */
1244                            <IMX8QM_SIM0_RST_LSIO_GPIO0_IO01                     0x00000021>;
1245         };
1246
1247         /* Apalis SPDIF */
1248         pinctrl_spdif0: spdif0grp {
1249                 fsl,pins = <IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX                      0xc6000040>,
1250                            <IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX                      0xc6000040>;
1251         };
1252
1253         pinctrl_touchctrl_gpios: touchctrlgpiosgrp {
1254                 fsl,pins = <IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04                    0x00000021>,
1255                            <IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05                    0x00000041>,
1256                            <IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17                     0x00000021>,
1257                            <IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21                     0x00000041>;
1258         };
1259
1260         pinctrl_touchctrl_idle: touchctrlidlegrp {
1261                 fsl,pins = <IMX8QM_ADC_IN4_LSIO_GPIO3_IO22                      0x00000021>,
1262                            <IMX8QM_ADC_IN5_LSIO_GPIO3_IO23                      0x00000021>,
1263                            <IMX8QM_ADC_IN6_LSIO_GPIO3_IO24                      0x00000021>,
1264                            <IMX8QM_ADC_IN7_LSIO_GPIO3_IO25                      0x00000021>;
1265         };
1266
1267         /* On-module USB HSIC HUB (active) */
1268         pinctrl_usb_hsic_active: usbh1activegrp {
1269                 fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA           0x000000cf>,
1270                            <IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE       0x000000ff>;
1271         };
1272
1273         /* On-module USB HSIC HUB (idle) */
1274         pinctrl_usb_hsic_idle: usbh1idlegrp {
1275                 fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA           0x000000cf>,
1276                            <IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE       0x000000cf>;
1277         };
1278
1279         /* On-module USB HSIC HUB */
1280         pinctrl_usb3503a: usb3503agrp {
1281                 fsl,pins = /* On-module HSIC_HUB_CONNECT */
1282                            <IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31                 0x00000041>,
1283                            /* On-module HSIC_INT_N */
1284                            <IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01                 0x00000021>,
1285                            /* On-module HSIC_RESET_N */
1286                            <IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02                 0x00000041>;
1287         };
1288
1289         /* Apalis USBH_EN */
1290         pinctrl_usbh_en: usbhengrp {
1291                 fsl,pins = <IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04                  0x00000021>;
1292         };
1293
1294         /* Apalis USBO1 */
1295         pinctrl_usbotg1: usbotg1grp {
1296                 fsl,pins = /* Apalis USBO1_EN */
1297                            <IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR                0x00000021>,
1298                            /* Apalis USBO1_OC# */
1299                            <IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC                 0x04000021>;
1300         };
1301
1302         /* On-module eMMC */
1303         pinctrl_usdhc1: usdhc1grp {
1304                 fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK                     0x06000041>,
1305                            <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD                     0x00000021>,
1306                            <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0                 0x00000021>,
1307                            <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1                 0x00000021>,
1308                            <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2                 0x00000021>,
1309                            <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3                 0x00000021>,
1310                            <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4                 0x00000021>,
1311                            <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5                 0x00000021>,
1312                            <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6                 0x00000021>,
1313                            <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7                 0x00000021>,
1314                            <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE               0x06000041>,
1315                            <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B             0x00000021>;
1316         };
1317
1318         pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1319                 fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK                     0x06000040>,
1320                            <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD                     0x00000020>,
1321                            <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0                 0x00000020>,
1322                            <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1                 0x00000020>,
1323                            <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2                 0x00000020>,
1324                            <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3                 0x00000020>,
1325                            <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4                 0x00000020>,
1326                            <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5                 0x00000020>,
1327                            <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6                 0x00000020>,
1328                            <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7                 0x00000020>,
1329                            <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE               0x06000040>,
1330                            <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B             0x00000020>;
1331         };
1332
1333         pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1334                 fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK                     0x06000040>,
1335                            <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD                     0x00000020>,
1336                            <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0                 0x00000020>,
1337                            <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1                 0x00000020>,
1338                            <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2                 0x00000020>,
1339                            <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3                 0x00000020>,
1340                            <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4                 0x00000020>,
1341                            <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5                 0x00000020>,
1342                            <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6                 0x00000020>,
1343                            <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7                 0x00000020>,
1344                            <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE               0x06000040>,
1345                            <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B             0x00000020>;
1346         };
1347
1348         /* Apalis TS_6 */
1349         pinctrl_usdhc1_gpios: usdhc1gpiosgrp {
1350                 fsl,pins = <IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23                0x00000021>;
1351         };
1352
1353         /* Apalis MMC1 */
1354         pinctrl_usdhc2_4bit: usdhc2grp4bitgrp {
1355                 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK                   0x06000041>,
1356                            <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD                   0x00000021>,
1357                            <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0               0x00000021>,
1358                            <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1               0x00000021>,
1359                            <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2               0x00000021>,
1360                            <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3               0x00000021>,
1361                            /* On-module PMIC use */
1362                            <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT           0x00000021>;
1363         };
1364
1365         pinctrl_usdhc2_4bit_100mhz: usdhc2-4bit100mhzgrp {
1366                 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK                   0x06000040>,
1367                            <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD                   0x00000020>,
1368                            <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0               0x00000020>,
1369                            <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1               0x00000020>,
1370                            <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2               0x00000020>,
1371                            <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3               0x00000020>,
1372                            /* On-module PMIC use */
1373                            <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT           0x00000021>;
1374         };
1375
1376         pinctrl_usdhc2_4bit_200mhz: usdhc2-4bit200mhzgrp {
1377                 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK                   0x06000040>,
1378                            <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD                   0x00000020>,
1379                            <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0               0x00000020>,
1380                            <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1               0x00000020>,
1381                            <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2               0x00000020>,
1382                            <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3               0x00000020>,
1383                            /* On-module PMIC use */
1384                            <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT           0x00000021>;
1385         };
1386
1387         pinctrl_usdhc2_8bit: usdhc2grp8bitgrp {
1388                 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4               0x00000021>,
1389                            <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5               0x00000021>,
1390                            <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6               0x00000021>,
1391                            <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7               0x00000021>;
1392         };
1393
1394         pinctrl_usdhc2_8bit_100mhz: usdhc2-8bit100mhzgrp {
1395                 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4               0x00000020>,
1396                            <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5               0x00000020>,
1397                            <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6               0x00000020>,
1398                            <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7               0x00000020>;
1399         };
1400
1401         pinctrl_usdhc2_8bit_200mhz: usdhc2-8bit200mhzgrp {
1402                 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4               0x00000020>,
1403                            <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5               0x00000020>,
1404                            <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6               0x00000020>,
1405                            <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7               0x00000020>;
1406         };
1407
1408         pinctrl_usdhc2_4bit_sleep: usdhc2-4bitsleepgrp {
1409                 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK                   0x04000061>,
1410                            <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD                   0x04000061>,
1411                            <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0               0x04000061>,
1412                            <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1               0x04000061>,
1413                            <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2               0x04000061>,
1414                            <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3               0x04000061>,
1415                            /* On-module PMIC use */
1416                            <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT           0x00000021>;
1417         };
1418
1419         pinctrl_usdhc2_8bit_sleep: usdhc2-8bitsleepgrp {
1420                 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4               0x04000061>,
1421                            <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5               0x04000061>,
1422                            <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6               0x04000061>,
1423                            <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7               0x04000061>;
1424         };
1425
1426         /* Apalis SD1 */
1427         pinctrl_usdhc3: usdhc3grp {
1428                 fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK                   0x06000041>,
1429                            <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD                   0x00000021>,
1430                            <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0               0x00000021>,
1431                            <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1               0x00000021>,
1432                            <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2               0x00000021>,
1433                            <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3               0x00000021>,
1434                            /* On-module PMIC use */
1435                            <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT           0x00000021>;
1436         };
1437
1438         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1439                 fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK                   0x06000041>,
1440                            <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD                   0x00000021>,
1441                            <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0               0x00000021>,
1442                            <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1               0x00000021>,
1443                            <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2               0x00000021>,
1444                            <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3               0x00000021>,
1445                            /* On-module PMIC use */
1446                            <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT           0x00000021>;
1447         };
1448
1449         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1450                 fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK                   0x06000041>,
1451                            <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD                   0x00000021>,
1452                            <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0               0x00000021>,
1453                            <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1               0x00000021>,
1454                            <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2               0x00000021>,
1455                            <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3               0x00000021>,
1456                            /* On-module PMIC use */
1457                            <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT           0x00000021>;
1458         };
1459
1460         /* On-module Wi-Fi */
1461         pinctrl_wifi: wifigrp {
1462                 fsl,pins = /* On-module Wi-Fi_SUSCLK_32k */
1463                            <IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K    0x06000021>,
1464                            /* On-module Wi-Fi_PCIE_W_DISABLE */
1465                            <IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24           0x06000021>;
1466         };
1467
1468         pinctrl_wifi_pdn: wifipdngrp {
1469                 fsl,pins = /* On-module Wi-Fi_POWER_DOWN */
1470                            <IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28           0x06000021>;
1471         };
1472 };