1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree file for LX2162AQDS
9 #include "fsl-lx2160a.dtsi"
12 model = "NXP Layerscape LX2162AQDS";
13 compatible = "fsl,lx2162a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "LTM4619-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
34 compatible = "mdio-mux-multiplexer";
35 mux-controls = <&mux 0>;
36 mdio-parent-bus = <&emdio1>;
40 mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */
45 rgmii_phy1: ethernet-phy@1 {
46 compatible = "ethernet-phy-id001c.c916";
52 mdio@8 { /* On-board RTL8211F PHY #2 RGMII2 */
57 rgmii_phy2: ethernet-phy@2 {
58 compatible = "ethernet-phy-id001c.c916";
64 mdio@18 { /* Slot #1 */
70 mdio@19 { /* Slot #2 */
76 mdio@1a { /* Slot #3 */
82 mdio@1b { /* Slot #4 */
88 mdio@1c { /* Slot #5 */
94 mdio@1d { /* Slot #6 */
100 mdio@1e { /* Slot #7 */
102 #address-cells = <1>;
106 mdio@1f { /* Slot #8 */
108 #address-cells = <1>;
114 compatible = "mdio-mux-multiplexer";
115 mux-controls = <&mux 1>;
116 mdio-parent-bus = <&emdio2>;
117 #address-cells = <1>;
120 mdio@0 { /* Slot #1 (secondary EMI) */
122 #address-cells = <1>;
126 mdio@1 { /* Slot #2 (secondary EMI) */
128 #address-cells = <1>;
132 mdio@2 { /* Slot #3 (secondary EMI) */
134 #address-cells = <1>;
138 mdio@3 { /* Slot #4 (secondary EMI) */
140 #address-cells = <1>;
144 mdio@4 { /* Slot #5 (secondary EMI) */
146 #address-cells = <1>;
150 mdio@5 { /* Slot #6 (secondary EMI) */
152 #address-cells = <1>;
156 mdio@6 { /* Slot #7 (secondary EMI) */
158 #address-cells = <1>;
162 mdio@7 { /* Slot #8 (secondary EMI) */
164 #address-cells = <1>;
183 phy-handle = <&rgmii_phy1>;
184 phy-connection-type = "rgmii-id";
188 phy-handle = <&rgmii_phy2>;
189 phy-connection-type = "rgmii-id";
196 #address-cells = <1>;
198 compatible = "jedec,spi-nor";
200 spi-max-frequency = <1000000>;
208 #address-cells = <1>;
210 compatible = "jedec,spi-nor";
212 spi-max-frequency = <1000000>;
220 #address-cells = <1>;
222 compatible = "jedec,spi-nor";
224 spi-max-frequency = <1000000>;
254 mt35xu512aba0: flash@0 {
255 #address-cells = <1>;
257 compatible = "jedec,spi-nor";
259 spi-max-frequency = <50000000>;
261 spi-rx-bus-width = <8>;
262 spi-tx-bus-width = <8>;
270 compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
274 mux: mux-controller {
275 compatible = "reg-mux";
276 #mux-control-cells = <1>;
277 mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
278 <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
283 compatible = "nxp,pca9547";
285 #address-cells = <1>;
289 #address-cells = <1>;
294 compatible = "ti,ina220";
296 shunt-resistor = <500>;
300 compatible = "ti,ina220";
302 shunt-resistor = <1000>;
307 #address-cells = <1>;
311 temperature-sensor@4c {
312 compatible = "nxp,sa56004";
314 vcc-supply = <&sb_3v3>;
318 compatible = "nxp,pcf2129";
320 /* IRQ_RTC_B -> IRQ11_B(CPLD) -> IRQ11(CPU), active low */
321 interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>;