1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree file for LX2162A Clearfog
5 // Copyright 2023 Josua Mayer <josua@solid-run.com>
9 #include "fsl-lx2160a.dtsi"
10 #include "fsl-lx2162a-sr-som.dtsi"
13 model = "SolidRun LX2162A Clearfog";
14 compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a";
34 stdout-path = "serial0:115200n8";
38 compatible = "gpio-leds";
40 led_sfp_at: led-sfp-at {
41 gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */
42 default-state = "off";
45 led_sfp_ab: led-sfp-ab {
46 gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */
47 default-state = "off";
50 led_sfp_bt: led-sfp-bt {
51 gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */
52 default-state = "off";
55 led_sfp_bb: led-sfp-bb {
56 gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */
57 default-state = "off";
62 compatible = "sff,sfp";
63 i2c-bus = <&sfp_i2c0>;
64 mod-def0-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; /* EVT4_B */
65 maximum-power-milliwatt = <2000>;
69 compatible = "sff,sfp";
70 i2c-bus = <&sfp_i2c1>;
71 mod-def0-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; /* PROC_IRQ1 */
72 maximum-power-milliwatt = <2000>;
76 compatible = "sff,sfp";
77 i2c-bus = <&sfp_i2c2>;
78 mod-def0-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* PROC_IRQ10 */
79 maximum-power-milliwatt = <2000>;
83 compatible = "sff,sfp";
84 i2c-bus = <&sfp_i2c3>;
85 mod-def0-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; /* EVT3_B */
86 maximum-power-milliwatt = <2000>;
92 managed = "in-band-status";
98 managed = "in-band-status";
104 managed = "in-band-status";
105 phys = <&serdes_1 5>;
110 managed = "in-band-status";
111 phys = <&serdes_1 4>;
115 phys = <&serdes_2 0>;
116 phy-handle = <ðernet_phy3>;
117 phy-connection-type = "sgmii";
122 phys = <&serdes_2 1>;
123 phy-handle = <ðernet_phy1>;
124 phy-connection-type = "sgmii";
129 phys = <&serdes_2 6>;
130 phy-handle = <ðernet_phy6>;
131 phy-connection-type = "sgmii";
136 phys = <&serdes_2 7>;
137 phy-handle = <ðernet_phy8>;
138 phy-connection-type = "sgmii";
143 phys = <&serdes_2 4>;
144 phy-handle = <ðernet_phy4>;
145 phy-connection-type = "sgmii";
150 phys = <&serdes_2 5>;
151 phy-handle = <ðernet_phy2>;
152 phy-connection-type = "sgmii";
157 /* override connection to on-SoM phy */
158 /delete-property/ phy-handle;
159 /delete-property/ phy-connection-type;
161 phys = <&serdes_2 2>;
162 phy-handle = <ðernet_phy5>;
163 phy-connection-type = "sgmii";
168 phys = <&serdes_2 3>;
169 phy-handle = <ðernet_phy7>;
170 phy-connection-type = "sgmii";
175 ethernet_phy1: ethernet-phy@8 {
176 compatible = "ethernet-phy-ieee802.3-c45";
181 ethernet_phy2: ethernet-phy@9 {
182 compatible = "ethernet-phy-ieee802.3-c45";
187 ethernet_phy3: ethernet-phy@10 {
188 compatible = "ethernet-phy-ieee802.3-c45";
193 ethernet_phy4: ethernet-phy@11 {
194 compatible = "ethernet-phy-ieee802.3-c45";
199 ethernet_phy5: ethernet-phy@12 {
200 compatible = "ethernet-phy-ieee802.3-c45";
205 ethernet_phy6: ethernet-phy@13 {
206 compatible = "ethernet-phy-ieee802.3-c45";
211 ethernet_phy7: ethernet-phy@14 {
212 compatible = "ethernet-phy-ieee802.3-c45";
217 ethernet_phy8: ethernet-phy@15 {
218 compatible = "ethernet-phy-ieee802.3-c45";
234 * SoM has a phy at address 1 connected to SoC Ethernet Controller 1.
235 * It competes for WRIOP MAC17, and no connector has been wired.
246 compatible = "nxp,pca9546";
248 #address-cells = <1>;
250 i2c-mux-idle-disconnect;
253 #address-cells = <1>;
259 #address-cells = <1>;
265 #address-cells = <1>;
271 #address-cells = <1>;
278 compatible = "nxp,pca9546";
280 #address-cells = <1>;
282 i2c-mux-idle-disconnect;
285 #address-cells = <1>;
291 #address-cells = <1>;
297 #address-cells = <1>;
301 /* clock-controller@6b */